coreboot-gerrit May 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: sb/intel/i82801gx: Consolidate interrupt routing
by Arthur Heymans (Code Review) 02 May '17

02 May '17

Hello Vladimir Serbinenko, Paul Menzel, build bot (Jenkins), coreboot org, I'd like you to reexamine a change. Please visit https://review.coreboot.org/19017 to look at the new patch set (#7). Change subject: sb/intel/i82801gx: Consolidate interrupt routing ...................................................................... sb/intel/i82801gx: Consolidate interrupt routing The current code tries to make routing per-board, presumably for optimizing IRQ balancing but instead fails at providing an error-free default. Rewrite in unified and simplified way at the cost of minor performance hit on very old OS. This is set up similar to newer Intel PCH where a sane default is provided by coreboot. Change-Id: I46838d2249c6fefedf9e2c63ade0812d22e7d627 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/apple/macbook21/Kconfig D src/mainboard/apple/macbook21/acpi/i945_pci_irqs.asl M src/mainboard/apple/macbook21/devicetree.cb M src/mainboard/apple/macbook21/romstage.c M src/mainboard/asus/p5gc-mx/Kconfig D src/mainboard/asus/p5gc-mx/acpi/i945_pci_irqs.asl M src/mainboard/asus/p5gc-mx/devicetree.cb M src/mainboard/getac/p470/Kconfig M src/mainboard/getac/p470/devicetree.cb M src/mainboard/getac/p470/romstage.c D src/mainboard/gigabyte/ga-945gcm-s2l/acpi/i945_pci_irqs.asl M src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c M src/mainboard/gigabyte/ga-g41m-es2l/Kconfig D src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl M src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c M src/mainboard/ibase/mb899/Kconfig D src/mainboard/ibase/mb899/acpi/i945_pci_irqs.asl M src/mainboard/ibase/mb899/devicetree.cb M src/mainboard/ibase/mb899/romstage.c M src/mainboard/intel/d510mo/Kconfig D src/mainboard/intel/d510mo/acpi/pineview_pci_irqs.asl M src/mainboard/intel/d510mo/devicetree.cb M src/mainboard/intel/d510mo/romstage.c M src/mainboard/intel/d945gclf/Kconfig D src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl M src/mainboard/intel/d945gclf/devicetree.cb M src/mainboard/intel/d945gclf/romstage.c M src/mainboard/kontron/986lcd-m/Kconfig D src/mainboard/kontron/986lcd-m/acpi/i945_pci_irqs.asl M src/mainboard/kontron/986lcd-m/devicetree.cb M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/lenovo/t60/Kconfig D src/mainboard/lenovo/t60/acpi/i945_pci_irqs.asl M src/mainboard/lenovo/t60/devicetree.cb M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/x60/Kconfig D src/mainboard/lenovo/x60/acpi/i945_pci_irqs.asl M src/mainboard/lenovo/x60/devicetree.cb M src/mainboard/lenovo/x60/romstage.c M src/mainboard/roda/rk886ex/Kconfig D src/mainboard/roda/rk886ex/acpi/i945_pci_irqs.asl M src/mainboard/roda/rk886ex/devicetree.cb M src/mainboard/roda/rk886ex/romstage.c M src/northbridge/intel/i945/acpi/hostbridge.asl M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/i945/i945.h M src/northbridge/intel/pineview/acpi/hostbridge.asl M src/northbridge/intel/pineview/early_init.c M src/northbridge/intel/x4x/acpi/hostbridge.asl M src/northbridge/intel/x4x/early_init.c M src/southbridge/intel/i82801gx/acpi/ich7.asl R src/southbridge/intel/i82801gx/acpi/irq.asl M src/southbridge/intel/i82801gx/chip.h M src/southbridge/intel/i82801gx/early_lpc.c M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801gx/lpc.c 58 files changed, 390 insertions(+), 1,221 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/19017/7 -- To view, visit https://review.coreboot.org/19017 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I46838d2249c6fefedf9e2c63ade0812d22e7d627 Gerrit-PatchSet: 7 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com>

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Change in coreboot[master]: mb/gigabyte/ga-b75m-d3h: add libgfxinit support
by Arthur Heymans (Code Review) 02 May '17

02 May '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/19522 ) Change subject: mb/gigabyte/ga-b75m-d3h: add libgfxinit support ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/19522/3//COMMIT_MSG Commit Message: PS3, Line 9: only on port HDMI1 What happens on the DVI and Analog port? Maybe you can compile with ada debug and create a bug report if that does not work? -- To view, visit https://review.coreboot.org/19522 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: If00a7247df0c32b3d1f489fb92d86baaa8fdf8ba Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Anonymous Coward #1001586 Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: Yes

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Change in coreboot[master]: mb/lenovo/s230u: fix sata port map for the msata port
by Arthur Heymans (Code Review) 02 May '17

02 May '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/19523 ) Change subject: mb/lenovo/s230u: fix sata port map for the msata port ...................................................................... Patch Set 3: (2 comments) https://review.coreboot.org/#/c/19523/3//COMMIT_MSG Commit Message: PS3, Line 10: 1 & 4 0 & 4 PS3, Line 11: port 1 & 3 0 & 2 -- To view, visit https://review.coreboot.org/19523 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I1e9e96f0d0849b1e8c4e02aa4f686ceb5e10b3ab Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Anonymous Coward #1001586 Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/common/block: Add Intel XDCI code support
by Barnali Sarkar (Code Review) 02 May '17

02 May '17

Barnali Sarkar has posted comments on this change. ( https://review.coreboot.org/19428 ) Change subject: soc/intel/common/block: Add Intel XDCI code support ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/19428 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I9cbc686a00c26b92be2847b6bd6c2e5aa5a690f7 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: Use intel/common/xhci driver
by Barnali Sarkar (Code Review) 02 May '17

02 May '17

Barnali Sarkar has posted comments on this change. ( https://review.coreboot.org/19427 ) Change subject: soc/intel/apollolake: Use intel/common/xhci driver ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/19427 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Iccb6b6c8c002701d17444fcf62ec11315e5aeed9 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: Use XDCI common code
by Barnali Sarkar (Code Review) 02 May '17

02 May '17

Barnali Sarkar has posted comments on this change. ( https://review.coreboot.org/19429 ) Change subject: soc/intel/apollolake: Use XDCI common code ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/19429 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I4649bffe1bb90d7df6a72b5334793bf8f0fdbaeb Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: Clean up code by using common FAST_SPI...
by Furquan Shaikh (Code Review) 02 May '17

02 May '17

Furquan Shaikh has submitted this change and it was merged. ( https://review.coreboot.org/19080 ) Change subject: soc/intel/apollolake: Clean up code by using common FAST_SPI module ...................................................................... soc/intel/apollolake: Clean up code by using common FAST_SPI module This patch currently contains the following - 1. Use SOC_INTEL_COMMON_BLOCK_FAST_SPI kconfig for common FAST_SPI code. 2. Perform FAST_SPI programming by calling APIs from common FAST_SPI library. 3. Use common FAST_SPI header file. Change-Id: Ifd72734dadda541fe4c828e4f1716e532ec69c27 Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> Reviewed-on: https://review.coreboot.org/19080 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/apollolake/bootblock/bootblock.c M src/soc/intel/apollolake/chip.c D src/soc/intel/apollolake/flash_ctrlr.c D src/soc/intel/apollolake/include/soc/flash_ctrlr.h M src/soc/intel/apollolake/mmap_boot.c M src/soc/intel/apollolake/romstage.c 8 files changed, 9 insertions(+), 540 deletions(-) Approvals: Aaron Durbin: Looks good to me, approved Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 852dfad..d60f85e 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -54,6 +54,7 @@ select SOC_INTEL_COMMON_ACPI select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_ITSS select SOC_INTEL_COMMON_BLOCK_LPSS select SOC_INTEL_COMMON_BLOCK_PCR diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 1d5bac8..36455f3 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -11,7 +11,6 @@ bootblock-y += bootblock/bootblock.c bootblock-y += bootblock/bootblock.c bootblock-y += car.c -bootblock-y += flash_ctrlr.c bootblock-y += gpio.c bootblock-y += heci.c bootblock-y += lpc_lib.c @@ -24,7 +23,6 @@ romstage-y += car.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c -romstage-y += flash_ctrlr.c romstage-y += gpio.c romstage-y += heci.c romstage-y += i2c_early.c @@ -38,7 +36,6 @@ romstage-y += reset.c romstage-y += spi.c -smm-y += flash_ctrlr.c smm-y += mmap_boot.c smm-y += pmutil.c smm-y += gpio.c @@ -52,7 +49,6 @@ ramstage-y += chip.c ramstage-y += cse.c ramstage-y += elog.c -ramstage-y += flash_ctrlr.c ramstage-y += dsp.c ramstage-y += gpio.c ramstage-y += graphics.c @@ -79,7 +75,6 @@ ramstage-y += xhci.c ramstage-y += sd.c -postcar-y += flash_ctrlr.c postcar-y += memmap.c postcar-y += mmap_boot.c postcar-y += spi.c @@ -89,7 +84,6 @@ postcar-$(CONFIG_FSP_CAR) += exit_car_fsp.S verstage-y += car.c -verstage-y += flash_ctrlr.c verstage-y += i2c_early.c verstage-y += heci.c verstage-y += memmap.c diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 8a56890..2c98be4 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -18,13 +18,13 @@ #include <bootblock_common.h> #include <cpu/x86/mtrr.h> #include <device/pci.h> +#include <intelblocks/fast_spi.h> #include <intelblocks/pcr.h> -#include <intelblocks/systemagent.h> #include <intelblocks/rtc.h> +#include <intelblocks/systemagent.h> #include <lib.h> #include <soc/iomap.h> #include <soc/cpu.h> -#include <soc/flash_ctrlr.h> #include <soc/gpio.h> #include <soc/mmap_boot.h> #include <soc/systemagent.h> @@ -92,35 +92,6 @@ set_var_mtrr(mtrr, 4ULL*GiB - rom_size, rom_size, MTRR_TYPE_WRPROT); } -/* - * Program temporary BAR for SPI in case any of the stages before ramstage need - * to access SPI MMIO regs. Ramstage will assign a new BAR during PCI - * enumeration. - */ -static void enable_spibar(void) -{ - device_t dev = PCH_DEV_SPI; - uint8_t val; - - /* Disable Bus Master and MMIO space. */ - val = pci_read_config8(dev, PCI_COMMAND); - val &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - pci_write_config8(dev, PCI_COMMAND, val); - - /* Program Temporary BAR for SPI */ - pci_write_config32(dev, PCI_BASE_ADDRESS_0, - PRERAM_SPI_BASE_ADDRESS | - PCI_BASE_ADDRESS_SPACE_MEMORY); - - /* Enable Bus Master and MMIO Space */ - val = pci_read_config8(dev, PCI_COMMAND); - val |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config8(dev, PCI_COMMAND, val); - - /* Initialize SPI to allow BIOS to write/erase on flash. */ - spi_flash_init(); -} - static void enable_pmcbar(void) { device_t pmc = PCH_DEV_PMC; @@ -152,7 +123,7 @@ enable_pm_timer_emulation(); - enable_spibar(); + fast_spi_early_init(PRERAM_SPI_BASE_ADDRESS); cache_bios_region(); diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 3108987..5211f84 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -24,6 +24,7 @@ #include <cpu/x86/mp.h> #include <device/device.h> #include <device/pci.h> +#include <intelblocks/fast_spi.h> #include <fsp/api.h> #include <fsp/util.h> #include <intelblocks/itss.h> @@ -31,7 +32,6 @@ #include <soc/iomap.h> #include <soc/itss.h> #include <soc/cpu.h> -#include <soc/flash_ctrlr.h> #include <soc/intel/common/vbt.h> #include <soc/nvs.h> #include <soc/pci_devs.h> @@ -578,7 +578,7 @@ */ static void spi_flash_init_cb(void *unused) { - spi_flash_init(); + fast_spi_init(); } BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_flash_init_cb, NULL); diff --git a/src/soc/intel/apollolake/flash_ctrlr.c b/src/soc/intel/apollolake/flash_ctrlr.c deleted file mode 100644 index 95f540c..0000000 --- a/src/soc/intel/apollolake/flash_ctrlr.c +++ /dev/null @@ -1,391 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Intel Corp. - * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define __SIMPLE_DEVICE__ - -#include <arch/early_variables.h> -#include <arch/io.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <soc/flash_ctrlr.h> -#include <soc/intel/common/spi_flash.h> -#include <soc/pci_devs.h> -#include <spi_flash.h> -#include <spi-generic.h> -#include <stdlib.h> -#include <string.h> - -/* Helper to create a SPI context on API entry. */ -#define BOILERPLATE_CREATE_CTX(ctx) \ - struct spi_flash_ctx real_ctx; \ - struct spi_flash_ctx *ctx = &real_ctx; \ - _get_spi_flash_ctx(ctx) - -/* - * Anything that's not success is <0. Provided solely for readability, as these - * constants are not used outside this file. - */ -enum errors { - SUCCESS = 0, - E_NOT_IMPLEMENTED = -1, - E_TIMEOUT = -2, - E_HW_ERROR = -3, - E_ARGUMENT = -4, -}; - -/* Reduce data-passing burden by grouping transaction data in a context. */ -struct spi_flash_ctx { - uintptr_t mmio_base; - device_t pci_dev; - uint32_t hsfsts_on_last_error; -}; - -static void _get_spi_flash_ctx(struct spi_flash_ctx *ctx) -{ - uint32_t bar; - - /* FIXME: use device definition */ - ctx->pci_dev = PCH_DEV_SPI; - - bar = pci_read_config32(ctx->pci_dev, PCI_BASE_ADDRESS_0); - ctx->mmio_base = bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; - ctx->hsfsts_on_last_error = 0; -} - -/* Read register from the SPI flash controller. 'reg' is the register offset. */ -static uint32_t _spi_flash_ctrlr_reg_read(struct spi_flash_ctx *ctx, - uint16_t reg) -{ - uintptr_t addr = ALIGN_DOWN(ctx->mmio_base + reg, 4); - return read32((void *)addr); -} - -uint32_t spi_flash_ctrlr_reg_read(uint16_t reg) -{ - BOILERPLATE_CREATE_CTX(ctx); - return _spi_flash_ctrlr_reg_read(ctx, reg); -} - -/* Write to register in SPI flash controller. 'reg' is the register offset. */ -static void _spi_flash_ctrlr_reg_write(struct spi_flash_ctx *ctx, uint16_t reg, - uint32_t val) -{ - uintptr_t addr = ALIGN_DOWN(ctx->mmio_base + reg, 4); - write32((void *)addr, val); - -} - -/* - * The hardware datasheet is not clear on what HORD values actually do. It - * seems that HORD_SFDP provides access to the first 8 bytes of the SFDP, which - * is the signature and revision fields. HORD_JEDEC provides access to the - * actual flash parameters, and is most likely what you want to use when - * probing the flash from software. - * It's okay to rely on SFPD, since the SPI flash controller requires an SFDP - * 1.5 or newer compliant SPI flash chip. - * NOTE: Due to the register layout of the hardware, all accesses will be - * aligned to a 4 byte boundary. - */ -static uint32_t read_spi_flash_sfdp_param(struct spi_flash_ctx *ctx, - uint16_t sfdp_reg) -{ - uint32_t ptinx_index = sfdp_reg & SPIBAR_PTINX_IDX_MASK; - _spi_flash_ctrlr_reg_write(ctx, SPIBAR_PTINX, - ptinx_index | SPIBAR_PTINX_HORD_JEDEC); - return _spi_flash_ctrlr_reg_read(ctx, SPIBAR_PTDATA); -} - -/* Fill FDATAn FIFO in preparation for a write transaction. */ -static void fill_xfer_fifo(struct spi_flash_ctx *ctx, const void *data, - size_t len) -{ - len = min(len, SPIBAR_FDATA_FIFO_SIZE); - - /* YES! memcpy() works. FDATAn does not require 32-bit accesses. */ - memcpy((void *)(ctx->mmio_base + SPIBAR_FDATA(0)), data, len); -} - -/* Drain FDATAn FIFO after a read transaction populates data. */ -static void drain_xfer_fifo(struct spi_flash_ctx *ctx, void *dest, size_t len) -{ - len = min(len, SPIBAR_FDATA_FIFO_SIZE); - - /* YES! memcpy() works. FDATAn does not require 32-bit accesses. */ - memcpy(dest, (void *)(ctx->mmio_base + SPIBAR_FDATA(0)), len); -} - -/* Fire up a transfer using the hardware sequencer. */ -static void start_hwseq_xfer(struct spi_flash_ctx *ctx, uint32_t hsfsts_cycle, - uint32_t flash_addr, size_t len) -{ - /* Make sure all W1C status bits get cleared. */ - uint32_t hsfsts = SPIBAR_HSFSTS_W1C_BITS; - /* Set up transaction parameters. */ - hsfsts |= hsfsts_cycle & SPIBAR_HSFSTS_FCYCLE_MASK; - hsfsts |= SPIBAR_HSFSTS_FBDC(len - 1); - - _spi_flash_ctrlr_reg_write(ctx, SPIBAR_FADDR, flash_addr); - _spi_flash_ctrlr_reg_write(ctx, SPIBAR_HSFSTS_CTL, - hsfsts | SPIBAR_HSFSTS_FGO); -} - -static void print_xfer_error(struct spi_flash_ctx *ctx, - const char *failure_reason, uint32_t flash_addr) -{ - printk(BIOS_ERR, "SPI Transaction %s at flash offset %x.\n" - "\tHSFSTS = 0x%08x\n", - failure_reason, flash_addr, ctx->hsfsts_on_last_error); -} - -static int wait_for_hwseq_xfer(struct spi_flash_ctx *ctx) -{ - uint32_t hsfsts; - do { - hsfsts = _spi_flash_ctrlr_reg_read(ctx, SPIBAR_HSFSTS_CTL); - - if (hsfsts & SPIBAR_HSFSTS_FCERR) { - ctx->hsfsts_on_last_error = hsfsts; - return E_HW_ERROR; - } - /* TODO: set up timer and abort on timeout */ - } while (!(hsfsts & SPIBAR_HSFSTS_FDONE)); - - return SUCCESS; -} - -/* Execute SPI flash transfer. This is a blocking call. */ -static int exec_sync_hwseq_xfer(struct spi_flash_ctx *ctx, - uint32_t hsfsts_cycle, uint32_t flash_addr, - size_t len) -{ - int ret; - start_hwseq_xfer(ctx, hsfsts_cycle, flash_addr, len); - ret = wait_for_hwseq_xfer(ctx); - if (ret != SUCCESS) { - const char *reason = (ret == E_TIMEOUT) ? "timeout" : "error"; - print_xfer_error(ctx, reason, flash_addr); - } - return ret; -} - -unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) -{ - return MIN(buf_len, SPIBAR_FDATA_FIFO_SIZE); -} - -/* - * Write-protection status for BIOS region (BIOS_CONTROL register): - * EISS/WPD bits 00 01 10 11 - * -- -- -- -- - * normal mode RO RW RO RO - * SMM mode RO RW RO RW - */ -void spi_flash_init(void) -{ - uint32_t bios_ctl; - - BOILERPLATE_CREATE_CTX(ctx); - - bios_ctl = pci_read_config32(ctx->pci_dev, SPIBAR_BIOS_CONTROL); - bios_ctl |= SPIBAR_BIOS_CONTROL_WPD; - bios_ctl &= ~SPIBAR_BIOS_CONTROL_EISS; - - /* Enable Prefetching and caching. */ - bios_ctl |= SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE; - bios_ctl &= ~SPIBAR_BIOS_CONTROL_CACHE_DISABLE; - - pci_write_config32(ctx->pci_dev, SPIBAR_BIOS_CONTROL, bios_ctl); -} - -/* Flash device operations. */ -static struct spi_flash boot_flash CAR_GLOBAL; - -static int nuclear_spi_flash_erase(const struct spi_flash *flash, - uint32_t offset, size_t len) -{ - int ret; - size_t erase_size; - uint32_t erase_cycle; - - BOILERPLATE_CREATE_CTX(ctx); - - if (!IS_ALIGNED(offset, 4 * KiB) || !IS_ALIGNED(len, 4 * KiB)) { - printk(BIOS_ERR, "BUG! SPI erase region not sector aligned.\n"); - return E_ARGUMENT; - } - - while (len) { - if (IS_ALIGNED(offset, 64 * KiB) && (len >= 64 * KiB)) { - erase_size = 64 * KiB; - erase_cycle = SPIBAR_HSFSTS_CYCLE_64K_ERASE; - } else { - erase_size = 4 * KiB; - erase_cycle = SPIBAR_HSFSTS_CYCLE_4K_ERASE; - } - printk(BIOS_SPEW, "Erasing flash addr %x + %zu KiB\n", - offset, erase_size / KiB); - - ret = exec_sync_hwseq_xfer(ctx, erase_cycle, offset, 0); - if (ret != SUCCESS) - return ret; - - offset += erase_size; - len -= erase_size; - } - - return SUCCESS; -} - -/* - * Ensure read/write xfer len is not greater than SPIBAR_FDATA_FIFO_SIZE and - * that the operation does not cross 256-byte boundary. - */ -static size_t get_xfer_len(uint32_t addr, size_t len) -{ - size_t xfer_len = min(len, SPIBAR_FDATA_FIFO_SIZE); - size_t bytes_left = ALIGN_UP(addr, 256) - addr; - - if (bytes_left) - xfer_len = min(xfer_len, bytes_left); - - return xfer_len; -} - -static int nuclear_spi_flash_read(const struct spi_flash *flash, uint32_t addr, - size_t len, void *buf) -{ - int ret; - size_t xfer_len; - uint8_t *data = buf; - - BOILERPLATE_CREATE_CTX(ctx); - - while (len) { - xfer_len = get_xfer_len(addr, len); - - ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_READ, - addr, xfer_len); - if (ret != SUCCESS) - return ret; - - drain_xfer_fifo(ctx, data, xfer_len); - - addr += xfer_len; - data += xfer_len; - len -= xfer_len; - } - - return SUCCESS; -} - -static int nuclear_spi_flash_write(const struct spi_flash *flash, uint32_t addr, - size_t len, const void *buf) -{ - int ret; - size_t xfer_len; - const uint8_t *data = buf; - - BOILERPLATE_CREATE_CTX(ctx); - - while (len) { - xfer_len = get_xfer_len(addr, len); - fill_xfer_fifo(ctx, data, xfer_len); - - ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_WRITE, - addr, xfer_len); - if (ret != SUCCESS) - return ret; - - addr += xfer_len; - data += xfer_len; - len -= xfer_len; - } - - return SUCCESS; -} - -static int nuclear_spi_flash_status(const struct spi_flash *flash, uint8_t *reg) -{ - int ret; - BOILERPLATE_CREATE_CTX(ctx); - - ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_RD_STATUS, 0, - sizeof(*reg)); - if (ret != SUCCESS) - return ret; - - drain_xfer_fifo(ctx, reg, sizeof(*reg)); - return ret; -} - -/* - * We can't use FDOC and FDOD to read FLCOMP, as previous platforms did. - * For details see: - * Ch 31, SPI: p. 194 - * The size of the flash component is always taken from density field in the - * SFDP table. FLCOMP.C0DEN is no longer used by the Flash Controller. - */ -struct spi_flash *spi_flash_programmer_probe(struct spi_slave *dev, int force) -{ - BOILERPLATE_CREATE_CTX(ctx); - struct spi_flash *flash; - uint32_t flash_bits; - - flash = car_get_var_ptr(&boot_flash); - - /* - * bytes = (bits + 1) / 8; - * But we need to do the addition in a way which doesn't overflow for - * 4 Gbit devices (flash_bits == 0xffffffff). - */ - /* FIXME: Don't hardcode 0x04 ? */ - flash_bits = read_spi_flash_sfdp_param(ctx, 0x04); - flash->size = (flash_bits >> 3) + 1; - - memcpy(&flash->spi, dev, sizeof(*dev)); - flash->name = "Apollolake hardware sequencer"; - - /* Can erase both 4 KiB and 64 KiB chunks. Declare the smaller size. */ - flash->sector_size = 4 * KiB; - /* - * FIXME: Get erase+cmd, and status_cmd from SFDP. - * - * flash->erase_cmd = ??? - * flash->status_cmd = ??? - */ - - flash->internal_write = nuclear_spi_flash_write; - flash->internal_erase = nuclear_spi_flash_erase; - flash->internal_read = nuclear_spi_flash_read; - flash->internal_status = nuclear_spi_flash_status; - - return flash; -} - -int spi_flash_get_fpr_info(struct fpr_info *info) -{ - BOILERPLATE_CREATE_CTX(ctx); - - if (!ctx->mmio_base) - return -1; - - info->base = ctx->mmio_base + SPIBAR_FPR_BASE; - info->max = SPIBAR_FPR_MAX; - - return 0; -} diff --git a/src/soc/intel/apollolake/include/soc/flash_ctrlr.h b/src/soc/intel/apollolake/include/soc/flash_ctrlr.h deleted file mode 100644 index 336ce52..0000000 --- a/src/soc/intel/apollolake/include/soc/flash_ctrlr.h +++ /dev/null @@ -1,94 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_APOLLOLAKE_SPI_H_ -#define _SOC_APOLLOLAKE_SPI_H_ - -/* PCI configuration registers */ -#define SPIBAR_BIOS_CONTROL 0xdc -/* Bit definitions for BIOS_CONTROL */ -#define SPIBAR_BIOS_CONTROL_WPD (1 << 0) -#define SPIBAR_BIOS_CONTROL_CACHE_DISABLE (1 << 2) -#define SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE (1 << 3) -#define SPIBAR_BIOS_CONTROL_EISS (1 << 5) - -/* Maximum bytes of data that can fit in FDATAn registers */ -#define SPIBAR_FDATA_FIFO_SIZE 0x40 - -/* Register offsets from the MMIO region base (PCI_BASE_ADDRESS_0) */ -#define SPIBAR_BIOS_BFPREG 0x00 -#define SPIBAR_HSFSTS_CTL 0x04 -#define SPIBAR_FADDR 0x08 -#define SPIBAR_FDATA(n) (0x10 + ((n) & 0xf) * 4) -#define SPIBAR_FPR_BASE 0x84 -#define SPIBAR_PTINX 0xcc -#define SPIBAR_PTDATA 0xd0 - -#define SPIBAR_FPR_MAX 5 - -/* Bit definitions and masks for BIOS_BFPREG register. */ -#define SPIBAR_BFPREG_PRB_MASK (0x7fff) -#define SPIBAR_BFPREG_PRL_SHIFT (16) -#define SPIBAR_BFPREG_PRL_MASK (0x7fff << SPIBAR_BFPREG_PRL_SHIFT) -#define SPIBAR_BFPREG_SBRS (1 << 31) - -/* Bit definitions for HSFSTS_CTL register */ -#define SPIBAR_HSFSTS_FBDC_MASK (0x3f << 24) -#define SPIBAR_HSFSTS_FBDC(n) (((n) << 24) & SPIBAR_HSFSTS_FBDC_MASK) -#define SPIBAR_HSFSTS_WET (1 << 21) -#define SPIBAR_HSFSTS_FCYCLE_MASK (0xf << 17) -#define SPIBAR_HSFSTS_FCYCLE(cyc) (((cyc) << 17) \ - & SPIBAR_HSFSTS_FCYCLE_MASK) -#define SPIBAR_HSFSTS_FGO (1 << 16) -#define SPIBAR_HSFSTS_FLOCKDN (1 << 15) -#define SPIBAR_HSFSTS_FDV (1 << 14) -#define SPIBAR_HSFSTS_FDOPSS (1 << 13) -#define SPIBAR_HSFSTS_SAF_CE (1 << 8) -#define SPIBAR_HSFSTS_SAF_ACTIVE (1 << 7) -#define SPIBAR_HSFSTS_SAF_LE (1 << 6) -#define SPIBAR_HSFSTS_SCIP (1 << 5) -#define SPIBAR_HSFSTS_SAF_DLE (1 << 4) -#define SPIBAR_HSFSTS_SAF_ERROR (1 << 3) -#define SPIBAR_HSFSTS_AEL (1 << 2) -#define SPIBAR_HSFSTS_FCERR (1 << 1) -#define SPIBAR_HSFSTS_FDONE (1 << 0) -#define SPIBAR_HSFSTS_W1C_BITS (0xff) -/* Supported flash cycle types */ -#define SPIBAR_HSFSTS_CYCLE_READ SPIBAR_HSFSTS_FCYCLE(0) -#define SPIBAR_HSFSTS_CYCLE_WRITE SPIBAR_HSFSTS_FCYCLE(2) -#define SPIBAR_HSFSTS_CYCLE_4K_ERASE SPIBAR_HSFSTS_FCYCLE(3) -#define SPIBAR_HSFSTS_CYCLE_64K_ERASE SPIBAR_HSFSTS_FCYCLE(4) -#define SPIBAR_HSFSTS_CYCLE_RD_STATUS SPIBAR_HSFSTS_FCYCLE(8) - -/* Bit definitions for PTINX register */ -#define SPIBAR_PTINX_COMP_0 (0 << 14) -#define SPIBAR_PTINX_COMP_1 (1 << 14) -#define SPIBAR_PTINX_HORD_SFDP (0 << 12) -#define SPIBAR_PTINX_HORD_PARAM (1 << 12) -#define SPIBAR_PTINX_HORD_JEDEC (2 << 12) -#define SPIBAR_PTINX_IDX_MASK 0xffc - -/* - * Reads status register. On success returns 0 and status contains the value - * read from the status register. On error returns -1. - */ -int spi_flash_read_status(uint8_t *status); - -/* Read SPI controller register. */ -uint32_t spi_flash_ctrlr_reg_read(uint16_t reg); - -void spi_flash_init(void); -#endif diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c index 50d0ff0..598c068 100644 --- a/src/soc/intel/apollolake/mmap_boot.c +++ b/src/soc/intel/apollolake/mmap_boot.c @@ -22,7 +22,7 @@ #include <commonlib/region.h> #include <console/console.h> #include <fmap.h> -#include <soc/flash_ctrlr.h> +#include <intelblocks/fast_spi.h> #include <soc/mmap_boot.h> /* @@ -65,7 +65,7 @@ static void bios_mmap_init(void) { - size_t size, start, bios_end, bios_mapped_size; + size_t size, start, bios_mapped_size; uintptr_t base; size = car_get_var(bios_size); @@ -73,18 +73,7 @@ /* If bios_size is initialized, then bail out. */ if (size != 0) return; - - /* - * BIOS_BFPREG provides info about BIOS Flash Primary Region - * Base and Limit. - * Base and Limit fields are in units of 4KiB. - */ - uint32_t val = spi_flash_ctrlr_reg_read(SPIBAR_BIOS_BFPREG); - - start = (val & SPIBAR_BFPREG_PRB_MASK) * 4 * KiB; - bios_end = (((val & SPIBAR_BFPREG_PRL_MASK) >> - SPIBAR_BFPREG_PRL_SHIFT) + 1) * 4 * KiB; - size = bios_end - start; + start = fast_spi_get_bios_region(&size); /* BIOS region is mapped right below 4G. */ base = 4ULL * GiB - size; diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index c1353c8..98c7015 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -33,7 +33,6 @@ #include <fsp/util.h> #include <reset.h> #include <soc/cpu.h> -#include <soc/flash_ctrlr.h> #include <soc/intel/common/mrc_cache.h> #include <soc/iomap.h> #include <soc/systemagent.h> -- To view, visit https://review.coreboot.org/19080 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: Ifd72734dadda541fe4c828e4f1716e532ec69c27 Gerrit-PatchSet: 22 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins)

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Change in coreboot[master]: soc/intel/skylake: Clean up code by using common FAST_SPI mo...
by Furquan Shaikh (Code Review) 02 May '17

02 May '17

Furquan Shaikh has submitted this change and it was merged. ( https://review.coreboot.org/19055 ) Change subject: soc/intel/skylake: Clean up code by using common FAST_SPI module ...................................................................... soc/intel/skylake: Clean up code by using common FAST_SPI module This patch currently contains the following - 1. Use SOC_INTEL_COMMON_BLOCK_FAST_SPI kconfig for common FAST_SPI code. 2. Perform FAST_SPI programming by calling APIs from common FAST_SPI library. 3. Use common FAST_SPI header file. Change-Id: I4fc90504d322db70ed4ea644b1593cc0605b5fe8 Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> Reviewed-on: https://review.coreboot.org/19055 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/Makefile.inc M src/soc/intel/skylake/bootblock/cpu.c M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/skylake/finalize.c D src/soc/intel/skylake/flash_controller.c M src/soc/intel/skylake/include/fsp11/soc/romstage.h M src/soc/intel/skylake/include/fsp20/soc/romstage.h D src/soc/intel/skylake/include/soc/flash_controller.h M src/soc/intel/skylake/include/soc/pch.h D src/soc/intel/skylake/include/soc/spi.h M src/soc/intel/skylake/pch.c M src/soc/intel/skylake/romstage/Makefile.inc M src/soc/intel/skylake/romstage/romstage.c D src/soc/intel/skylake/romstage/spi.c M src/soc/intel/skylake/smihandler.c 16 files changed, 36 insertions(+), 859 deletions(-) Approvals: Aaron Durbin: Looks good to me, approved Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 95cf330..515de91 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -50,6 +50,7 @@ select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_GSPI select SOC_INTEL_COMMON_BLOCK_ITSS select SOC_INTEL_COMMON_BLOCK_LPSS diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 171a916..1d8fe16 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -15,7 +15,6 @@ bootblock-y += bootblock/pch.c bootblock-y += bootblock/report_platform.c bootblock-y += bootblock/smbus.c -bootblock-y += flash_controller.c bootblock-$(CONFIG_UART_DEBUG) += bootblock/uart.c bootblock-$(CONFIG_UART_DEBUG) += uart_debug.c bootblock-y += gpio.c @@ -26,7 +25,6 @@ bootblock-y += spi.c bootblock-y += tsc_freq.c -verstage-y += flash_controller.c verstage-y += gspi.c verstage-y += monotonic_timer.c verstage-y += pch.c @@ -36,7 +34,6 @@ verstage-y += spi.c verstage-y += tsc_freq.c -romstage-y += flash_controller.c romstage-y += gpio.c romstage-y += gspi.c romstage-y += bootblock/i2c.c @@ -61,7 +58,6 @@ ramstage-y += dsp.c ramstage-y += elog.c ramstage-y += finalize.c -ramstage-y += flash_controller.c ramstage-y += gpio.c ramstage-y += gspi.c ramstage-y += i2c.c @@ -98,7 +94,6 @@ smm-y += pch.c smm-y += pmutil.c smm-y += smihandler.c -smm-$(CONFIG_SPI_FLASH_SMM) += flash_controller.c smm-$(CONFIG_SPI_FLASH_SMM) += spi.c smm-y += tsc_freq.c smm-$(CONFIG_UART_DEBUG) += uart_debug.c diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c index fab589f..040e847 100644 --- a/src/soc/intel/skylake/bootblock/cpu.c +++ b/src/soc/intel/skylake/bootblock/cpu.c @@ -14,20 +14,20 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <delay.h> #include <arch/io.h> #include <console/console.h> -#include <cpu/x86/mtrr.h> #include <cpu/intel/microcode/microcode.c> -#include <reset.h> +#include <cpu/x86/mtrr.h> +#include <delay.h> +#include <intelblocks/fast_spi.h> #include <lib.h> +#include <reset.h> #include <soc/bootblock.h> #include <soc/cpu.h> #include <soc/iomap.h> #include <soc/msr.h> #include <soc/pci_devs.h> -#include <soc/spi.h> +#include <stdint.h> /* Soft Reset Data Register Bit 12 = MAX Boot Frequency */ #define SPI_STRAP_MAX_FREQ (1<<12) @@ -36,14 +36,7 @@ static void set_pch_cpu_strap(u8 flex_ratio) { - uint8_t *spibar = (void *)SPI_BASE_ADDRESS; - u32 ssl, ssms, soft_reset_data; - - - /* Set Strap Lock Disable */ - ssl = read32(spibar + SPIBAR_RESET_LOCK); - ssl |= SPIBAR_RESET_LOCK_DISABLE; - write32(spibar + SPIBAR_RESET_LOCK, ssl); + u32 soft_reset_data; /* Soft Reset Data Register Bit 12 = MAX Boot Frequency * Bit 6-11 = Flex Ratio @@ -51,17 +44,7 @@ */ soft_reset_data = SPI_STRAP_MAX_FREQ; soft_reset_data |= (flex_ratio << FLEX_RATIO_BIT); - write32(spibar + SPIBAR_RESET_DATA, soft_reset_data); - - /* Set Strap Mux Select set to '1' */ - ssms = read32(spibar + SPIBAR_RESET_CTRL); - ssms |= SPIBAR_RESET_CTRL_SSMC; - write32(spibar + SPIBAR_RESET_CTRL, ssms); - - /* Set Strap Lock Enable */ - ssl = read32(spibar + SPIBAR_RESET_LOCK); - ssl |= SPIBAR_RESET_LOCK_ENABLE; - write32(spibar + SPIBAR_RESET_LOCK, ssl); + fast_spi_set_strap_msg_data(soft_reset_data); } static void set_flex_ratio_to_tdp_nominal(void) diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index 01bff0b..a92e4cf 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -18,6 +18,7 @@ #include <chip.h> #include <device/device.h> #include <device/pci_def.h> +#include <intelblocks/fast_spi.h> #include <intelblocks/itss.h> #include <intelblocks/pcr.h> #include <intelblocks/rtc.h> @@ -46,38 +47,6 @@ #define PCR_DMI_LPCIOD 0x2770 #define PCR_DMI_LPCIOE 0x2774 -/* - * Enable Prefetching and Caching. - */ -static void enable_spi_prefetch(void) -{ - u8 reg8 = pci_read_config8(PCH_DEV_SPI, 0xdc); - reg8 &= ~(3 << 2); - reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ - pci_write_config8(PCH_DEV_SPI, 0xdc, reg8); -} - -static void enable_spibar(void) -{ - device_t dev = PCH_DEV_SPI; - u8 pcireg; - - /* Assign Resources to SPI Controller */ - /* Clear BIT 1-2 SPI Command Register */ - pcireg = pci_read_config8(dev, PCI_COMMAND); - pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - pci_write_config8(dev, PCI_COMMAND, pcireg); - - /* Program Temporary BAR for SPI */ - pci_write_config32(dev, PCI_BASE_ADDRESS_0, - SPI_BASE_ADDRESS | PCI_BASE_ADDRESS_SPACE_MEMORY); - - /* Enable Bus Master and MMIO Space */ - pcireg = pci_read_config8(dev, PCI_COMMAND); - pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config8(dev, PCI_COMMAND, pcireg); -} - static void enable_p2sbbar(void) { device_t dev = PCH_DEV_P2SB; @@ -99,8 +68,7 @@ void bootblock_pch_early_init(void) { - enable_spibar(); - enable_spi_prefetch(); + fast_spi_early_init(SPI_BASE_ADDRESS); enable_p2sbbar(); } diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 9cb246c..171d92e 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -21,10 +21,10 @@ #include <console/post_codes.h> #include <cpu/x86/smm.h> #include <device/pci.h> +#include <intelblocks/fast_spi.h> #include <intelblocks/pcr.h> #include <reg_script.h> #include <spi-generic.h> -#include <stdlib.h> #include <soc/lpc.h> #include <soc/me.h> #include <soc/p2sb.h> @@ -32,8 +32,8 @@ #include <soc/pcr_ids.h> #include <soc/pm.h> #include <soc/smbus.h> -#include <soc/spi.h> #include <soc/systemagent.h> +#include <stdlib.h> #define PCR_DMI_GCS 0x274C #define PCR_DMI_GCS_BILD (1 << 0) @@ -87,8 +87,7 @@ static void pch_finalize_script(void) { device_t dev; - uint32_t reg32, hsfs; - void *spibar = get_spi_bar(); + uint32_t reg32; u16 tcobase; u16 tcocnt; uint8_t *pmcbase; @@ -96,15 +95,11 @@ u32 pmsyncreg; u8 reg8; - /* Set SPI opcode menu */ - write16(spibar + SPIBAR_PREOP, SPI_OPPREFIX); - write16(spibar + SPIBAR_OPTYPE, SPI_OPTYPE); - write32(spibar + SPIBAR_OPMENU_LOWER, SPI_OPMENU_LOWER); - write32(spibar + SPIBAR_OPMENU_UPPER, SPI_OPMENU_UPPER); - /* Lock SPIBAR */ - hsfs = read32(spibar + SPIBAR_HSFS); - hsfs |= SPIBAR_HSFS_FLOCKDN; - write32(spibar + SPIBAR_HSFS, hsfs); + /* Set FAST_SPI opcode menu */ + fast_spi_set_opcode_menu(); + + /* Lock FAST_SPIBAR */ + fast_spi_lock_bar(); /*TCO Lock down */ tcobase = smbus_tco_regs(); @@ -177,12 +172,9 @@ BIOS_CNTL) | LPC_BC_BILD); /* Reads back for posted write to take effect */ pci_read_config8(PCH_DEV_LPC, BIOS_CNTL); - pci_write_config32(PCH_DEV_SPI, SPIBAR_BIOS_CNTL, - pci_read_config32(PCH_DEV_SPI, - SPIBAR_BIOS_CNTL) | - SPIBAR_BC_BILD); - /* Reads back for posted write to take effect */ - pci_read_config32(PCH_DEV_SPI, SPIBAR_BIOS_CNTL); + + fast_spi_set_bios_interface_lock_down(); + /* GCS reg of DMI */ pcr_or8(PID_DMI, PCR_DMI_GCS, PCR_DMI_GCS_BILD); } @@ -192,9 +184,8 @@ pci_write_config8(PCH_DEV_LPC, BIOS_CNTL, pci_read_config8(PCH_DEV_LPC, BIOS_CNTL) | LPC_BC_LE); - pci_write_config8(PCH_DEV_SPI, BIOS_CNTL, - pci_read_config8(PCH_DEV_SPI, - BIOS_CNTL) | SPIBAR_BC_LE); + + fast_spi_set_lock_enable(); } /* SPIEiss */ @@ -202,10 +193,8 @@ pci_write_config8(PCH_DEV_LPC, BIOS_CNTL, pci_read_config8(PCH_DEV_LPC, BIOS_CNTL) | LPC_BC_EISS); - pci_write_config8(PCH_DEV_SPI, BIOS_CNTL, - pci_read_config8(PCH_DEV_SPI, - SPIBAR_BIOS_CNTL) | - SPIBAR_BC_EISS); + + fast_spi_set_eiss(); } } diff --git a/src/soc/intel/skylake/flash_controller.c b/src/soc/intel/skylake/flash_controller.c deleted file mode 100644 index ac6758e..0000000 --- a/src/soc/intel/skylake/flash_controller.c +++ /dev/null @@ -1,378 +0,0 @@ -/* - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This file is derived from the flashrom project. */ -#include <arch/early_variables.h> -#include <stdint.h> -#include <stdlib.h> -#include <string.h> -#include <bootstate.h> -#include <timer.h> -#include <soc/flash_controller.h> -#include <soc/intel/common/spi_flash.h> -#include <soc/pci_devs.h> -#include <soc/spi.h> -#include <spi-generic.h> - -static inline uint16_t spi_flash_read_hsfs(pch_spi_flash_regs * const regs) -{ - return readw_(&regs->hsfs); -} - -static inline void spi_flash_clear_status(pch_spi_flash_regs * const regs) -{ - /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ - writew_(spi_flash_read_hsfs(regs), &regs->hsfs); -} - -static inline uint16_t spi_flash_read_hsfc(pch_spi_flash_regs * const regs) -{ - return readw_(&regs->hsfc); -} - -static inline uint32_t spi_flash_read_faddr(pch_spi_flash_regs * const regs) -{ - return readl_(&regs->faddr) & SPIBAR_FADDR_MASK; -} - -/* - * Polls for Cycle Done Status, Flash Cycle Error - * Resets all error flags in HSFS. - * Returns 0 if the cycle completes successfully without errors within - * timeout, 1 on errors. - */ -static int wait_for_completion(pch_spi_flash_regs * const regs, int timeout_ms, - size_t len) -{ - uint16_t hsfs; - uint16_t hsfc; - uint32_t addr; - struct stopwatch sw; - int timeout = 0; - - stopwatch_init_msecs_expire(&sw, timeout_ms); - - do { - hsfs = spi_flash_read_hsfs(regs); - - if ((hsfs & (HSFS_FDONE | HSFS_FCERR))) - break; - } while (!(timeout = stopwatch_expired(&sw))); - - if (timeout) { - addr = spi_flash_read_faddr(regs); - hsfc = spi_flash_read_hsfc(regs); - printk(BIOS_ERR, "%ld ms Transaction timeout between offset " - "0x%08x and 0x%08zx (= 0x%08x + %zd) HSFC=%x HSFS=%x!\n", - stopwatch_duration_msecs(&sw), addr, addr + len - 1, - addr, len - 1, hsfc, hsfs); - return 1; - } - - if (hsfs & HSFS_FCERR) { - addr = spi_flash_read_faddr(regs); - hsfc = spi_flash_read_hsfc(regs); - printk(BIOS_ERR, "Transaction error between offset 0x%08x and " - "0x%08zx (= 0x%08x + %zd) HSFC=%x HSFS=%x!\n", - addr, addr + len - 1, addr, len - 1, - hsfc, hsfs); - return 1; - } - - return 0; -} - -/* Start operation returning 0 on success, non-zero on error or timeout. */ -static int spi_flash_do_operation(int op, size_t offset, size_t size, - int timeout_ms) -{ - uint16_t hsfc; - pch_spi_flash_regs * const regs = get_spi_bar(); - - /* Clear status prior to operation. */ - spi_flash_clear_status(regs); - - /* Set the FADDR */ - writel_(offset & SPIBAR_FADDR_MASK, &regs->faddr); - - hsfc = readw_(&regs->hsfc); - /* Clear then set the correct op. */ - hsfc &= ~HSFC_FCYCLE_MASK; - hsfc |= op; - /* Set the size field */ - hsfc &= ~HSFC_FDBC_MASK; - /* Check for sizes of confirming operations. */ - if (size && size <= SPI_FDATA_BYTES) - hsfc |= ((size - 1) << HSFC_FDBC_SHIFT) & HSFC_FDBC_MASK; - /* start operation */ - hsfc |= HSFC_FGO; - writew_(hsfc, &regs->hsfc); - - return wait_for_completion(regs, timeout_ms, size); -} - -unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) -{ - return min(SPI_FDATA_BYTES, buf_len); -} - -static size_t spi_get_flash_size(pch_spi_flash_regs *spi_bar) -{ - uint32_t flcomp; - size_t size; - - writel_(SPIBAR_FDOC_COMPONENT, &spi_bar->fdoc); - flcomp = readl_(&spi_bar->fdod); - - switch (flcomp & FLCOMP_C0DEN_MASK) { - case FLCOMP_C0DEN_8MB: - size = 8*MiB; - break; - case FLCOMP_C0DEN_16MB: - size = 16*MiB; - break; - case FLCOMP_C0DEN_32MB: - size = 32*MiB; - break; - default: - size = 16*MiB; - } - - return size; -} - -void spi_flash_init(void) -{ - uint8_t bios_cntl; - device_t dev = PCH_DEV_SPI; - - /* Disable the BIOS write protect so write commands are allowed. */ - pci_read_config_byte(dev, SPIBAR_BIOS_CNTL, &bios_cntl); - bios_cntl &= ~SPIBAR_BC_EISS; - bios_cntl |= SPIBAR_BC_WPD; - pci_write_config_byte(dev, SPIBAR_BIOS_CNTL, bios_cntl); -} - -int pch_hwseq_erase(const struct spi_flash *flash, u32 offset, size_t len) -{ - u32 start, end, erase_size; - int ret = 0; - - erase_size = flash->sector_size; - if (offset % erase_size || len % erase_size) { - printk(BIOS_ERR, "SF: Erase offset/length not multiple of erase size\n"); - return -1; - } - - start = offset; - end = start + len; - - while (offset < end) { - if (spi_flash_do_operation(HSFC_FCYCLE_4KE, offset, 0, 5000)) { - printk(BIOS_ERR, "SF: Erase failed at %x\n", offset); - ret = -1; - goto out; - } - - offset += erase_size; - } - - printk(BIOS_DEBUG, "SF: Successfully erased %zu bytes @ %#x\n", - len, start); - -out: - return ret; -} - -static void pch_read_data(uint8_t *data, int len) -{ - int i; - pch_spi_flash_regs *spi_bar; - uint32_t temp32 = 0; - - spi_bar = get_spi_bar(); - - for (i = 0; i < len; i++) { - if ((i % 4) == 0) - temp32 = readl_((uint8_t *)spi_bar->fdata + i); - - data[i] = (temp32 >> ((i % 4) * 8)) & 0xff; - } -} - -int pch_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len, - void *buf) -{ - uint8_t block_len; - - if (addr + len > spi_get_flash_size(get_spi_bar())) { - printk(BIOS_ERR, - "Attempt to read %x-%x which is out of chip\n", - (unsigned int) addr, - (unsigned int) addr + (unsigned int)len); - return -1; - } - - while (len > 0) { - const int timeout_ms = 6; - - block_len = min(len, SPI_FDATA_BYTES); - if (block_len > (~addr & 0xff)) - block_len = (~addr & 0xff) + 1; - - if (spi_flash_do_operation(HSFC_FCYCLE_RD, addr, block_len, - timeout_ms)) - return -1; - - pch_read_data(buf, block_len); - addr += block_len; - buf += block_len; - len -= block_len; - } - return 0; -} - -/* Fill len bytes from the data array into the fdata/spid registers. - * - * Note that using len > flash->pgm->spi.max_data_write will trash the registers - * following the data registers. - */ -static void pch_fill_data(const uint8_t *data, int len) -{ - uint32_t temp32 = 0; - int i; - pch_spi_flash_regs *spi_bar; - - spi_bar = get_spi_bar(); - if (len <= 0) - return; - - for (i = 0; i < len; i++) { - if ((i % 4) == 0) - temp32 = 0; - - temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8); - - if ((i % 4) == 3) /* 32 bits are full, write them to regs. */ - writel_(temp32, - (uint8_t *)spi_bar->fdata + (i - (i % 4))); - } - i--; - if ((i % 4) != 3) /* Write remaining data to regs. */ - writel_(temp32, (uint8_t *)spi_bar->fdata + (i - (i % 4))); -} - -int pch_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len, - const void *buf) -{ - uint8_t block_len; - uint32_t start = addr; - pch_spi_flash_regs *spi_bar; - - spi_bar = get_spi_bar(); - - if (addr + len > spi_get_flash_size(spi_bar)) { - printk(BIOS_ERR, - "Attempt to write 0x%x-0x%x which is out of chip\n", - (unsigned int)addr, (unsigned int)(addr + len)); - return -1; - } - - while (len > 0) { - const int timeout_ms = 6; - - block_len = min(len, sizeof(spi_bar->fdata)); - if (block_len > (~addr & 0xff)) - block_len = (~addr & 0xff) + 1; - - pch_fill_data(buf, block_len); - if (spi_flash_do_operation(HSFC_FCYCLE_WR, addr, block_len, - timeout_ms)) { - printk(BIOS_ERR, "SF: write failure at %x\n", addr); - return -1; - } - addr += block_len; - buf += block_len; - len -= block_len; - } - printk(BIOS_DEBUG, "SF: Successfully written %u bytes @ %#x\n", - (unsigned int)(addr - start), start); - return 0; -} - -int pch_hwseq_read_status(const struct spi_flash *flash, u8 *reg) -{ - size_t block_len = SPI_READ_STATUS_LENGTH; - const int timeout_ms = 6; - - if (spi_flash_do_operation(HSFC_FCYCLE_RS, 0, block_len, timeout_ms)) - return -1; - - pch_read_data(reg, block_len); - - return 0; -} - -static struct spi_flash boot_flash CAR_GLOBAL; - -struct spi_flash *spi_flash_programmer_probe(struct spi_slave *spi, int force) -{ - struct spi_flash *flash; - - flash = car_get_var_ptr(&boot_flash); - - /* Ensure writes can take place to the flash. */ - spi_flash_init(); - - memcpy(&flash->spi, spi, sizeof(*spi)); - flash->name = "Opaque HW-sequencing"; - - flash->internal_write = pch_hwseq_write; - flash->internal_erase = pch_hwseq_erase; - flash->internal_read = pch_hwseq_read; - flash->internal_status = pch_hwseq_read_status; - - /* The hardware sequencing supports 4KiB or 64KiB erase. Use 4KiB. */ - flash->sector_size = 4*KiB; - - flash->size = spi_get_flash_size(get_spi_bar()); - - return flash; -} - -int spi_flash_get_fpr_info(struct fpr_info *info) -{ - pch_spi_flash_regs *spi_bar = get_spi_bar(); - - if (!spi_bar) - return -1; - - info->base = (uintptr_t)&spi_bar->pr[0]; - info->max = SPI_FPR_MAX; - - return 0; -} - -#if ENV_RAMSTAGE -/* - * spi_flash_init() needs run unconditionally in every boot (including resume) - * to allow write protect to be disabled for eventlog and firmware updates. - */ -static void spi_flash_init_cb(void *unused) -{ - spi_flash_init(); -} - -BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_flash_init_cb, NULL); -#endif diff --git a/src/soc/intel/skylake/include/fsp11/soc/romstage.h b/src/soc/intel/skylake/include/fsp11/soc/romstage.h index f3e4371..36825f7 100644 --- a/src/soc/intel/skylake/include/fsp11/soc/romstage.h +++ b/src/soc/intel/skylake/include/fsp11/soc/romstage.h @@ -24,7 +24,6 @@ void enable_smbus(void); int smbus_read_byte(unsigned int device, unsigned int address); -int early_spi_read_wpsr(u8 *sr); void mainboard_fill_spd_data(struct pei_data *pei_data); #endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/skylake/include/fsp20/soc/romstage.h b/src/soc/intel/skylake/include/fsp20/soc/romstage.h index 6bdc3b5..cdcc8fb 100644 --- a/src/soc/intel/skylake/include/fsp20/soc/romstage.h +++ b/src/soc/intel/skylake/include/fsp20/soc/romstage.h @@ -23,7 +23,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd); void systemagent_early_init(void); int smbus_read_byte(unsigned int device, unsigned int address); -int early_spi_read_wpsr(u8 *sr); /* Board type */ enum board_type { BOARD_TYPE_MOBILE = 0, diff --git a/src/soc/intel/skylake/include/soc/flash_controller.h b/src/soc/intel/skylake/include/soc/flash_controller.h deleted file mode 100644 index 712a18d..0000000 --- a/src/soc/intel/skylake/include/soc/flash_controller.h +++ /dev/null @@ -1,181 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_FLASH_CONTROLLER__H_ -#define _SOC_FLASH_CONTROLLER__H_ - -#include <rules.h> -#include <arch/io.h> -#include <console/console.h> -#include <spi_flash.h> - -int pch_hwseq_erase(const struct spi_flash *flash, u32 offset, size_t len); -int pch_hwseq_write(const struct spi_flash *flash, u32 addr, size_t len, - const void *buf); -int pch_hwseq_read(const struct spi_flash *flash, u32 addr, size_t len, - void *buf); -int pch_hwseq_read_status(const struct spi_flash *flash, u8 *reg); - -void spi_flash_init(void); - -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) -static u8 readb_(const void *addr) -{ - u8 v = read8(addr); - printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", - v, ((unsigned int) addr & 0xffff) - 0xf020); - return v; -} - -static u16 readw_(const void *addr) -{ - u16 v = read16(addr); - printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", - v, ((unsigned int) addr & 0xffff) - 0xf020); - return v; -} - -static u32 readl_(const void *addr) -{ - u32 v = read32(addr); - printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", - v, ((unsigned int) addr & 0xffff) - 0xf020); - return v; -} - -static void writeb_(u8 b, void *addr) -{ - write8(addr, b); - printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", - b, ((unsigned int) addr & 0xffff) - 0xf020); -} - -static void writew_(u16 b, void *addr) -{ - write16(addr, b); - printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", - b, ((unsigned int) addr & 0xffff) - 0xf020); -} - -static void writel_(u32 b, void *addr) -{ - write32(addr, b); - printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", - b, ((unsigned int) addr & 0xffff) - 0xf020); -} - -#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ - -#define readb_(a) read8(a) -#define readw_(a) read16(a) -#define readl_(a) read32(a) -#define writeb_(val, addr) write8(addr, val) -#define writew_(val, addr) write16(addr, val) -#define writel_(val, addr) write32(addr, val) - -#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */ - -#if ENV_SMM -#define pci_read_config_byte(dev, reg, targ)\ - (*(targ) = pci_read_config8(dev, reg)) -#define pci_read_config_word(dev, reg, targ)\ - (*(targ) = pci_read_config16(dev, reg)) -#define pci_read_config_dword(dev, reg, targ)\ - (*(targ) = pci_read_config32(dev, reg)) -#define pci_write_config_byte(dev, reg, val)\ - pci_write_config8(dev, reg, val) -#define pci_write_config_word(dev, reg, val)\ - pci_write_config16(dev, reg, val) -#define pci_write_config_dword(dev, reg, val)\ - pci_write_config32(dev, reg, val) -#else /* !ENV_SMM */ -#include <device/device.h> -#include <device/pci.h> -#define pci_read_config_byte(dev, reg, targ)\ - (*(targ) = pci_read_config8(dev, reg)) -#define pci_read_config_word(dev, reg, targ)\ - (*(targ) = pci_read_config16(dev, reg)) -#define pci_read_config_dword(dev, reg, targ)\ - (*(targ) = pci_read_config32(dev, reg)) -#define pci_write_config_byte(dev, reg, val)\ - pci_write_config8(dev, reg, val) -#define pci_write_config_word(dev, reg, val)\ - pci_write_config16(dev, reg, val) -#define pci_write_config_dword(dev, reg, val)\ - pci_write_config32(dev, reg, val) -#endif /* ENV_SMM */ - -#define HSFC_FCYCLE_MASK (0xf << HSFC_FCYCLE_SHIFT) -#define HSFC_FCYCLE_RD (0x0 << HSFC_FCYCLE_SHIFT) -#define HSFC_FCYCLE_WR (0x2 << HSFC_FCYCLE_SHIFT) -#define HSFC_FCYCLE_4KE (0x3 << HSFC_FCYCLE_SHIFT) -#define HSFC_FCYCLE_64KE (0x4 << HSFC_FCYCLE_SHIFT) -#define HSFC_FCYCLE_SFDP (0x5 << HSFC_FCYCLE_SHIFT) -#define HSFC_FCYCLE_JEDECID (0x6 << HSFC_FCYCLE_SHIFT) -#define HSFC_FCYCLE_WS (0x7 << HSFC_FCYCLE_SHIFT) -#define HSFC_FCYCLE_RS (0x8 << HSFC_FCYCLE_SHIFT) -#define HSFC_FDBC_MASK (0x3f << HSFC_FDBC_SHIFT) - -#define SPI_READ_STATUS_LENGTH 1 /* Read Status Register 1 */ - -#define WPSR_MASK_SRP0_BIT 0x80 - -#define SPI_FDATA_REGS 16 -#define SPI_FDATA_BYTES (SPI_FDATA_REGS * sizeof(uint32_t)) - -typedef struct pch_spi_flash_regs { - uint32_t bfpr; - uint16_t hsfs; - uint16_t hsfc; - uint32_t faddr; - uint32_t dlock; - uint32_t fdata[SPI_FDATA_REGS]; - uint32_t frap; - uint32_t freg[6]; - uint32_t _reserved1[6]; - uint32_t pr[5]; - uint32_t gpr0; - uint32_t _reserved2; - uint32_t _reserved3; - uint16_t preop; - uint16_t optype; - uint8_t opmenu[8]; - uint32_t bbar; - uint32_t fdoc; - uint32_t fdod; - uint8_t _reserved4[8]; - uint32_t afc; - uint32_t lvscc; - uint32_t uvscc; - uint8_t _reserved5[4]; - uint32_t fpb; - uint8_t _reserved6[28]; - uint32_t srdl; - uint32_t srdc; - uint32_t srd; -} __attribute__((packed)) pch_spi_flash_regs; - -enum { - HSFS_FDONE = 0x0001, - HSFS_FCERR = 0x0002, - HSFS_FDV = 0x4000, -}; - -enum { - HSFC_FGO = 0x0001, - HSFC_FCYCLE_SHIFT = 1, - HSFC_FDBC_SHIFT = 8, -}; -#endif /* _SOC_FLASH_CONTROLLER__H_ */ diff --git a/src/soc/intel/skylake/include/soc/pch.h b/src/soc/intel/skylake/include/soc/pch.h index d8e5b96..9602f10 100644 --- a/src/soc/intel/skylake/include/soc/pch.h +++ b/src/soc/intel/skylake/include/soc/pch.h @@ -37,7 +37,6 @@ u8 pch_revision(void); u16 pch_type(void); -u32 pch_read_soft_strap(int id); void pch_log_state(void); #if ENV_RAMSTAGE void pch_disable_devfn(device_t dev); diff --git a/src/soc/intel/skylake/include/soc/spi.h b/src/soc/intel/skylake/include/soc/spi.h deleted file mode 100644 index a92b78d..0000000 --- a/src/soc/intel/skylake/include/soc/spi.h +++ /dev/null @@ -1,126 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_SPI_H_ -#define _SOC_SPI_H_ - -/* - * SPI Opcode Menu setup for SPIBAR lockdown - * should support most common flash chips. - */ -#define SPIDVID_OFFSET 0x0 - -/* Reigsters within the SPIBAR */ -#define SPIBAR_SSFC 0xA1 - -#define SPIBAR_PREOP 0xA4 -#define SPIBAR_OPTYPE 0xA6 -#define SPIBAR_OPMENU_LOWER 0xA8 -#define SPIBAR_OPMENU_UPPER 0xAc -/* STRAP LOCK Register */ -#define SPIBAR_RESET_LOCK 0xF0 -#define SPIBAR_RESET_LOCK_DISABLE 0 -#define SPIBAR_RESET_LOCK_ENABLE 1 -/* STRAP MSG Control Register*/ -#define SPIBAR_RESET_CTRL 0xF4 -#define SPIBAR_RESET_CTRL_SSMC 1 -/* STRAP Data Register*/ -#define SPIBAR_RESET_DATA 0xF8 - -#define SPI_FPR_MAX 5 - -#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ -#define SPI_OPTYPE_0 0x01 /* Write, no address */ - -#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ -#define SPI_OPTYPE_1 0x03 /* Write, address required */ - -#define SPI_OPMENU_2 0x03 /* READ: Read Data */ -#define SPI_OPTYPE_2 0x02 /* Read, address required */ - -#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ -#define SPI_OPTYPE_3 0x00 /* Read, no address */ - -#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ -#define SPI_OPTYPE_4 0x03 /* Write, address required */ - -#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ -#define SPI_OPTYPE_5 0x00 /* Read, no address */ - -#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ -#define SPI_OPTYPE_6 0x03 /* Write, address required */ - -#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ -#define SPI_OPTYPE_7 0x02 /* Read, address required */ - -#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ - (SPI_OPMENU_5 << 8) | SPI_OPMENU_4) -#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ - (SPI_OPMENU_1 << 8) | SPI_OPMENU_0) - -#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ - (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ - (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ - (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0)) - -#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ - -#define SPIBAR_HSFS 0x04 /* SPI hardware sequence status */ -#define SPIBAR_HSFS_FLOCKDN (1 << 15)/* Flash Configuration Lock-Down */ -#define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ -#define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */ -#define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */ -#define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */ -#define SPIBAR_HSFS_BERASE_MASK 3 /* Block/Sector Erase MASK */ -#define SPIBAR_HSFS_BERASE_OFFSET 3 /* Block/Sector Erase OFFSET */ -#define SPIBAR_HSFC 0x06 /* SPI hardware sequence control */ -#define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8) -#define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */ -#define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */ -#define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */ -#define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */ -#define SPIBAR_FADDR 0x08 /* SPI flash address */ -#define SPIBAR_FADDR_MASK 0x7FFFFFF - -#define SPIBAR_FDATA(n) (0x10 + (4 * n)) /* SPI flash data */ -#define SPIBAR_FPR(n) (0x84 + (4 * n)) /* SPI flash protected range */ -#define SPIBAR_FPR_WPE (1 << 31) /* Flash Write protected */ -#define SPIBAR_SSFS 0xA0 -#define SPIBAR_SSFS_ERROR (1 << 3) -#define SPIBAR_SSFS_DONE (1 << 2) -#define SPIBAR_SSFC 0xA1 -#define SPIBAR_SSFC_DATA (1 << 14) -#define SPIBAR_SSFC_GO (1 << 1) - -#define SPIBAR_FDOC 0xB4 -#define SPIBAR_FDOC_COMPONENT (1 << 12) -#define SPIBAR_FDOC_FDSI_1 (1 << 2) - -#define SPIBAR_FDOD 0xB8 -#define FLCOMP_C0DEN_MASK 0xF -#define FLCOMP_C0DEN_8MB 4 -#define FLCOMP_C0DEN_16MB 5 -#define FLCOMP_C0DEN_32MB 6 - -#define SPIBAR_BIOS_CNTL 0xDC -#define SPIBAR_BC_BILD (1 << 7) -#define SPIBAR_BC_EISS (1 << 5) -#define SPIBAR_BC_LE (1 << 2) -#define SPIBAR_BC_WPD (1 << 0) - -void *get_spi_bar(void); - -#endif diff --git a/src/soc/intel/skylake/pch.c b/src/soc/intel/skylake/pch.c index ed64c8f..7084fa2 100644 --- a/src/soc/intel/skylake/pch.c +++ b/src/soc/intel/skylake/pch.c @@ -15,16 +15,15 @@ * GNU General Public License for more details. */ +#include <arch/io.h> #include <console/console.h> #include <delay.h> -#include <arch/io.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_def.h> #include <soc/pch.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> -#include <soc/spi.h> u8 pch_revision(void) { @@ -34,34 +33,6 @@ u16 pch_type(void) { return pci_read_config16(PCH_DEV_LPC, PCI_DEVICE_ID); -} - -void *get_spi_bar(void) -{ - device_t dev = PCH_DEV_SPI; - uint32_t bar; - - bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); - /* Bits 31-12 are the base address as per EDS for SPI 1F/5, - * Don't care about 0-11 bit - */ - return (void *)(bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK); -} - -u32 pch_read_soft_strap(int id) -{ - uint32_t fdoc; - void *spibar = get_spi_bar(); - - fdoc = read32(spibar + SPIBAR_FDOC); - fdoc &= ~0x00007ffc; - write32(spibar + SPIBAR_FDOC, fdoc); - - fdoc |= 0x00004000; - fdoc |= id * 4; - write32(spibar + SPIBAR_FDOC, fdoc); - - return read32(spibar + SPIBAR_FDOD); } #if ENV_RAMSTAGE diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc index 7dfbd35..b3f3fab 100644 --- a/src/soc/intel/skylake/romstage/Makefile.inc +++ b/src/soc/intel/skylake/romstage/Makefile.inc @@ -5,5 +5,4 @@ romstage-y += power_state.c romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += romstage.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage_fsp20.c -romstage-y += spi.c romstage-y += systemagent.c diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index fb261c3..cb704fd 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -14,8 +14,6 @@ * GNU General Public License for more details. */ -#include <stddef.h> -#include <stdint.h> #include <arch/cpu.h> #include <arch/io.h> #include <arch/cbfs.h> @@ -30,6 +28,7 @@ #include <device/pci.h> #include <device/pci_def.h> #include <elog.h> +#include <intelblocks/fast_spi.h> #include <reset.h> #include <romstage_handoff.h> #include <soc/pci_devs.h> @@ -38,8 +37,9 @@ #include <soc/pmc.h> #include <soc/serialio.h> #include <soc/romstage.h> -#include <soc/spi.h> #include <stage_cache.h> +#include <stddef.h> +#include <stdint.h> #include <timestamp.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -58,7 +58,7 @@ u8 status; /* Return unprotected status if status read fails. */ - return early_spi_read_wpsr(&status) ? 0 : !!(status & 0x80); + return fast_spi_flash_read_wpsr(&status) ? 0 : !!(status & 0x80); } /* UPD parameters to be initialized before MemoryInit */ diff --git a/src/soc/intel/skylake/romstage/spi.c b/src/soc/intel/skylake/romstage/spi.c deleted file mode 100644 index 41e06a7..0000000 --- a/src/soc/intel/skylake/romstage/spi.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/flash_controller.h> -#include <soc/romstage.h> -#include <spi-generic.h> - -/* - * Minimal set of commands to read WPSR from SPI. - * Returns 0 on success, < 0 on failure. - */ -int early_spi_read_wpsr(u8 *sr) -{ - uint8_t rdsr; - int ret = 0; - - spi_flash_init(); - - /* sending NULL for spiflash struct parameter since we are not - * calling HWSEQ read_status() call via Probe. - */ - ret = pch_hwseq_read_status(NULL, &rdsr); - if (ret) { - printk(BIOS_ERR, "SPI rdsr failed\n"); - return ret; - } - *sr = rdsr & WPSR_MASK_SRP0_BIT; - - return 0; -} diff --git a/src/soc/intel/skylake/smihandler.c b/src/soc/intel/skylake/smihandler.c index e6f6959..c4c4a7b 100644 --- a/src/soc/intel/skylake/smihandler.c +++ b/src/soc/intel/skylake/smihandler.c @@ -15,8 +15,6 @@ * GNU General Public License for more details. */ -#include <delay.h> -#include <types.h> #include <arch/hlt.h> #include <arch/io.h> #include <console/console.h> @@ -24,10 +22,13 @@ #include <cpu/x86/smm.h> #include <device/pci_def.h> #include <elog.h> +#include <intelblocks/fast_spi.h> #include <intelblocks/pcr.h> +#include <delay.h> +#include <device/pci_def.h> +#include <elog.h> #include <pc80/mc146818rtc.h> #include <spi-generic.h> -#include <soc/flash_controller.h> #include <soc/iomap.h> #include <soc/lpc.h> #include <soc/nvs.h> @@ -37,6 +38,7 @@ #include <soc/pm.h> #include <soc/pmc.h> #include <soc/smm.h> +#include <types.h> /* IO Trap PCRs */ /* Trap status Register */ @@ -286,7 +288,7 @@ if (IS_ENABLED(CONFIG_SPI_FLASH_SMM)) /* Re-init SPI driver to handle locked BAR */ - spi_flash_init(); + fast_spi_init(); } static void southbridge_smi_apmc(void) -- To view, visit https://review.coreboot.org/19055 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I4fc90504d322db70ed4ea644b1593cc0605b5fe8 Gerrit-PatchSet: 24 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins)

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Change in coreboot[master]: soc/intel/apollolake: Clean up code by using common FAST_SPI...
by Furquan Shaikh (Code Review) 02 May '17

02 May '17

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/19080 ) Change subject: soc/intel/apollolake: Clean up code by using common FAST_SPI module ...................................................................... Patch Set 21: Code-Review+2 -- To view, visit https://review.coreboot.org/19080 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ifd72734dadda541fe4c828e4f1716e532ec69c27 Gerrit-PatchSet: 21 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Clean up code by using common FAST_SPI mo...
by Furquan Shaikh (Code Review) 02 May '17

02 May '17

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/19055 ) Change subject: soc/intel/skylake: Clean up code by using common FAST_SPI module ...................................................................... Patch Set 23: Code-Review+2 -- To view, visit https://review.coreboot.org/19055 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I4fc90504d322db70ed4ea644b1593cc0605b5fe8 Gerrit-PatchSet: 23 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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coreboot-gerrit May 2017