coreboot-gerrit May 2017

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Change in coreboot[master]: mainboard/google/poppy: Update GPIO table for next build
by Furquan Shaikh (Code Review) 02 May '17

02 May '17

Furquan Shaikh has submitted this change and it was merged. ( https://review.coreboot.org/19517 ) Change subject: mainboard/google/poppy: Update GPIO table for next build ...................................................................... mainboard/google/poppy: Update GPIO table for next build Update GPIO table to match the schematics for next build. Change-Id: I949a14bfaa7972f2257a0b11ee81dcb0771e2f7f Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/19517 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/poppy/variants/baseboard/gpio.c 1 file changed, 25 insertions(+), 20 deletions(-) Approvals: Aaron Durbin: Looks good to me, approved Sumeet R Pawnikar: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/poppy/variants/baseboard/gpio.c b/src/mainboard/google/poppy/variants/baseboard/gpio.c index 4d77f5e..fcbbb1d 100644 --- a/src/mainboard/google/poppy/variants/baseboard/gpio.c +++ b/src/mainboard/google/poppy/variants/baseboard/gpio.c @@ -29,7 +29,7 @@ /* A5 : ESPI_CS# */ /* A6 : SERIRQ ==> NC(TP44) */ PAD_CFG_NC(GPP_A6), - /* A7 : PIRQA# ==> NC */ + /* A7 : PIRQA# ==> NC(TP29) */ PAD_CFG_NC(GPP_A7), /* A8 : CLKRUN# ==> NC(TP45) */ PAD_CFG_NC(GPP_A8), @@ -40,8 +40,8 @@ PAD_CFG_NC(GPP_A11), /* A12 : BM_BUSY# ==> NC */ PAD_CFG_NC(GPP_A12), - /* A13 : SUSWARN# ==> NC */ - PAD_CFG_NC(GPP_A13), + /* A13 : SUSWARN# ==> SUSWARN_L */ + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* A14 : ESPI_RESET# */ /* A15 : SUSACK# ==> SUSACK_L */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), @@ -130,11 +130,11 @@ /* C8 : UART0_RXD ==> FP_INT */ PAD_CFG_GPI_APIC(GPP_C8, NONE, PLTRST), /* C9 : UART0_TXD ==> FP_RST_ODL */ - PAD_CFG_GPO(GPP_C9, 0, DEEP), /* FP_RST_ODL */ - /* C10 : UART0_RTS# ==> NC */ - PAD_CFG_NC(GPP_C10), - /* C11 : UART0_CTS# ==> NC */ - PAD_CFG_NC(GPP_C11), + PAD_CFG_GPO(GPP_C9, 0, DEEP), + /* C10 : UART0_RTS# ==> EC_CAM_PMIC_RST_L */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), + /* C11 : UART0_CTS# ==> EN_PP3300_DX_CAM */ + PAD_CFG_GPO(GPP_C11, 1, DEEP), /* C12 : UART1_RXD ==> PCH_MEM_CONFIG[0] */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* C13 : UART1_TXD ==> PCH_MEM_CONFIG[1] */ @@ -147,9 +147,9 @@ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* C17 : I2C0_SCL ==> PCH_I2C0_TOUCHSCREEN_3V3_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), - /* C18 : I2C1_SDA ==> PCH_I2C1_NFC_3V3_SDA */ + /* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), - /* C19 : I2C1_SCL ==> PCH_I2C1_NFC_3V3_SCL */ + /* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), @@ -190,8 +190,8 @@ PAD_CFG_NC(GPP_D13), /* D14 : ISH_UART0_TXD ==> NC */ PAD_CFG_NC(GPP_D14), - /* D15 : ISH_UART0_RTS# ==> MIC_IRQ_L */ - PAD_CFG_GPI_APIC(GPP_D15, NONE, PLTRST), + /* D15 : ISH_UART0_RTS# ==> NC */ + PAD_CFG_NC(GPP_D15), /* D16 : ISH_UART0_CTS# ==> NC */ PAD_CFG_NC(GPP_D16), /* D17 : DMIC_CLK1 */ @@ -217,14 +217,14 @@ PAD_CFG_NC(GPP_E2), /* E3 : CPU_GP0 ==> NC */ PAD_CFG_NC(GPP_E3), - /* E4 : SATA_DEVSLP0 ==> NFC_RESET_ODL */ - PAD_CFG_GPO(GPP_E4, 0, DEEP), - /* E5 : SATA_DEVSLP1 ==> NFC_INT_L */ - PAD_CFG_GPI_APIC(GPP_E5, NONE, PLTRST), - /* E6 : SATA_DEVSLP2 ==> NFC_FW_DL */ - PAD_CFG_GPO(GPP_E6, 0, DEEP), /* NFC_FW_DL */ + /* E4 : SATA_DEVSLP0 ==> NC */ + PAD_CFG_NC(GPP_E4), + /* E5 : SATA_DEVSLP1 ==> NC */ + PAD_CFG_NC(GPP_E5), + /* E6 : SATA_DEVSLP2 ==> NC */ + PAD_CFG_NC(GPP_E6), /* E7 : CPU_GP1 ==> TOUCHSCREEN_INT_L */ - PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* TOUCHSCREEN_INT_L */ + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), /* E8 : SATALED# ==> NC */ PAD_CFG_NC(GPP_E8), /* E9 : USB2_OCO# ==> USB_C0_OC_ODL */ @@ -346,7 +346,7 @@ /* GPD9: SLP_WLAN# ==> NC(TP25) */ PAD_CFG_NC(GPD9), /* GPD10: SLP_S5# ==> NC(TP15) */ - PAD_CFG_NC(GPD10), /* TP15 */ + PAD_CFG_NC(GPD10), /* GPD11: LANPHYC ==> NC */ PAD_CFG_NC(GPD11), }; @@ -362,6 +362,11 @@ /* B18 : GSPI0_MOSI ==> PCH_SPI_H1_3V3_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), + /* C18 : I2C1_SDA ==> PCH_I2C1_H1_3V3_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : I2C1_SCL ==> PCH_I2C1_H1_3V3_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* Ensure UART pins are in native mode for H1. */ /* C20 : UART2_RXD ==> PCHRX_SERVOTX_UART */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), -- To view, visit https://review.coreboot.org/19517 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I949a14bfaa7972f2257a0b11ee81dcb0771e2f7f Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: amd/pi/00670F00: Add AMD PSP support for Stoney Ridge
by build bot (Jenkins) (Code Review) 02 May '17

02 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19157 ) Change subject: amd/pi/00670F00: Add AMD PSP support for Stoney Ridge ...................................................................... Patch Set 17: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53094/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/8928/ : SUCCESS -- To view, visit https://review.coreboot.org/19157 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Icf111470b261d6516b878e88be471967abe681b3 Gerrit-PatchSet: 17 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: amd/pi/00670F00: Add AMD PSP support for Stoney Ridge
by Marshall Dawson (Code Review) 02 May '17

02 May '17

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/19157 ) Change subject: amd/pi/00670F00: Add AMD PSP support for Stoney Ridge ...................................................................... Patch Set 14: (7 comments) https://review.coreboot.org/#/c/19157/14/src/northbridge/amd/pi/00670F00/ps… File src/northbridge/amd/pi/00670F00/psp.c: Line 102: long usec_wait = 10000000; /* arbitrary 10 seconds */ > https://www.coreboot.org/Development_Guidelines#General_Guidelines > https://www.coreboot.org/Development_Guidelines#General_Guidelines good enough - done. Line 140: if (rd_mbox_sts(mbox) & STATUS_HALT) { > Turns out this is all within standard, C enums are just ints. Done - changed to #define Line 150: if (wait_initialized(mbox)) { > Yeah, I forgot it's the same with AGESA_SUCCESS. So no real need for "fix" Done Line 170: if (rd_mbox_sts(mbox) & (STATUS_ERROR || STATUS_TERMINATED)) { > bitwise, not boolean OR Done Line 184: void psp_notify_dram(void) > The only issue is that we don't let the platform/mainboard set policy then Done Line 191: buffer.header.size = sizeof(struct mbox_default_buffer); > PI equivalent MBOX_DEFAULT_BUFFER is only the header without reserve, so si > PI equivalent MBOX_DEFAULT_BUFFER is only the header without reserve, so size used here is not consistent with the reference. I see now. Removed reserved bytes from mbox_default_buffer. Line 196: status_to_string(cmd_status)); > The status_to_string() is indexed with cmd_status that is not the same as b > I think we just always show static "status=0" here, errors or no. I don't think that's correct. cmd_status can report timeout, PSP-in-recovery, etc. It uses the return value from send_psp_command() which can be affected by buffer->header.status. I can jam the return and see an error message. -- To view, visit https://review.coreboot.org/19157 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Icf111470b261d6516b878e88be471967abe681b3 Gerrit-PatchSet: 14 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: amd/pi/00670F00: Add AMD PSP support for Stoney Ridge
by Marshall Dawson (Code Review) 02 May '17

02 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19157 to look at the new patch set (#17). Change subject: amd/pi/00670F00: Add AMD PSP support for Stoney Ridge ...................................................................... amd/pi/00670F00: Add AMD PSP support for Stoney Ridge Add PSP communication support that is not covered by AGESA. The PSP must be notified DRAM is ready after amdinitpost(). Move amd_initcpuio() to the end of amdinitpost() so that the PSP decode for notify works. Change-Id: Icf111470b261d6516b878e88be471967abe681b3 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- M src/cpu/amd/pi/00670F00/romstage.c M src/northbridge/amd/pi/00670F00/Makefile.inc A src/northbridge/amd/pi/00670F00/psp.c A src/northbridge/amd/pi/00670F00/psp.h M src/northbridge/amd/pi/agesawrapper.c 5 files changed, 295 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/19157/17 -- To view, visit https://review.coreboot.org/19157 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: Icf111470b261d6516b878e88be471967abe681b3 Gerrit-PatchSet: 17 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: lib/edid.c: Return value differentiates absent and non-confo...
by Arthur Heymans (Code Review) 02 May '17

02 May '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/19502 ) Change subject: lib/edid.c: Return value differentiates absent and non-conformant ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/#/c/19502/5/src/drivers/parade/ps8640/ps8640.c File src/drivers/parade/ps8640/ps8640.c: Line 50: if (decode_edid(edid, edid_size, out) != EDID_CONFORMANT) { > Why do all these have to be changed? Why not just carefully assign the new it's indeed not necessary but I thought that since return value can now differentiate between absent and not conformant I'd make this explicit in code that uses return value without changing behavior. -- To view, visit https://review.coreboot.org/19502 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Id90aa210ff72092c4ab638a7bafb82bd11889bdc Gerrit-PatchSet: 5 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: lib/edid.c: Return value differentiates absent and non-confo...
by Julius Werner (Code Review) 02 May '17

02 May '17

Julius Werner has posted comments on this change. ( https://review.coreboot.org/19502 ) Change subject: lib/edid.c: Return value differentiates absent and non-conformant ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/#/c/19502/5/src/drivers/parade/ps8640/ps8640.c File src/drivers/parade/ps8640/ps8640.c: Line 50: if (decode_edid(edid, edid_size, out) != EDID_CONFORMANT) { Why do all these have to be changed? Why not just carefully assign the new return values so that EDID_CONFORMANT is 0, EDID_NON_CONFORMANT is -1 and EDID_ABSENT is -2 or something (so that you can still use a blanket (decode_edid() < 0) to check for conformance). -- To view, visit https://review.coreboot.org/19502 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Id90aa210ff72092c4ab638a7bafb82bd11889bdc Gerrit-PatchSet: 5 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: Yes

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Change in coreboot[master]: cbmem: Add new command line flag to dump console for one boo...
by Julius Werner (Code Review) 02 May '17

02 May '17

Julius Werner has submitted this change and it was merged. ( https://review.coreboot.org/19497 ) Change subject: cbmem: Add new command line flag to dump console for one boot only ...................................................................... cbmem: Add new command line flag to dump console for one boot only Even though the persistent CBMEM console is obviously awesome, there may be cases where we only want to look at console output from the last boot. It's easy to tell where one boot ends and another begins from the banner message that coreboot prints at the start of every stage, but in order to make it easier to find that point (especially for external tools), let's put that functionality straight into the cbmem utility with a new command line flag. Use the POSIX/libc regular expression API to find the banner string for maximum compatilibity, even though it's kinda icky. Change-Id: Ic17383507a884d84de9a2a880380cb15b25708a1 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/19497 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M util/cbmem/cbmem.c 1 file changed, 37 insertions(+), 4 deletions(-) Approvals: Aaron Durbin: Looks good to me, approved Philippe Mathieu-Daudé: Looks good to me, but someone else must approve Sumeet R Pawnikar: Looks good to me, but someone else must approve build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 7b7f10d..c1b1caa 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -31,6 +31,7 @@ #include <sys/mman.h> #include <libgen.h> #include <assert.h> +#include <regex.h> #include <commonlib/cbmem_id.h> #include <commonlib/timestamp_serialized.h> #include <commonlib/coreboot_tables.h> @@ -611,7 +612,7 @@ #define CBMC_OVERFLOW (1 << 31) /* dump the cbmem console */ -static void dump_console(void) +static void dump_console(int one_boot_only) { struct cbmem_console *console_p; char *console_c; @@ -659,8 +660,32 @@ for (cursor = 0; cursor < size; cursor++) if (!isprint(console_c[cursor]) && !isspace(console_c[cursor])) console_c[cursor] = '?'; - printf("%s\n", console_c); + /* We detect the last boot by looking for a bootblock, romstage or + ramstage banner, in that order (to account for platforms without + CONFIG_BOOTBLOCK_CONSOLE and/or CONFIG_EARLY_CONSOLE). Once we find + a banner, store the last match for that stage in cursor and stop. */ + cursor = 0; + if (one_boot_only) { +#define BANNER_REGEX(stage) "\n\ncoreboot-[^\n]* " stage " starting\\.\\.\\.\n" + const char *regex[] = { BANNER_REGEX("bootblock"), + BANNER_REGEX("romstage"), + BANNER_REGEX("ramstage")}; + int i; + + for (i = 0; !cursor && i < ARRAY_SIZE(regex); i++) { + regex_t re; + regmatch_t match; + assert(!regcomp(&re, regex[i], 0)); + + /* Keep looking for matches so we find the last one. */ + while (!regexec(&re, console_c + cursor, 1, &match, 0)) + cursor += match.rm_so + 1; + regfree(&re); + } + } + + puts(console_c + cursor); free(console_c); unmap_memory(); } @@ -936,6 +961,7 @@ printf("usage: %s [-cCltTxVvh?]\n", name); printf("\n" " -c | --console: print cbmem console\n" + " -1 | --oneboot: print cbmem console for last boot only\n" " -C | --coverage: dump coverage information\n" " -l | --list: print cbmem table of contents\n" " -x | --hexdump: print hexdump of cbmem area\n" @@ -1074,11 +1100,13 @@ int print_rawdump = 0; int print_timestamps = 0; int machine_readable_timestamps = 0; + int one_boot_only = 0; unsigned int rawdump_id = 0; int opt, option_index = 0; static struct option long_options[] = { {"console", 0, 0, 'c'}, + {"oneboot", 0, 0, '1'}, {"coverage", 0, 0, 'C'}, {"list", 0, 0, 'l'}, {"timestamps", 0, 0, 't'}, @@ -1090,11 +1118,16 @@ {"help", 0, 0, 'h'}, {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "cCltTxVvh?r:", + while ((opt = getopt_long(argc, argv, "c1CltTxVvh?r:", long_options, &option_index)) != EOF) { switch (opt) { case 'c': print_console = 1; + print_defaults = 0; + break; + case '1': + print_console = 1; + one_boot_only = 1; print_defaults = 0; break; case 'C': @@ -1211,7 +1244,7 @@ #endif if (print_console) - dump_console(); + dump_console(one_boot_only); if (print_coverage) dump_coverage(); -- To view, visit https://review.coreboot.org/19497 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: Ic17383507a884d84de9a2a880380cb15b25708a1 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins)

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Change in coreboot[master]: scarlet/gru: skip usbphy1 setup for Scarlet
by Julius Werner (Code Review) 02 May '17

02 May '17

Julius Werner has posted comments on this change. ( https://review.coreboot.org/19489 ) Change subject: scarlet/gru: skip usbphy1 setup for Scarlet ...................................................................... Patch Set 3: (3 comments) The mainboard code is accessing struct members from the SoC header, Paul, you can't change them independently. LGTM except for a few nits. https://review.coreboot.org/#/c/19489/3//COMMIT_MSG Commit Message: PS3, Line 2: philipchen This should say "Philip Chen". Can you double-check your git config? PS3, Line 7: scarlet/gru This would be better as "google/gru: ", probably, then you can keep the "Scarlet" at the end. https://review.coreboot.org/#/c/19489/3/src/mainboard/google/gru/mainboard.c File src/mainboard/google/gru/mainboard.c: PS3, Line 309: { nit: can remove braces -- To view, visit https://review.coreboot.org/19489 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I66e0d8a235cc9057964f7abca32bc692d41e88fd Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: Yes

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Change in coreboot[master]: sb/intel/i82801gx: Consolidate interrupt routing
by coreboot org (Code Review) 02 May '17

02 May '17

coreboot org has posted comments on this change. ( https://review.coreboot.org/19017 ) Change subject: sb/intel/i82801gx: Consolidate interrupt routing ...................................................................... Patch Set 8: Verified-1 Gigabyte GA-G41M-ES2L: Target OFFLINE. Test ABORTED. Asus P5GC-MX: Boot successful. Extended test FAILED.Asus P5GC-MX: DMESG_ACCESS_FAILURE -- To view, visit https://review.coreboot.org/19017 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I46838d2249c6fefedf9e2c63ade0812d22e7d627 Gerrit-PatchSet: 8 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-HasComments: No

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Change in coreboot[master]: mb/lenovo/s230u: fix sata port map for the msata port
by build bot (Jenkins) (Code Review) 02 May '17

02 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19523 ) Change subject: mb/lenovo/s230u: fix sata port map for the msata port ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53093/ : SUCCESS -- To view, visit https://review.coreboot.org/19523 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I1e9e96f0d0849b1e8c4e02aa4f686ceb5e10b3ab Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Anonymous Coward #1001586 Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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coreboot-gerrit May 2017