Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/19539 )
Change subject: mb/lenovo/x200: Make button on dock to undock work
......................................................................
Patch Set 1:
I don't really know why this works or if this could be further improved by removing other noop methods...
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Gerrit-MessageType: comment
Gerrit-Change-Id: Ib74408802e977d9caabcb815c9cbd06bd8dbe395
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
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Hello Patrick Rudolph, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/19500
to look at the new patch set (#19).
Change subject: nb/intel/gm45: Set display backlight according to EDID string
......................................................................
nb/intel/gm45: Set display backlight according to EDID string
Add some known good values for some thinkpads displays.
Known good means that at this pwm frequency the display is evenly lit
on all duty cycles, the display makes minimal to no noise at lower
duty cycles and the display does not flicker. This values differs from
vendor (which uses an obviously wrong display clock (190MHz instead
of 320MHz) resulting in frequency more than 60% off the intended
value.
TESTED on Thinkpad X200 with edid ascii string in list and removed
from list to see if notice message is shown.
Change-Id: Id7bc0d453fac31e806852206ba2c895720b2c843
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/mainboard/lenovo/t400/Makefile.inc
A src/mainboard/lenovo/t400/blc.c
M src/mainboard/lenovo/x200/Makefile.inc
A src/mainboard/lenovo/x200/blc.c
M src/mainboard/roda/rk9/Makefile.inc
A src/mainboard/roda/rk9/blc.c
M src/northbridge/intel/gm45/chip.h
M src/northbridge/intel/gm45/gm45.h
M src/northbridge/intel/gm45/gma.c
9 files changed, 147 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/19500/19
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Gerrit-Change-Id: Id7bc0d453fac31e806852206ba2c895720b2c843
Gerrit-PatchSet: 19
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Hello Patrick Rudolph, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/19500
to look at the new patch set (#18).
Change subject: nb/intel/gm45: Set display backlight according to EDID string
......................................................................
nb/intel/gm45: Set display backlight according to EDID string
Add some known good values for some thinkpads displays.
Known good means that at this pwm frequency the display is evenly lit
on all duty cycles, the display makes minimal to no noise at lower
duty cycles and the display does not flicker. This values differs from
vendor (which uses an obviously wrong display clock (190MHz instead
of 320MHz) resulting in frequency more than 60% off the intended
value.
TESTED on Thinkpad X200 with edid ascii string in list and removed
from list to see if notice message is shown.
Change-Id: Id7bc0d453fac31e806852206ba2c895720b2c843
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/mainboard/lenovo/t400/Makefile.inc
A src/mainboard/lenovo/t400/blc.c
M src/mainboard/lenovo/x200/Makefile.inc
A src/mainboard/lenovo/x200/blc.c
M src/mainboard/roda/rk9/Makefile.inc
A src/mainboard/roda/rk9/blc.c
M src/northbridge/intel/gm45/chip.h
M src/northbridge/intel/gm45/gm45.h
M src/northbridge/intel/gm45/gma.c
9 files changed, 147 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/19500/18
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Gerrit-Change-Id: Id7bc0d453fac31e806852206ba2c895720b2c843
Gerrit-PatchSet: 18
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/19535 )
Change subject: drivers/pc80/tpm: Fix missing tis_close() function and TPM deactivation.
......................................................................
Patch Set 1: Code-Review-2
According to the spec the TPM_Startup command can't be sent twice.
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Gerrit-Change-Id: I1a06f6a29015708e4bc1de6e6678827c28b84e98
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
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Werner Zeh has uploaded a new change for review. ( https://review.coreboot.org/19537 )
Change subject: fsp_broadwell_de: Switch CPU to high frequency mode
......................................................................
fsp_broadwell_de: Switch CPU to high frequency mode
According to Yang York the FSP is responsible for switching the CPU into
high frequency mode (HFM). For an unknown reason this is not done for the
BSP on my platform though the APs are switched properly.
This code switches the CPU into HFM which makes sure that all cores are in
high frequency mode before payload is started.
It should not harm the operation even if FSP was successful in switching
to HFM.
Change-Id: I91baf538511747d1692a8b6b359df5c3a8d56848
Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com>
---
M src/soc/intel/fsp_broadwell_de/cpu.c
M src/soc/intel/fsp_broadwell_de/include/soc/msr.h
2 files changed, 32 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/19537/1
diff --git a/src/soc/intel/fsp_broadwell_de/cpu.c b/src/soc/intel/fsp_broadwell_de/cpu.c
index 9d7fe98..68825a3 100644
--- a/src/soc/intel/fsp_broadwell_de/cpu.c
+++ b/src/soc/intel/fsp_broadwell_de/cpu.c
@@ -65,8 +65,38 @@
*parallel = 1;
}
+static int cpu_config_tdp_levels(void)
+{
+ msr_t platform_info;
+
+ /* Bits 34:33 indicate how many levels are supported. */
+ platform_info = rdmsr(MSR_PLATFORM_INFO);
+ return (platform_info.hi >> 1) & 3;
+}
+
+static void set_max_ratio(void)
+{
+ msr_t msr, perf_ctl;
+
+ perf_ctl.hi = 0;
+
+ /* Check for configurable TDP option. */
+ if (cpu_config_tdp_levels()) {
+ /* Set to nominal TDP ratio. */
+ msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
+ perf_ctl.lo = (msr.lo & 0xff) << 8;
+ } else {
+ /* Platform Info Bits 15:8 give max ratio. */
+ msr = rdmsr(MSR_PLATFORM_INFO);
+ perf_ctl.lo = msr.lo & 0xff00;
+ }
+ wrmsr(IA32_PERF_CTL, perf_ctl);
+}
+
static void post_mp_init(void)
{
+ /* Set Max Ratio */
+ set_max_ratio();
/* Now that all APs have been relocated as well as the BSP let SMIs
start flowing. */
southbridge_smm_enable_smi();
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h
index f5ea34c..6b87061 100644
--- a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h
+++ b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h
@@ -21,10 +21,12 @@
#define MSR_IA32_PLATFORM_ID 0x17
#define MSR_CORE_THREAD_COUNT 0x35
#define MSR_PLATFORM_INFO 0xce
+#define IA32_PERF_CTL 0x199
#define MSR_TURBO_RATIO_LIMIT 0x1ad
#define MSR_IA32_MC0_STATUS 0x400
#define MSR_PKG_POWER_SKU_UNIT 0x606
#define MSR_PKG_POWER_LIMIT 0x610
+#define MSR_CONFIG_TDP_NOMINAL 0x648
#define SMM_MCA_CAP_MSR 0x17d
#define SMM_CPU_SVRSTR_BIT 57
--
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Gerrit-Change-Id: I91baf538511747d1692a8b6b359df5c3a8d56848
Gerrit-PatchSet: 1
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Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com>