Duncan Laurie has uploaded a new change for review. ( https://review.coreboot.org/19549 )
Change subject: mb/google/eve: Set SUSWARN# pin to native function
......................................................................
mb/google/eve: Set SUSWARN# pin to native function
Set GPP_A13/SUSWARN# pin mode to native function 1. This pin is tied
to SUSACK# in the schematic and and is intented to be used in Deep Sx
so it should not be configured for GPIO mode.
BUG=b:35581264
TEST=build and boot on Eve platform, test that Deep S3 and Deep S5
are still functional. (this change should have no visible effect)
Change-Id: Ie2dc24d095872ab93a5bfcbe5307c3b7a8e4dbcc
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
---
M src/mainboard/google/eve/gpio.h
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/19549/1
diff --git a/src/mainboard/google/eve/gpio.h b/src/mainboard/google/eve/gpio.h
index 6da8244..ed0d712 100644
--- a/src/mainboard/google/eve/gpio.h
+++ b/src/mainboard/google/eve/gpio.h
@@ -58,7 +58,7 @@
/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10),
/* PME# */ PAD_CFG_NC(GPP_A11), /* TP67 */
/* BM_BUSY# */ PAD_CFG_NC(GPP_A12),
-/* SUSWARN# */ PAD_CFG_NC(GPP_A13),
+/* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
/* ESPI_RESET# */
/* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16),
--
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Gerrit-MessageType: newchange
Gerrit-Change-Id: Ie2dc24d095872ab93a5bfcbe5307c3b7a8e4dbcc
Gerrit-PatchSet: 1
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Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/19547 )
Change subject: nb/intel/sandybridge/early_init: Use register name
......................................................................
Patch Set 1: Code-Review+2
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/19546 )
Change subject: sb/intel/bd82x6x/bootblock: Use register name
......................................................................
Patch Set 1: Code-Review+2
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/19545 )
Change subject: sb/intel/bd82x6x/finalize: Use register name
......................................................................
Patch Set 1: Code-Review+2
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/19544 )
Change subject: nb/intel/sandybridge/romstage: Use register name
......................................................................
Patch Set 1: Code-Review+2
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