coreboot-gerrit May 2017

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Change in coreboot[master]: drivers/pc80/tpm: Refactor init_tpm() implementation
by Philipp Deppenwiese (Code Review) 03 May '17

03 May '17

Philipp Deppenwiese has uploaded a new change for review. ( https://review.coreboot.org/19555 ) Change subject: drivers/pc80/tpm: Refactor init_tpm() implementation ...................................................................... drivers/pc80/tpm: Refactor init_tpm() implementation Move the TPM deactivate command after the tis_init() function in order to ensure that there is a TPM which can be used. Add additional doc for CONFIG_NO_TPM_RESUME kconfig option which is mainly used by chromebooks. Add TPM_PcrRead command for TPM state retrieval by calling it. Now the TPM state is logged. Also if TPM deactivate is enforced and something is wrong it will jump directly to the error handling. Change-Id: I2c51ce402f43466e211bc1990335fd320d685829 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- M src/drivers/pc80/tpm/romstage.c 1 file changed, 64 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/19555/1 diff --git a/src/drivers/pc80/tpm/romstage.c b/src/drivers/pc80/tpm/romstage.c index a6167a4..85ce641 100644 --- a/src/drivers/pc80/tpm/romstage.c +++ b/src/drivers/pc80/tpm/romstage.c @@ -30,6 +30,8 @@ #define TPM_E_COMMUNICATION_ERROR ((u32)0x00005004) #define TPM_E_NON_FATAL ((u32)0x00000800) #define TPM_E_INVALID_POSTINIT ((u32)0x00000026) +#define TPM_E_DEACTIVATED ((u32)0x00000006) +#define TPM_E_DISABLED ((u32)0x00000007) #define TPM_E_NEEDS_SELFTEST ((u32)(TPM_E_NON_FATAL + 1)) #define TPM_E_DOING_SELFTEST ((u32)(TPM_E_NON_FATAL + 2)) @@ -56,6 +58,13 @@ u8 buffer[10]; } tpm_continueselftest_cmd = { { 0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x53 } +}; + +static const struct { + u8 buffer[14]; + u16 pcrNum; +} tpm_pcr_read_cmd = { + {0x0, 0xc1, 0x0, 0x0, 0x0, 0xe, 0x0, 0x0, 0x0, 0x15, }, 10, }; static inline void FromTpmUint32(const u8 * buffer, u32 * x) @@ -183,20 +192,8 @@ u32 result; u8 response[TPM_LARGE_ENOUGH_COMMAND_SIZE]; - if (IS_ENABLED(CONFIG_TPM_DEACTIVATE)) { - printk(BIOS_SPEW, "TPM: Deactivate\n"); - result = TlclSendReceive(tpm_deactivate_cmd.buffer, - response, sizeof(response)); - if (result == TPM_SUCCESS) { - printk(BIOS_SPEW, "TPM: OK.\n"); - return; - } - - printk(BIOS_ERR, "TPM: Error code 0x%x.\n", result); - return; - } - - /* Doing TPM startup when we're not coming in on the S3 resume path + /* CHROMEOS hack to be faster but not recommended for normal tpm usage. + * Doing TPM startup when we're not coming in on the S3 resume path * saves us roughly 20ms in boot time only. This does not seem to * be worth an API change to vboot_reference-firmware right now, so * let's keep the code around, but just bail out early: @@ -215,31 +212,63 @@ if (tis_open()) return; - if (s3resume) { - /* S3 Resume */ - printk(BIOS_SPEW, "TPM: Resume\n"); - result = TlclSendReceive(tpm_resume_cmd.buffer, + if (IS_ENABLED(CONFIG_TPM_DEACTIVATE)) { + printk(BIOS_SPEW, "TPM: PhysicalDeactivate\n"); + result = TlclSendReceive(tpm_deactivate_cmd.buffer, response, sizeof(response)); - if (result == TPM_E_INVALID_POSTINIT) { - /* We're on a platform where the TPM maintains power - * in S3, so it's already initialized. - */ - printk(BIOS_DEBUG, "TPM: Already initialized.\n"); - tis_close(); - return; - } } else { - printk(BIOS_SPEW, "TPM: Startup\n"); - result = TlclSendReceive(tpm_startup_cmd.buffer, - response, sizeof(response)); + if (s3resume) { + /* S3 Resume */ + printk(BIOS_SPEW, "TPM: Resume\n"); + result = TlclSendReceive(tpm_resume_cmd.buffer, + response, sizeof(response)); + if (result == TPM_E_INVALID_POSTINIT) { + + /* We're on a platform where the TPM maintains power + * in S3, so it's already initialized. + */ + printk(BIOS_DEBUG, "TPM: Already initialized.\n"); + tis_close(); + return; + } + } else { + printk(BIOS_SPEW, "TPM: Startup\n"); + result = TlclSendReceive(tpm_startup_cmd.buffer, + response, sizeof(response)); + } } - if (result == TPM_SUCCESS) { - printk(BIOS_SPEW, "TPM: OK.\n"); - tis_close(); - return; + if (result != TPM_SUCCESS) + goto error; + + printk(BIOS_SPEW, "Get TPM status information\n"); + result = TlclSendReceive(tpm_pcr_read_cmd.buffer, + response, sizeof(response)); + + switch (result) { + case TPM_E_DEACTIVATED: + printk(BIOS_INFO, "TPM is deactivated via PPI!\n"); + break; + case TPM_E_DISABLED: + printk(BIOS_INFO, "TPM is disabled via PPI!\n"); + break; + case TPM_SUCCESS: + if (IS_ENABLED(CONFIG_TPM_DEACTIVATE)) { + printk(BIOS_INFO, "TPM is active that shouldn't happen!\n"); + goto error; + } else { + printk(BIOS_INFO, "TPM is running!\n"); + } + break; + default: + goto error; } + printk(BIOS_SPEW, "TPM: OK.\n"); + tis_close(); + return; + +error: printk(BIOS_ERR, "TPM: Error code 0x%x.\n", result); if (IS_ENABLED(CONFIG_TPM_INIT_FAILURE_IS_FATAL)) { @@ -248,5 +277,7 @@ if (IS_ENABLED(CONFIG_CONSOLE_CBMEM_DUMP_TO_UART)) cbmem_dump_console(); hard_reset(); + } else { + tis_close(); } } -- To view, visit https://review.coreboot.org/19555 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I2c51ce402f43466e211bc1990335fd320d685829 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>

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Change in coreboot[master]: google/fizz: Configure SATAXPCIe GPIOs to use native function
by Furquan Shaikh (Code Review) 03 May '17

03 May '17

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/19554 ) Change subject: google/fizz: Configure SATAXPCIe GPIOs to use native function ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/19554 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I4a85b9f3ba1d0a4c0a753420e166d3353417a1d1 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: mb/lenovo/t400: Generate undock event with dock button
by build bot (Jenkins) (Code Review) 03 May '17

03 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19551 ) Change subject: mb/lenovo/t400: Generate undock event with dock button ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53153/ : SUCCESS -- To view, visit https://review.coreboot.org/19551 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I1161ed5f5c30201d2ad156d8fce4e8a90e65bff6 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: mb/lenovo/t400: Generate undock event with dock button
by Arthur Heymans (Code Review) 03 May '17

03 May '17

Hello Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19551 to look at the new patch set (#2). Change subject: mb/lenovo/t400: Generate undock event with dock button ...................................................................... mb/lenovo/t400: Generate undock event with dock button Change-Id: I1161ed5f5c30201d2ad156d8fce4e8a90e65bff6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/t400/acpi/dock.asl 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/19551/2 -- To view, visit https://review.coreboot.org/19551 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I1161ed5f5c30201d2ad156d8fce4e8a90e65bff6 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: google/fizz: Enable SATA ports
by Furquan Shaikh (Code Review) 03 May '17

03 May '17

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/19553 ) Change subject: google/fizz: Enable SATA ports ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/19553/1//COMMIT_MSG Commit Message: PS1, Line 7: google/fizz soc/intel/skylake https://review.coreboot.org/#/c/19553/1/src/soc/intel/skylake/sata.c File src/soc/intel/skylake/sata.c: PS1, Line 49: u32 temp Put declaration at the start of the function. -- To view, visit https://review.coreboot.org/19553 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I8525f6f5ddfdf61c564febd86b1ba2e01c22d9e5 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: google/fizz: Configure SATAXPCIe GPIOs to use native function
by build bot (Jenkins) (Code Review) 03 May '17

03 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19554 ) Change subject: google/fizz: Configure SATAXPCIe GPIOs to use native function ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53152/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/8983/ : SUCCESS -- To view, visit https://review.coreboot.org/19554 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I4a85b9f3ba1d0a4c0a753420e166d3353417a1d1 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: google/fizz: Enable SATA ports
by build bot (Jenkins) (Code Review) 03 May '17

03 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19553 ) Change subject: google/fizz: Enable SATA ports ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53151/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/8982/ : SUCCESS -- To view, visit https://review.coreboot.org/19553 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I8525f6f5ddfdf61c564febd86b1ba2e01c22d9e5 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: google/fizz: Enable devices under pci 1c.0
by build bot (Jenkins) (Code Review) 03 May '17

03 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19533 ) Change subject: google/fizz: Enable devices under pci 1c.0 ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53150/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/8981/ : SUCCESS -- To view, visit https://review.coreboot.org/19533 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ide66823283c58d2bea0c9886f762f0581741affe Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: google/fizz: Configure SATAXPCIe GPIOs to use native function
by Shelley Chen (Code Review) 03 May '17

03 May '17

Shelley Chen has uploaded a new change for review. ( https://review.coreboot.org/19554 ) Change subject: google/fizz: Configure SATAXPCIe GPIOs to use native function ...................................................................... google/fizz: Configure SATAXPCIe GPIOs to use native function BUG=b:37486021, b:35775024 BRANCH=None TEST=reboot and ensure that device detects SSD Change-Id: I4a85b9f3ba1d0a4c0a753420e166d3353417a1d1 Signed-off-by: Shelley Chen <shchen(a)chromium.org> --- M src/mainboard/google/fizz/gpio.h 1 file changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/19554/1 diff --git a/src/mainboard/google/fizz/gpio.h b/src/mainboard/google/fizz/gpio.h index 1cd9d53..0950c76 100644 --- a/src/mainboard/google/fizz/gpio.h +++ b/src/mainboard/google/fizz/gpio.h @@ -143,9 +143,10 @@ /* SATAXPCI0 */ PAD_CFG_GPI_APIC_INVERT(GPP_E0, NONE, PLTRST), /* H1_PCH_INT_ODL */ -/* SATAXPCIE1 */ PAD_CFG_GPI(GPP_E1, NONE, DEEP), /* MB_PCIE_SATA#_DET */ -/* SATAXPCIE2 */ PAD_CFG_GPI(GPP_E2, 20K_PU, - DEEP), /* DB_PCIE_SATA#_DET */ +/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, + NF1), /* MB_PCIE_SATA#_DET */ +/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, 20K_PU, DEEP, + NF1), /* DB_PCIE_SATA#_DET */ /* CPU_GP0 */ PAD_CFG_NC(GPP_E3), /* SATA_DEVSLP0 */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), /* DEVSLP0_MB */ /* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* DEVSLP1_DB */ -- To view, visit https://review.coreboot.org/19554 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I4a85b9f3ba1d0a4c0a753420e166d3353417a1d1 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Shelley Chen <shchen(a)google.com>

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Change in coreboot[master]: google/fizz: Enable SATA ports
by Shelley Chen (Code Review) 03 May '17

03 May '17

Shelley Chen has uploaded a new change for review. ( https://review.coreboot.org/19553 ) Change subject: google/fizz: Enable SATA ports ...................................................................... google/fizz: Enable SATA ports Previous implementation was incorrect and was actually disabling the ports. BUG=b:37486021, b:35775024 BRANCH=None TEST=reboot and ensure that we can boot from SATA SSD. Change-Id: I8525f6f5ddfdf61c564febd86b1ba2e01c22d9e5 Signed-off-by: Shelley Chen <shchen(a)chromium.org> --- M src/soc/intel/skylake/sata.c 1 file changed, 6 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/19553/1 diff --git a/src/soc/intel/skylake/sata.c b/src/soc/intel/skylake/sata.c index c110436..2027b03 100644 --- a/src/soc/intel/skylake/sata.c +++ b/src/soc/intel/skylake/sata.c @@ -40,14 +40,16 @@ static void sata_final(device_t dev) { void *ahcibar = get_ahci_bar(); - u8 port_impl; + u32 port_impl; dev = PCH_DEV_SATA; /* Read Ports Implemented (GHC_PI) */ - port_impl = read32(ahcibar + 0x0c); - port_impl = ~port_impl & 0x07; + port_impl = read32(ahcibar + 0x0c) & 0x07; /* Port enable */ - pci_write_config8(dev, 0x92, port_impl); + u32 temp = pci_read_config32(dev, 0x92); + temp |= port_impl; + pci_write_config32(dev, 0x92, temp); + } static struct device_operations sata_ops = { -- To view, visit https://review.coreboot.org/19553 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I8525f6f5ddfdf61c564febd86b1ba2e01c22d9e5 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Shelley Chen <shchen(a)google.com>

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coreboot-gerrit May 2017