Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/19553
to look at the new patch set (#3).
Change subject: soc/intel/skylake: Enable SATA ports
......................................................................
soc/intel/skylake: Enable SATA ports
Previous implementation was incorrect and was
actually disabling the ports.
BUG=b:37486021, b:35775024
BRANCH=None
TEST=reboot and ensure that we can boot from
SATA SSD.
Change-Id: I8525f6f5ddfdf61c564febd86b1ba2e01c22d9e5
Signed-off-by: Shelley Chen <shchen(a)chromium.org>
---
M src/soc/intel/skylake/sata.c
1 file changed, 6 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/19553/3
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Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I8525f6f5ddfdf61c564febd86b1ba2e01c22d9e5
Gerrit-PatchSet: 3
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Shelley Chen <shchen(a)google.com>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/19555
to look at the new patch set (#2).
Change subject: drivers/pc80/tpm: Refactor init_tpm() implementation
......................................................................
drivers/pc80/tpm: Refactor init_tpm() implementation
Move the TPM deactivate command after the tis_init()
function in order to ensure that there is a TPM which
can be used.
Add additional doc for CONFIG_NO_TPM_RESUME kconfig option
which is mainly used by chromebooks.
Add TPM_PcrRead command for TPM state retrieval by calling
it. Now the TPM state is logged. Also if TPM deactivate is
enforced and something is wrong it will jump directly to
the error handling.
Change-Id: I2c51ce402f43466e211bc1990335fd320d685829
Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org>
---
M src/drivers/pc80/tpm/romstage.c
1 file changed, 62 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/19555/2
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Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I2c51ce402f43466e211bc1990335fd320d685829
Gerrit-PatchSet: 2
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Lee Leahy has posted comments on this change. ( https://review.coreboot.org/19534 )
Change subject: Documentation/Intel: Add vboot documentation
......................................................................
Patch Set 2:
(6 comments)
https://review.coreboot.org/#/c/19534/2/Documentation/Intel/vboot.html
File Documentation/Intel/vboot.html:
PS2, Line 50: typically 1/4th of the SPI flash
> That's really platform specific. Do you think it actually matters to call t
Added platform specific
PS2, Line 92: key
> mention RSA since we're talking about key lengths?
Done
PS2, Line 215: COLLECT_TIMESTAMPS
> Is this just a side effect of how the code is written now? There's no real
This may be a side effect of the current code, but is currently required to successfully build vboot.
PS2, Line 226: RAM
> SRAM?
Done
PS2, Line 251: be built several times
> built? It's just added to cbfstool in multiple cbfs regions.
Fixed
PS2, Line 282: 0x100,0x1000,0x7ce80,0x1000
> Add a description for the magic constants and what they do? the same is tur
Done
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Gerrit-MessageType: comment
Gerrit-Change-Id: Ie17b8443772f596de0c9d8afe6f4ec3ac4d4fef8
Gerrit-PatchSet: 2
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Lee Leahy <leroy.p.leahy(a)intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-HasComments: Yes
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/19534
to look at the new patch set (#3).
Change subject: Documentation/Intel: Add vboot documentation
......................................................................
Documentation/Intel: Add vboot documentation
Add documentation which describes how to build and sign a coreboot image
which enables vboot.
TEST=None
Change-Id: Ie17b8443772f596de0c9d8afe6f4ec3ac4d4fef8
Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com>
---
M Documentation/Intel/index.html
A Documentation/Intel/vboot.html
2 files changed, 403 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/19534/3
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Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Ie17b8443772f596de0c9d8afe6f4ec3ac4d4fef8
Gerrit-PatchSet: 3
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Lee Leahy <leroy.p.leahy(a)intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/19553
to look at the new patch set (#2).
Change subject: google/fizz: Enable SATA ports
......................................................................
google/fizz: Enable SATA ports
Previous implementation was incorrect and was
actually disabling the ports.
BUG=b:37486021, b:35775024
BRANCH=None
TEST=reboot and ensure that we can boot from
SATA SSD.
Change-Id: I8525f6f5ddfdf61c564febd86b1ba2e01c22d9e5
Signed-off-by: Shelley Chen <shchen(a)chromium.org>
---
M src/soc/intel/skylake/sata.c
1 file changed, 6 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/19553/2
--
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Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I8525f6f5ddfdf61c564febd86b1ba2e01c22d9e5
Gerrit-PatchSet: 2
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Shelley Chen <shchen(a)google.com>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>