coreboot-gerrit May 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: pci_device: add PCI device IDs for Intel platforms
by Rizwan Qureshi (Code Review) 04 May '17

04 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19541 to look at the new patch set (#2). Change subject: pci_device: add PCI device IDs for Intel platforms ...................................................................... pci_device: add PCI device IDs for Intel platforms Add host of PCI device Ids for IPs in Intel platforms. Change-Id: I0eee9409df3e6dc326b60bc82c2b715c70e7debd Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/include/device/pci_ids.h 1 file changed, 106 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/19541/2 -- To view, visit https://review.coreboot.org/19541 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I0eee9409df3e6dc326b60bc82c2b715c70e7debd Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mainboard/google/poppy: Enable MODE_CHANGE event in SCI_MASK
by Furquan Shaikh (Code Review) 04 May '17

04 May '17

Furquan Shaikh has uploaded a new change for review. ( https://review.coreboot.org/19559 ) Change subject: mainboard/google/poppy: Enable MODE_CHANGE event in SCI_MASK ...................................................................... mainboard/google/poppy: Enable MODE_CHANGE event in SCI_MASK This is required to ensure that SCI is generated whenever a host event is set for MODE_CHANGE. Thus, when wake from MODE_CHANGE event occurs, eSPI SCI is generated which results in kernel handler reading host event from the EC and thus causes the wake pin to be de-asserted. BUG=b:37223093 TEST=Verified that wake from mode change event works fine in suspend mode and there is no interrupt storm for GPE SCI after resume. Change-Id: I1dd158ea0e302d5be9bcaa531cd1851082ba59fd Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/mainboard/google/poppy/variants/baseboard/include/baseboard/ec.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/19559/1 diff --git a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/ec.h index 8be83f3..5d6cf4c 100644 --- a/src/mainboard/google/poppy/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/poppy/variants/baseboard/include/baseboard/ec.h @@ -35,6 +35,7 @@ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP)) #define MAINBOARD_EC_SMI_EVENTS \ -- To view, visit https://review.coreboot.org/19559 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I1dd158ea0e302d5be9bcaa531cd1851082ba59fd Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: google/gru: support 800M/928M frequency for bob
by build bot (Jenkins) (Code Review) 04 May '17

04 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19558 ) Change subject: google/gru: support 800M/928M frequency for bob ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53170/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/8997/ : SUCCESS -- To view, visit https://review.coreboot.org/19558 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I613050292a09ff56f4636d7af285075e32259ef4 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: rockchip: rk3399: enable DPLL SSC for DDR EMI test on bob
by build bot (Jenkins) (Code Review) 04 May '17

04 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19557 ) Change subject: rockchip: rk3399: enable DPLL SSC for DDR EMI test on bob ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53169/ : SUCCESS -- To view, visit https://review.coreboot.org/19557 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I75461d4235bcf55324e6664a1220754e770b4786 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: google/gru: support 800M/928M frequency for bob
by Caesar Wang (Code Review) 04 May '17

04 May '17

Hello Julius Werner, Philip Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/19558 to review the following change. Change subject: google/gru: support 800M/928M frequency for bob ...................................................................... google/gru: support 800M/928M frequency for bob In order to support the 800M/928M frequency for bob. We will use the ram_id and board_id to select the board on bob. Change-Id: I613050292a09ff56f4636d7af285075e32259ef4 Signed-off-by: Caesar Wang <wxt(a)rock-chips.com> --- M src/mainboard/google/gru/Kconfig M src/mainboard/google/gru/Makefile.inc M src/mainboard/google/gru/sdram_configs.c M src/mainboard/google/gru/sdram_params_800/Makefile.inc M src/mainboard/google/gru/sdram_params_933/Makefile.inc 5 files changed, 32 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/19558/1 diff --git a/src/mainboard/google/gru/Kconfig b/src/mainboard/google/gru/Kconfig index 0fce7cc..1bae084 100644 --- a/src/mainboard/google/gru/Kconfig +++ b/src/mainboard/google/gru/Kconfig @@ -94,13 +94,6 @@ default "Gru" if BOARD_GOOGLE_GRU default "Kevin" if BOARD_GOOGLE_KEVIN -# The default max sdram freq is 933M(actually 928M dpll), and -# 800M is another choice. -config MAX_SDRAM_FREQ - int - default 800 if BOARD_GOOGLE_BOB - default 933 - config GBB_HWID string depends on CHROMEOS diff --git a/src/mainboard/google/gru/Makefile.inc b/src/mainboard/google/gru/Makefile.inc index d54ce2f..9972c5b 100644 --- a/src/mainboard/google/gru/Makefile.inc +++ b/src/mainboard/google/gru/Makefile.inc @@ -13,7 +13,7 @@ ## GNU General Public License for more details. ## -subdirs-y += sdram_params_$(CONFIG_MAX_SDRAM_FREQ)/ +subdirs-y += sdram_params_800/ sdram_params_933/ bootblock-y += bootblock.c bootblock-y += chromeos.c diff --git a/src/mainboard/google/gru/sdram_configs.c b/src/mainboard/google/gru/sdram_configs.c index b9f77d0..a9264d5 100644 --- a/src/mainboard/google/gru/sdram_configs.c +++ b/src/mainboard/google/gru/sdram_configs.c @@ -22,22 +22,37 @@ #include <string.h> #include <types.h> -static const char *sdram_configs[] = { - [0] = "sdram-lpddr3-hynix-4GB", - [3] = "sdram-lpddr3-samsung-2GB-24EB", - [4] = "sdram-lpddr3-micron-2GB", - [5] = "sdram-lpddr3-samsung-4GB-04EB", - [6] = "sdram-lpddr3-micron-4GB", +#define MAX_SDRAM_CONFIGS 10 + +static const char *sdram_configs_800[MAX_SDRAM_CONFIGS] = { + [3] = "sdram-lpddr3-samsung-2GB-24EB-800", + [4] = "sdram-lpddr3-micron-2GB-800", + [5] = "sdram-lpddr3-samsung-4GB-04EB-800", + [6] = "sdram-lpddr3-micron-4GB-800", +}; + +static const char *sdram_configs_933[MAX_SDRAM_CONFIGS] = { + [0] = "sdram-lpddr3-hynix-4GB-933", + [3] = "sdram-lpddr3-samsung-2GB-24EB-933", + [4] = "sdram-lpddr3-micron-2GB-933", + [5] = "sdram-lpddr3-samsung-4GB-04EB-933", + [6] = "sdram-lpddr3-micron-4GB-933", }; static struct rk3399_sdram_params params; const struct rk3399_sdram_params *get_sdram_config() { + const char **sdram_configs; uint32_t ramcode; + if (IS_ENABLED(CONFIG_BOARD_GOOGLE_BOB) && board_id() < 4) + sdram_configs = sdram_configs_800; + else + sdram_configs = sdram_configs_933; + ramcode = ram_code(); - if (ramcode >= ARRAY_SIZE(sdram_configs) || !sdram_configs[ramcode] || + if (ramcode >= MAX_SDRAM_CONFIGS || !sdram_configs[ramcode] || (cbfs_boot_load_struct(sdram_configs[ramcode], &params, sizeof(params)) != sizeof(params))) die("Cannot load SDRAM parameter file!"); diff --git a/src/mainboard/google/gru/sdram_params_800/Makefile.inc b/src/mainboard/google/gru/sdram_params_800/Makefile.inc index ca7b52b..56dd390 100644 --- a/src/mainboard/google/gru/sdram_params_800/Makefile.inc +++ b/src/mainboard/google/gru/sdram_params_800/Makefile.inc @@ -13,15 +13,18 @@ ## GNU General Public License for more details. ## +freq := 800 + sdram-params := sdram-params += sdram-lpddr3-samsung-2GB-24EB sdram-params += sdram-lpddr3-micron-2GB sdram-params += sdram-lpddr3-samsung-4GB-04EB sdram-params += sdram-lpddr3-micron-4GB +sdram-params := $(addsuffix -$(freq), $(sdram-params)) $(foreach params,$(sdram-params), \ $(eval cbfs-files-y += $(params)) \ - $(eval $(params)-file := $(params).c:struct) \ + $(eval $(params)-file := $(patsubst %-$(freq),%.c:struct, $(params))) \ $(eval $(params)-type := struct) \ $(eval $(params)-compression := $(CBFS_COMPRESS_FLAG)) \ ) diff --git a/src/mainboard/google/gru/sdram_params_933/Makefile.inc b/src/mainboard/google/gru/sdram_params_933/Makefile.inc index 8751e53..ce3ae60 100644 --- a/src/mainboard/google/gru/sdram_params_933/Makefile.inc +++ b/src/mainboard/google/gru/sdram_params_933/Makefile.inc @@ -1,7 +1,7 @@ ## ## This file is part of the coreboot project. ## -## Copyright 2016 Rockchip Inc. +## Copyright 2017 Rockchip Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -13,16 +13,19 @@ ## GNU General Public License for more details. ## +freq := 933 + sdram-params := sdram-params += sdram-lpddr3-hynix-4GB sdram-params += sdram-lpddr3-samsung-2GB-24EB sdram-params += sdram-lpddr3-micron-2GB sdram-params += sdram-lpddr3-samsung-4GB-04EB sdram-params += sdram-lpddr3-micron-4GB +sdram-params := $(addsuffix -$(freq), $(sdram-params)) $(foreach params,$(sdram-params), \ $(eval cbfs-files-y += $(params)) \ - $(eval $(params)-file := $(params).c:struct) \ + $(eval $(params)-file := $(patsubst %-$(freq),%.c:struct, $(params))) \ $(eval $(params)-type := struct) \ $(eval $(params)-compression := $(CBFS_COMPRESS_FLAG)) \ ) -- To view, visit https://review.coreboot.org/19558 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I613050292a09ff56f4636d7af285075e32259ef4 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com>

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Change in coreboot[master]: rockchip: rk3399: enable DPLL SSC for DDR EMI test on bob
by Caesar Wang (Code Review) 04 May '17

04 May '17

Hello Julius Werner, Philip Chen, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19557 to look at the new patch set (#3). Change subject: rockchip: rk3399: enable DPLL SSC for DDR EMI test on bob ...................................................................... rockchip: rk3399: enable DPLL SSC for DDR EMI test on bob Spread Spectrum Modulator(SSMOD) is a fully-digital circuit used to modulate the frequency of the Silicon Creations’ Fractional PLL in order to reduce EMI. We need to turn the DPLL spread spectrum feature on to reduce the EMI noise for DDR on bob. Change-Id: I75461d4235bcf55324e6664a1220754e770b4786 Signed-off-by: Xing Zheng <zhengxing(a)rock-chips.com> Signed-off-by: Caesar Wang <wxt(a)rock-chips.com> --- M src/soc/rockchip/rk3399/Kconfig M src/soc/rockchip/rk3399/clock.c 2 files changed, 65 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/19557/3 -- To view, visit https://review.coreboot.org/19557 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I75461d4235bcf55324e6664a1220754e770b4786 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: rockchip: rk3399: enable DPLL SSC for DDR EMI test on bob
by build bot (Jenkins) (Code Review) 04 May '17

04 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19557 ) Change subject: rockchip: rk3399: enable DPLL SSC for DDR EMI test on bob ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53168/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/8996/ : SUCCESS -- To view, visit https://review.coreboot.org/19557 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I75461d4235bcf55324e6664a1220754e770b4786 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: rockchip: rk3399: enable DPLL SSC for DDR EMI test on bob
by Caesar Wang (Code Review) 04 May '17

04 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19557 to look at the new patch set (#2). Change subject: rockchip: rk3399: enable DPLL SSC for DDR EMI test on bob ...................................................................... rockchip: rk3399: enable DPLL SSC for DDR EMI test on bob Spread Spectrum Modulator(SSMOD) is a fully-digital circuit used to modulate the frequency of the Silicon Creations’ Fractional PLL in order to reduce EMI. We need to turn the DPLL spread spectrum feature on to reduce the EMI noise for DDR on bob. BRANCH=none BUG=b:37262721 TEST=mem checks the register value on bob. localhost / # mem r 0xff76004c 0x00000100 localhost / # mem r 0xff760050 0x00000860 TEST=Test with memtester/s2r on bob. Change-Id: I75461d4235bcf55324e6664a1220754e770b4786 Signed-off-by: Xing Zheng <zhengxing(a)rock-chips.com> Signed-off-by: Caesar Wang <wxt(a)rock-chips.com> --- M src/soc/rockchip/rk3399/Kconfig M src/soc/rockchip/rk3399/clock.c 2 files changed, 65 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/19557/2 -- To view, visit https://review.coreboot.org/19557 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I75461d4235bcf55324e6664a1220754e770b4786 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/gigabyte/ga-b75m-d3h: add libgfxinit support
by Bill XIE (Code Review) 04 May '17

04 May '17

Bill XIE has posted comments on this change. ( https://review.coreboot.org/19522 ) Change subject: mb/gigabyte/ga-b75m-d3h: add libgfxinit support ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/#/c/19522/1//COMMIT_MSG Commit Message: PS1, Line 9: > Thanks, Linux falls back to default modes <= 1024x786, <= 61Hz Yes, this time the xrandr's output looks like this: Screen 0: minimum 8 x 8, current 1024 x 768, maximum 32767 x 32767 DP1 disconnected primary (normal left inverted right x axis y axis) DP2 disconnected (normal left inverted right x axis y axis) HDMI1 disconnected (normal left inverted right x axis y axis) HDMI2 disconnected (normal left inverted right x axis y axis) VGA1 connected 1024x768+0+0 (normal left inverted right x axis y axis) 0mm x 0mm 1024x768 60.00* 800x600 60.32 56.25 848x480 60.00 640x480 59.94 VIRTUAL1 disconnected (normal left inverted right x axis y axis) -- To view, visit https://review.coreboot.org/19522 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: If00a7247df0c32b3d1f489fb92d86baaa8fdf8ba Gerrit-PatchSet: 8 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: rockchip: rk3399: enable DPLL SSC for DDR EMI test on bob
by build bot (Jenkins) (Code Review) 04 May '17

04 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19557 ) Change subject: rockchip: rk3399: enable DPLL SSC for DDR EMI test on bob ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/53167/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/8995/ : SUCCESS -- To view, visit https://review.coreboot.org/19557 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I75461d4235bcf55324e6664a1220754e770b4786 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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coreboot-gerrit May 2017