Bill XIE has posted comments on this change. ( https://review.coreboot.org/19522 )
Change subject: mb/gigabyte/ga-b75m-d3h: add libgfxinit support
......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/#/c/19522/1//COMMIT_MSG
Commit Message:
PS1, Line 9:
> Thanks, Linux falls back to default modes <= 1024x786, <= 61Hz
I have just managed to borrow a real monitor for computer with vga port to test, and confirm that the native video init on the vga port dos work.
--
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Gerrit-MessageType: comment
Gerrit-Change-Id: If00a7247df0c32b3d1f489fb92d86baaa8fdf8ba
Gerrit-PatchSet: 7
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Bill XIE <persmule(a)gmail.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Bill XIE <persmule(a)gmail.com>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-HasComments: Yes
Hello Arthur Heymans, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/19522
to look at the new patch set (#7).
Change subject: mb/gigabyte/ga-b75m-d3h: add libgfxinit support
......................................................................
mb/gigabyte/ga-b75m-d3h: add libgfxinit support
Currently native video init works on port HDMI1 (wired to the
on-board DVI-D socket) , HDMI3 (the on-board HDMI port), and the VGA
port, both text mode and fb mode.
Every ports works on GNU/Linux.
Tested against an IVB cpu (i7-3770T).
Change-Id: If00a7247df0c32b3d1f489fb92d86baaa8fdf8ba
Signed-off-by: Bill XIE <persmule(a)gmail.com>
---
M src/mainboard/gigabyte/ga-b75m-d3h/Kconfig
M src/mainboard/gigabyte/ga-b75m-d3h/Makefile.inc
A src/mainboard/gigabyte/ga-b75m-d3h/gma-mainboard.ads
3 files changed, 17 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/19522/7
--
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Gerrit-MessageType: newpatchset
Gerrit-Change-Id: If00a7247df0c32b3d1f489fb92d86baaa8fdf8ba
Gerrit-PatchSet: 7
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Bill XIE <persmule(a)gmail.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Bill XIE <persmule(a)gmail.com>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/19550 )
Change subject: mb/google/eve: Remove code to set keyboard backlight at boot
......................................................................
mb/google/eve: Remove code to set keyboard backlight at boot
Remove the code that was enabling the keyboard backlight at boot
since this is not desired behavior for this device.
BUG=b:35581264
TEST=build and boot on Eve and ensure keyboard backlight does
not turn on when booting but can still be enabled in the OS.
Change-Id: I7229cf962597c0de74dc005f7afb9408f7a66f42
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://review.coreboot.org/19550
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
M src/mainboard/google/eve/bootblock.c
1 file changed, 0 insertions(+), 10 deletions(-)
Approvals:
Aaron Durbin: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/mainboard/google/eve/bootblock.c b/src/mainboard/google/eve/bootblock.c
index 872825f..5e92bb0 100644
--- a/src/mainboard/google/eve/bootblock.c
+++ b/src/mainboard/google/eve/bootblock.c
@@ -14,13 +14,10 @@
* GNU General Public License for more details.
*/
-#include <arch/io.h>
#include <bootblock_common.h>
#include <ec/google/chromeec/ec.h>
#include <gpio.h>
#include <soc/gpio.h>
-#include <soc/iomap.h>
-#include <soc/pm.h>
#include "gpio.h"
static void early_config_gpio(void)
@@ -30,12 +27,5 @@
void bootblock_mainboard_init(void)
{
- uint32_t pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
- uint32_t pm1_sts = inl(ACPI_BASE_ADDRESS + PM1_STS);
-
- /* Turn on keyboard backlight to indicate we are booting */
- if (!((pm1_sts & WAK_STS) && (acpi_sleep_from_pm1(pm1_cnt) == ACPI_S3)))
- google_chromeec_kbbacklight(75);
-
early_config_gpio();
}
--
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Gerrit-MessageType: merged
Gerrit-Change-Id: I7229cf962597c0de74dc005f7afb9408f7a66f42
Gerrit-PatchSet: 2
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/19549 )
Change subject: mb/google/eve: Set SUSWARN# pin to native function
......................................................................
mb/google/eve: Set SUSWARN# pin to native function
Set GPP_A13/SUSWARN# pin mode to native function 1. This pin is tied
to SUSACK# in the schematic and and is intented to be used in Deep Sx
so it should not be configured for GPIO mode.
BUG=b:35581264
TEST=build and boot on Eve platform, test that Deep S3 and Deep S5
are still functional. (this change should have no visible effect)
Change-Id: Ie2dc24d095872ab93a5bfcbe5307c3b7a8e4dbcc
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://review.coreboot.org/19549
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
M src/mainboard/google/eve/gpio.h
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Aaron Durbin: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/src/mainboard/google/eve/gpio.h b/src/mainboard/google/eve/gpio.h
index 6da8244..ed0d712 100644
--- a/src/mainboard/google/eve/gpio.h
+++ b/src/mainboard/google/eve/gpio.h
@@ -58,7 +58,7 @@
/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10),
/* PME# */ PAD_CFG_NC(GPP_A11), /* TP67 */
/* BM_BUSY# */ PAD_CFG_NC(GPP_A12),
-/* SUSWARN# */ PAD_CFG_NC(GPP_A13),
+/* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
/* ESPI_RESET# */
/* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16),
--
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Gerrit-MessageType: merged
Gerrit-Change-Id: Ie2dc24d095872ab93a5bfcbe5307c3b7a8e4dbcc
Gerrit-PatchSet: 2
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Youness Alaoui has uploaded a new change for review. ( https://review.coreboot.org/19556 )
Change subject: pciexp_device: Prevent race condition with retrain link
......................................................................
pciexp_device: Prevent race condition with retrain link
The PCIe specification[1] describes a race condition that
can occur when using the Retrain Link bit in the Link
Control Register.
The race condition is avoided by checking the retrain link
bit in the link status register and waiting until it is
set to 0, before initiating a new link retraining.
[1] PCI Express Base Specification Revision 3.0
Page 633
Change-Id: I9d5840fb9a6e63838b5a4084d3bbe483f1d870ed
Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm>
---
M src/device/pciexp_device.c
1 file changed, 19 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/19556/1
diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c
index 0c36538..fb2a284 100644
--- a/src/device/pciexp_device.c
+++ b/src/device/pciexp_device.c
@@ -53,6 +53,25 @@
unsigned try = PCIE_TRAIN_RETRY;
u16 lnk;
+ /* Implementation note (page 633) in PCIe Specification 3.0 suggests
+ * polling the Link Training bit in the Link Status register until the
+ * value returned is 0 before setting the Retrain Link bit to 1.
+ * This is meant to avoid a race condition when using the
+ * Retrain Link mechanism.
+ */
+ while (try--) {
+ lnk = pci_read_config16(dev, cap + PCI_EXP_LNKSTA);
+ if (!(lnk & PCI_EXP_LNKSTA_LT)) {
+ try = PCIE_TRAIN_RETRY;
+ break;
+ }
+ udelay(100);
+ }
+ if (try != PCIE_TRAIN_RETRY) {
+ printk(BIOS_ERR, "%s: Link Retrain timeout\n", dev_path(dev));
+ return -1;
+ }
+
/* Start link retraining */
lnk = pci_read_config16(dev, cap + PCI_EXP_LNKCTL);
lnk |= PCI_EXP_LNKCTL_RL;
--
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Gerrit-MessageType: newchange
Gerrit-Change-Id: I9d5840fb9a6e63838b5a4084d3bbe483f1d870ed
Gerrit-PatchSet: 1
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Youness Alaoui <snifikino(a)gmail.com>