coreboot-gerrit May 2017

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Change in coreboot[master]: nb/intel/sandybridge/romstage: Use register name
by build bot (Jenkins) (Code Review) 03 May '17

03 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19544 ) Change subject: nb/intel/sandybridge/romstage: Use register name ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53137/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/8968/ : SUCCESS -- To view, visit https://review.coreboot.org/19544 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Iacfe609f6454e6d58c9733f425377464238ce4a9 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: sb/intel/bd82x6x/finalize: Use register name
by build bot (Jenkins) (Code Review) 03 May '17

03 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19545 ) Change subject: sb/intel/bd82x6x/finalize: Use register name ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53136/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/8967/ : SUCCESS -- To view, visit https://review.coreboot.org/19545 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I08fc8435f29ab87a0534946b0e0c43231919785d Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: sb/intel/bd82x6x/bootblock: Use register name
by build bot (Jenkins) (Code Review) 03 May '17

03 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19546 ) Change subject: sb/intel/bd82x6x/bootblock: Use register name ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53138/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/8969/ : SUCCESS -- To view, visit https://review.coreboot.org/19546 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Idc90f254d7713f96a6e8b0389e34d860f461d9d1 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: sb/intel/bd82x6x/finalize: Lock ETR3 CF9GR
by build bot (Jenkins) (Code Review) 03 May '17

03 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19543 ) Change subject: sb/intel/bd82x6x/finalize: Lock ETR3 CF9GR ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53135/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/8966/ : SUCCESS -- To view, visit https://review.coreboot.org/19543 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I2cb30267a6342db1f3b11715034219ffb18ca678 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: Documentation/Intel: Add vboot documentation
by build bot (Jenkins) (Code Review) 03 May '17

03 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19534 ) Change subject: Documentation/Intel: Add vboot documentation ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53134/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/8965/ : SUCCESS -- To view, visit https://review.coreboot.org/19534 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ie17b8443772f596de0c9d8afe6f4ec3ac4d4fef8 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: [UNTESTED]mb/lenovo/t400: Make dock LEDs behave like vendor ...
by Arthur Heymans (Code Review) 03 May '17

03 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19542 to look at the new patch set (#2). Change subject: [UNTESTED]mb/lenovo/t400: Make dock LEDs behave like vendor bios ...................................................................... [UNTESTED]mb/lenovo/t400: Make dock LEDs behave like vendor bios Fetched from vendor DSDT and same as smm T60 dock code. No idea if dock/undock events are correctly here, but it is certainly useful as a visual aid to see if those work. Change-Id: Ia3ff479dba687216c537bc810ec561dfc98d25b1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/t400/acpi/dock.asl 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/19542/2 -- To view, visit https://review.coreboot.org/19542 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ia3ff479dba687216c537bc810ec561dfc98d25b1 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: nb/intel/sandybridge/early_init: Use register name
by Patrick Rudolph (Code Review) 03 May '17

03 May '17

Patrick Rudolph has uploaded a new change for review. ( https://review.coreboot.org/19547 ) Change subject: nb/intel/sandybridge/early_init: Use register name ...................................................................... nb/intel/sandybridge/early_init: Use register name Use names instead of magic values. No functional change. Change-Id: I3774595ff0fd21e42dc407ca8a0cf3fd7788a66f Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/northbridge/intel/sandybridge/early_init.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/19547/1 diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 16ea29d..efe27b1 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -30,10 +30,10 @@ { /* Setting up Southbridge. In the northbridge code. */ printk(BIOS_DEBUG, "Setting up static southbridge registers..."); - pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); + pci_write_config32(PCH_LPC_DEV, RCBA, (uintptr_t)DEFAULT_RCBA | 1); - pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */ + pci_write_config32(PCH_LPC_DEV, PMBASE, DEFAULT_PMBASE | 1); + pci_write_config8(PCH_LPC_DEV, ACPI_CNTL, 0x80); /* Enable ACPI BAR */ printk(BIOS_DEBUG, " done.\n"); -- To view, visit https://review.coreboot.org/19547 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I3774595ff0fd21e42dc407ca8a0cf3fd7788a66f Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: sb/intel/bd82x6x/bootblock: Use register name
by Patrick Rudolph (Code Review) 03 May '17

03 May '17

Patrick Rudolph has uploaded a new change for review. ( https://review.coreboot.org/19546 ) Change subject: sb/intel/bd82x6x/bootblock: Use register name ...................................................................... sb/intel/bd82x6x/bootblock: Use register name Use defines instead of magic values. No functional change. Change-Id: Idc90f254d7713f96a6e8b0389e34d860f461d9d1 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/southbridge/intel/bd82x6x/bootblock.c 1 file changed, 4 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/19546/1 diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c index 103b6a8..8541903 100644 --- a/src/southbridge/intel/bd82x6x/bootblock.c +++ b/src/southbridge/intel/bd82x6x/bootblock.c @@ -34,19 +34,17 @@ static void enable_spi_prefetch(void) { u8 reg8; - pci_devfn_t dev; + pci_devfn_t dev = PCH_LPC_DEV; - dev = PCI_DEV(0, 0x1f, 0); - - reg8 = pci_read_config8(dev, 0xdc); + reg8 = pci_read_config8(dev, BIOS_CNTL); reg8 &= ~(3 << 2); reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ - pci_write_config8(dev, 0xdc, reg8); + pci_write_config8(dev, BIOS_CNTL, reg8); } static void enable_port80_on_lpc(void) { - pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + pci_devfn_t dev = PCH_LPC_DEV; /* Enable port 80 POST on LPC */ pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); -- To view, visit https://review.coreboot.org/19546 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Idc90f254d7713f96a6e8b0389e34d860f461d9d1 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: nb/intel/sandybridge/romstage: Use register name
by Patrick Rudolph (Code Review) 03 May '17

03 May '17

Patrick Rudolph has uploaded a new change for review. ( https://review.coreboot.org/19544 ) Change subject: nb/intel/sandybridge/romstage: Use register name ...................................................................... nb/intel/sandybridge/romstage: Use register name Use register name instead of hex value. No functional change. Change-Id: Iacfe609f6454e6d58c9733f425377464238ce4a9 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/northbridge/intel/sandybridge/romstage.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/19544/1 diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 738e285..8608d5a 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -38,9 +38,9 @@ u8 reg8; // reset rtc power status - reg8 = pci_read_config8(PCH_LPC_DEV, 0xa4); + reg8 = pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3); reg8 &= ~(1 << 2); - pci_write_config8(PCH_LPC_DEV, 0xa4, reg8); + pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, reg8); } /* Platform has no romstage entry point under mainboard directory, -- To view, visit https://review.coreboot.org/19544 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Iacfe609f6454e6d58c9733f425377464238ce4a9 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: sb/intel/bd82x6x/finalize: Use register name
by Patrick Rudolph (Code Review) 03 May '17

03 May '17

Patrick Rudolph has uploaded a new change for review. ( https://review.coreboot.org/19545 ) Change subject: sb/intel/bd82x6x/finalize: Use register name ...................................................................... sb/intel/bd82x6x/finalize: Use register name Use register name instead of hex values. No functional change. Change-Id: I08fc8435f29ab87a0534946b0e0c43231919785d Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/southbridge/intel/bd82x6x/finalize.c M src/southbridge/intel/bd82x6x/pch.h 2 files changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/19545/1 diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c index c9296fd..4e08fc6 100644 --- a/src/southbridge/intel/bd82x6x/finalize.c +++ b/src/southbridge/intel/bd82x6x/finalize.c @@ -60,10 +60,10 @@ RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7)); /* Global SMI Lock */ - pci_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4); + pci_or_config16(PCH_LPC_DEV, GEN_PMCON_1, 1 << 4); /* GEN_PMCON Lock */ - pci_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2)); + pci_or_config8(PCH_LPC_DEV, GEN_PMCON_LOCK, (1 << 1) | (1 << 2)); /* R/WO registers */ RCBA32(0x21a4) = RCBA32(0x21a4); diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 8b22fca..da1f901 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -140,6 +140,7 @@ #define GEN_PMCON_1 0xa0 #define GEN_PMCON_2 0xa2 #define GEN_PMCON_3 0xa4 +#define GEN_PMCON_LOCK 0xa6 #define ETR3 0xac #define ETR3_CWORWRE (1 << 18) #define ETR3_CF9GR (1 << 20) -- To view, visit https://review.coreboot.org/19545 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I08fc8435f29ab87a0534946b0e0c43231919785d Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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coreboot-gerrit May 2017