Caesar Wang has posted comments on this change. ( https://review.coreboot.org/19557 )
Change subject: rockchip/rk3399: enable DPLL SSC for DDR EMI test on bob
......................................................................
Patch Set 7:
(4 comments)
https://review.coreboot.org/#/c/19557/4/src/soc/rockchip/rk3399/clock.c
File src/soc/rockchip/rk3399/clock.c:
Line 349: * extern wave table).
> nit: Should you maybe do this as you're writing it here? You're only settin
Done
Line 360: * TODO find the root cause why is the delay needed, Otherwise sometime
> Okay. Please change the comment to reflect that you don't know why the dela
Done
Line 373: /* Use frac mode */
> Sorry, I don't understand what you mean. According to the TRM (PLL initiali
Okay, you are right here.
I will set 0 for DPLL_CON2. Sorry!
Line 373: /* Use frac mode */
> So we're enabling fractional mode here, but where are we setting the fracti
0x31f / (2 << 24) == 0.00024% of the intended rate (i.e. 22KHz)? =====> that's offset for frequency
I just confirm with the SSC owner, the best way is we set the 0 for DPLL_CON2.
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Gerrit-MessageType: comment
Gerrit-Change-Id: I75461d4235bcf55324e6664a1220754e770b4786
Gerrit-PatchSet: 7
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Caesar Wang <wxt(a)rock-chips.com>
Gerrit-Reviewer: Caesar Wang <wxt(a)rock-chips.com>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/18511
to look at the new patch set (#9).
Change subject: nb/x4x/nortbridge.c: Compute TSEG resource allocation dynamically
......................................................................
nb/x4x/nortbridge.c: Compute TSEG resource allocation dynamically
Computes TSEG size dynamically.
Changes the size of legacy hole to match other Intel northbirdges.
Refactor this a little by needing one less variable.
Change-Id: I0e6898c06a2bc1016eeaa3f002ff6c39657018ae
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/northbridge/intel/x4x/northbridge.c
1 file changed, 37 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/18511/9
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Gerrit-Change-Id: I0e6898c06a2bc1016eeaa3f002ff6c39657018ae
Gerrit-PatchSet: 9
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Hello build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/19607
to look at the new patch set (#4).
Change subject: nb/intel/x4x: Don't run NGI if IGD has not been assigned VGA cycles
......................................................................
nb/intel/x4x: Don't run NGI if IGD has not been assigned VGA cycles
The NGI writes to legacy VGA registers which should not happen when
VGA cycles are assigned to a different device.
TESTED on ga-g41m-es2l
Change-Id: I0a03e35c0d7f2532edd6cc5e62d1cf07dab57f60
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/northbridge/intel/x4x/gma.c
1 file changed, 11 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/19607/4
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Gerrit-Change-Id: I0a03e35c0d7f2532edd6cc5e62d1cf07dab57f60
Gerrit-PatchSet: 4
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nickey.yang(a)rock-chips.com has posted comments on this change. ( https://review.coreboot.org/19477 )
Change subject: rockchip/rk3399: Add MIPI driver
......................................................................
Patch Set 5:
(7 comments)
https://review.coreboot.org/#/c/19477/2/src/soc/rockchip/rk3399/mipi.c
File src/soc/rockchip/rk3399/mipi.c:
Line 406: {
> That doesn't require you to have this here, though. You can just put a
No verified on the 3288 platform with Mipi panel, so can we put it here first?
https://review.coreboot.org/#/c/19477/4/src/soc/rockchip/rk3399/mipi.c
File src/soc/rockchip/rk3399/mipi.c:
PS4, Line 182:
> target_bps should also be unsigned long, just in case. Also, I think it wou
Done
PS4, Line 183: target_bps
> 1500 * MHz
Done
PS4, Line 206: / n) <
> 5 * MHz and 40 * MHz
Done
PS4, Line 216: ak;
> This should also be lane_bps instead and all subsequent calculations with i
Done
Line 405: void rk_mipi_prepare(const struct edid *edid)
> Remove this and just do
Done
Line 436
> I feel like I must have asked this somewhere already... where do the 500ms
Done
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