Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#13).
Change subject: mainboard/pcengines/apu2: Add LPC TPM support
......................................................................
mainboard/pcengines/apu2: Add LPC TPM support
APU2 exposes a LPC header which can be used
in conjunction with a LPC TPM module.
Change-Id: If9312370a5071ffbeb6d83888c75fa69a0c27819
Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org>
---
M src/mainboard/pcengines/apu2/Kconfig
M src/mainboard/pcengines/apu2/devicetree.cb
M src/mainboard/pcengines/apu2/romstage.c
3 files changed, 10 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/18523/13
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Gerrit-MessageType: newpatchset
Gerrit-Change-Id: If9312370a5071ffbeb6d83888c75fa69a0c27819
Gerrit-PatchSet: 13
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>
Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Martin Roth has posted comments on this change. ( https://review.coreboot.org/18523 )
Change subject: mainboard/pcengines/apu2: Add LPC TPM support
......................................................................
Patch Set 12:
(1 comment)
https://review.coreboot.org/#/c/18523/12/src/mainboard/pcengines/apu2/romst…
File src/mainboard/pcengines/apu2/romstage.c:
PS12, Line 96:
: #if CONFIG_LPC_TPM
Avoid the preprocessor #if if possible. You should use:
if (IS_ENABLED(CONFIG_LPC_TPM))
But since you're selecting LPC_TPM, and it will always be on, you could even just skip the if if you wanted.
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Gerrit-MessageType: comment
Gerrit-Change-Id: If9312370a5071ffbeb6d83888c75fa69a0c27819
Gerrit-PatchSet: 12
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>
Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-HasComments: Yes
Hello Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/18993
to look at the new patch set (#12).
Change subject: mainboard: Add ASRock G41C-GS
......................................................................
mainboard: Add ASRock G41C-GS
Start-point is Gigabyte GA-G41M-ES2L.
This board features a G41 northbridge and an ICH7 southbridge. This
board has slots for both DDR2 and DDR3 (cannot run concurrently
though) but only DDR2 is implemented in coreboot. The SPI flash
resides in a DIP-8 socket.
Tested and working:
* DDR2 dual channel (PC2 5300 and PC2 6400, though raminit is picky
with assymetric dimm setups);
* 3,5" IDE;
* SATA;
* PCIe x16 (with some patches up for review);
* Uart, PS2 Keyboard;
* USB, ethernet, audio;
* Native graphic init;
* Fan control;
* Reboot, poweroff, S3 resume;
* Flashrom (vendor and coreboot).
Tested but fails:
* DDR3 (not implemented in coreboot).
Tests were run with SeaBIOS and Debian sid, using Linux 4.9.0.
Change-Id: I992ee07b742dfc59733ce0f3a9be202a530ec6cc
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
A src/mainboard/asrock/g41c-gs/Kconfig
A src/mainboard/asrock/g41c-gs/Kconfig.name
A src/mainboard/asrock/g41c-gs/Makefile.inc
A src/mainboard/asrock/g41c-gs/acpi/ec.asl
A src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl
A src/mainboard/asrock/g41c-gs/acpi/platform.asl
A src/mainboard/asrock/g41c-gs/acpi/superio.asl
A src/mainboard/asrock/g41c-gs/acpi/x4x_pci_irqs.asl
A src/mainboard/asrock/g41c-gs/acpi_tables.c
A src/mainboard/asrock/g41c-gs/board_info.txt
A src/mainboard/asrock/g41c-gs/cmos.default
A src/mainboard/asrock/g41c-gs/cmos.layout
A src/mainboard/asrock/g41c-gs/cstates.c
A src/mainboard/asrock/g41c-gs/devicetree.cb
A src/mainboard/asrock/g41c-gs/dsdt.asl
A src/mainboard/asrock/g41c-gs/gpio.c
A src/mainboard/asrock/g41c-gs/hda_verb.c
A src/mainboard/asrock/g41c-gs/romstage.c
18 files changed, 878 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/18993/12
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Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I992ee07b742dfc59733ce0f3a9be202a530ec6cc
Gerrit-PatchSet: 12
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/18993 )
Change subject: mainboard: Add ASRock G41C-GS
......................................................................
Patch Set 11:
(4 comments)
https://review.coreboot.org/#/c/18993/6/src/mainboard/asrock/g41c-gs/acpi/x…
File src/mainboard/asrock/g41c-gs/acpi/x4x_pci_irqs.asl:
PS6, Line 40: Package() { 0x001fffff, 0, 0, 0x12 },
: Package() { 0x001fffff, 1, 0, 0x13 },
: Package() { 0x001fffff, 2, 0, 0x11 },
: Package() { 0x001fffff, 3, 0, 0x10 },
> Ping.
I see, so by default both SATA and SMBUS share the same interrupt pin.
https://review.coreboot.org/#/c/18993/7/src/mainboard/asrock/g41c-gs/romsta…
File src/mainboard/asrock/g41c-gs/romstage.c:
Line 51:
> Ping.
from datasheet, D30IP sets PINs for "AC ‘97 Audio Pin (AAIP)" default Pin A and "AC ‘97 Modem Pin (AMIP)", default PIN B, with RO LPC not using pin set by lower bits. PCI bridge PIN (unused) is RO and in lower bits of D31IP.
I guess it could be left untoched...
https://review.coreboot.org/#/c/18993/10/src/mainboard/asrock/g41c-gs/romst…
File src/mainboard/asrock/g41c-gs/romstage.c:
Line 69: RCBA32(GCS) = 0x00700464;
> Please sanitize (if it's from a dump, some reserved bits set might
ok
Line 72: RCBA32(CG) = 0x00000001;
> Does the PCIe x1 slot work with this?
I'd have to test this. I should have a PCIe 16x to 1x riser soon (no pcie device with right form factor here...)
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Gerrit-MessageType: comment
Gerrit-Change-Id: I992ee07b742dfc59733ce0f3a9be202a530ec6cc
Gerrit-PatchSet: 11
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
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Gerrit-HasComments: Yes
Philippe Mathieu-Daudé has posted comments on this change. ( https://review.coreboot.org/19622 )
Change subject: src/include: remove the __ROMCC__ to enable snprintf
......................................................................
Patch Set 3: Code-Review+1
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Gerrit-MessageType: comment
Gerrit-Change-Id: I6966dc8ebc911b954bc5ea8981df093df226dd6c
Gerrit-PatchSet: 3
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Caesar Wang <wxt(a)rock-chips.com>
Gerrit-Reviewer: Caesar Wang <wxt(a)rock-chips.com>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
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