Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/19090 )
Change subject: nb/intel/gm45: Allow setting backlight pwm frequency from CBFS
......................................................................
Patch Set 2: Code-Review-1
Not yet tested if rebase was ok.
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Hello Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/19627
to look at the new patch set (#3).
Change subject: mb/gigabyte/ga-g41m-es2l: Don't disable PATA
......................................................................
mb/gigabyte/ga-g41m-es2l: Don't disable PATA
This board features a PATA port.
TESTED PATA drive works in SeaBIOS and OS.
Change-Id: I74dc72c22e6c4fed07f28ef7d88adde54656ae39
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/19627/3
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Kevin Keijzer has posted comments on this change. ( https://review.coreboot.org/19090 )
Change subject: nb/intel/gm45: Allow setting backlight pwm frequency from CBFS
......................................................................
Patch Set 2: Code-Review+1
I would personally prefer the cbfs override to be present, because it seems like the easiest way to test a PWM value reliably prior to reporting the correct, tested value to be added to the whitelist. It's also a decent way to add an "unsupported" display without having to re-compile a ROM, or to work around degraded panels or weird inverters.
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Hello Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/18993
to look at the new patch set (#11).
Change subject: mainboard: Add ASRock G41C-GS
......................................................................
mainboard: Add ASRock G41C-GS
Start-point is Gigabyte GA-G41M-ES2L.
This board features a G41 northbridge and an ICH7 southbridge. This
board has slots for both DDR2 and DDR3 (cannot run concurrently
though) but only DDR2 is implemented in coreboot. The SPI flash
resides in a DIP-8 socket.
Tested and working:
* DDR2 dual channel (PC2 5300 and PC2 6400, though raminit is picky
with assymetric dimm setups);
* 3,5" IDE;
* SATA;
* PCIe x16 (with some patches up for review);
* Uart, PS2 Keyboard;
* USB, ethernet, audio;
* Native graphic init;
* Fan control;
* Reboot, poweroff, S3 resume;
* Flashrom (vendor and coreboot).
Tested but fails:
* DDR3 (not implemented in coreboot).
Tests were run with SeaBIOS and Debian sid, using Linux 4.9.0.
Change-Id: I992ee07b742dfc59733ce0f3a9be202a530ec6cc
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
A src/mainboard/asrock/g41c-gs/Kconfig
A src/mainboard/asrock/g41c-gs/Kconfig.name
A src/mainboard/asrock/g41c-gs/Makefile.inc
A src/mainboard/asrock/g41c-gs/acpi/ec.asl
A src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl
A src/mainboard/asrock/g41c-gs/acpi/platform.asl
A src/mainboard/asrock/g41c-gs/acpi/superio.asl
A src/mainboard/asrock/g41c-gs/acpi/x4x_pci_irqs.asl
A src/mainboard/asrock/g41c-gs/acpi_tables.c
A src/mainboard/asrock/g41c-gs/board_info.txt
A src/mainboard/asrock/g41c-gs/cmos.default
A src/mainboard/asrock/g41c-gs/cmos.layout
A src/mainboard/asrock/g41c-gs/cstates.c
A src/mainboard/asrock/g41c-gs/devicetree.cb
A src/mainboard/asrock/g41c-gs/dsdt.asl
A src/mainboard/asrock/g41c-gs/gpio.c
A src/mainboard/asrock/g41c-gs/hda_verb.c
A src/mainboard/asrock/g41c-gs/romstage.c
18 files changed, 879 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/18993/11
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/19627
to look at the new patch set (#2).
Change subject: mb/gigabyte/ga-g41m-es2l: Don't disable PATA
......................................................................
mb/gigabyte/ga-g41m-es2l: Don't disable PATA
This board features a PATA port.
TESTED PATA drive working in SeaBIOS and OS.
Change-Id: I74dc72c22e6c4fed07f28ef7d88adde54656ae39
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/19627/2
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/19090 )
Change subject: nb/intel/gm45: Allow setting backlight pwm frequency from CBFS
......................................................................
Patch Set 2:
how do you feel about this one? It allows the user to finetune it without recompiling but on the other hand I feel it's over engineered a little with a general default, a devicetree default, per EDID override and now with cbfs override...
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/19090
to look at the new patch set (#2).
Change subject: nb/intel/gm45: Allow setting backlight pwm frequency from CBFS
......................................................................
nb/intel/gm45: Allow setting backlight pwm frequency from CBFS
This patch allows the user to override the default pwm backlight
frequency using a cbfsfile called "backlight_pwm".
This file can be added using:
"cbfstool coreboot.rom add-int -i $freq_value -n backlight_pwm"
TESTED on Thinkpad X200
Change-Id: I82e90e47ffc42b8d7062af87f6b174cd03445bb7
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/northbridge/intel/gm45/gma.c
1 file changed, 34 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/19090/2
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/19557 )
Change subject: rockchip/rk3399: enable DPLL SSC for DDR EMI test on bob
......................................................................
Patch Set 5:
(4 comments)
https://review.coreboot.org/#/c/19557/4/src/soc/rockchip/rk3399/clock.c
File src/soc/rockchip/rk3399/clock.c:
Line 349: * extern wave table).
nit: Should you maybe do this as you're writing it here? You're only setting SPREAD and DIVVAL at the end, after you've already enabled SSC. Wouldn't it be better to set them first?
Line 360: printk(BIOS_ERR,"%s: failed to get refdiv(%d)\n", __func__,
> From the actual test, we need 10us delay at least.
Okay. Please change the comment to reflect that you don't know why the delay is needed yet, then. Your comment reads like you knew what you're doing here when you don't.
PS4, Line 359: if (!(dpll_cfg->refdiv && dpll_cfg->refdiv <= 6)) {
: printk(BIOS_ERR,"%s: failed to get refdiv(%d)\n", __func__,
: dpll_cfg->refdiv);
> Can we change it with the below patch?
Sorry, not quite sure what you mean here? I think this should be an assert()... it's a condition that shouldn't happen with the current code and is only dependent on compile-time factors.
Line 373: write32(&cru_ptr->dpll_con[3],
> In other word, the SSC register just enable the decimal mode, do not set th
Sorry, I don't understand what you mean. According to the TRM (PLL initialization section, 3.6.2):
> If DSMPD = 0 (DSM is enabled, "fractional mode")
> FOUTVCO = FREF / REFDIV * (FBDIV + FRAC / 224)
We are setting DSMPD to 0 here, so we are enabling fractional mode, right? That means FRAC (DPLL_CON2[23:0]) becomes relevant to calculate the output frequency and we should ensure that it's initialized correctly.
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Gerrit-Change-Id: I75461d4235bcf55324e6664a1220754e770b4786
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