coreboot-gerrit May 2017

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Change in coreboot[master]: superio/nuvoton/common: Make SuperIO config functions extern...
by Arthur Heymans (Code Review) 09 May '17

09 May '17

Arthur Heymans has uploaded a new change for review. ( https://review.coreboot.org/19626 ) Change subject: superio/nuvoton/common: Make SuperIO config functions externally available ...................................................................... superio/nuvoton/common: Make SuperIO config functions externally available Change-Id: I05f768c67542770e65279a562c05225b84edca40 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/superio/nuvoton/common/early_serial.c M src/superio/nuvoton/common/nuvoton.h 2 files changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/19626/1 diff --git a/src/superio/nuvoton/common/early_serial.c b/src/superio/nuvoton/common/early_serial.c index d1958a0..e80bcf1 100644 --- a/src/superio/nuvoton/common/early_serial.c +++ b/src/superio/nuvoton/common/early_serial.c @@ -45,7 +45,7 @@ /* Enable configuration: pass entry key '0x87' into index port dev * two times. */ -static void pnp_enter_conf_state(pnp_devfn_t dev) +void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(NUVOTON_ENTRY_KEY, port); @@ -53,7 +53,7 @@ } /* Disable configuration: pass exit key '0xAA' into index port dev. */ -static void pnp_exit_conf_state(pnp_devfn_t dev) +void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(NUVOTON_EXIT_KEY, port); diff --git a/src/superio/nuvoton/common/nuvoton.h b/src/superio/nuvoton/common/nuvoton.h index 22f1127..7407f73 100644 --- a/src/superio/nuvoton/common/nuvoton.h +++ b/src/superio/nuvoton/common/nuvoton.h @@ -21,6 +21,8 @@ #include <arch/io.h> #include <stdint.h> +void pnp_enter_conf_state(pnp_devfn_t dev); +void pnp_exit_conf_state(pnp_devfn_t dev); void nuvoton_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_NUVOTON_COMMON_ROMSTAGE_H */ -- To view, visit https://review.coreboot.org/19626 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I05f768c67542770e65279a562c05225b84edca40 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: mainboard: Add ASRock G41C-GS
by Arthur Heymans (Code Review) 09 May '17

09 May '17

Hello Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/18993 to look at the new patch set (#9). Change subject: mainboard: Add ASRock G41C-GS ...................................................................... mainboard: Add ASRock G41C-GS Start-point is Gigabyte GA-G41M-ES2L. This board features a G41 northbridge and an ICH7 southbridge. This board has slots for both DDR2 and DDR3 (cannot run concurrently though) but only DDR2 is implemented in coreboot. The SPI flash resides in a DIP-8 socket. Tested and working: * DDR2 dual channel (PC2 5300 and PC2 6400, though raminit is picky with assymetric dimm setups); * 3,5" IDE; * SATA; * PCIe x16 (with some patches up for review); * Uart, PS2 Keyboard; * USB, ethernet, audio; * Native graphic init; * Fan control; * Reboot, poweroff, S3 resume; * Flashrom (vendor and coreboot). Tested but fails: * DDR3 (not implemented in coreboot). Tests were run with SeaBIOS and Debian sid, using Linux 4.9.0. Change-Id: I992ee07b742dfc59733ce0f3a9be202a530ec6cc Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A src/mainboard/asrock/g41c-gs/Kconfig A src/mainboard/asrock/g41c-gs/Kconfig.name A src/mainboard/asrock/g41c-gs/Makefile.inc A src/mainboard/asrock/g41c-gs/acpi/ec.asl A src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl A src/mainboard/asrock/g41c-gs/acpi/platform.asl A src/mainboard/asrock/g41c-gs/acpi/superio.asl A src/mainboard/asrock/g41c-gs/acpi/x4x_pci_irqs.asl A src/mainboard/asrock/g41c-gs/acpi_tables.c A src/mainboard/asrock/g41c-gs/board_info.txt A src/mainboard/asrock/g41c-gs/cmos.default A src/mainboard/asrock/g41c-gs/cmos.layout A src/mainboard/asrock/g41c-gs/cstates.c A src/mainboard/asrock/g41c-gs/devicetree.cb A src/mainboard/asrock/g41c-gs/dsdt.asl A src/mainboard/asrock/g41c-gs/gpio.c A src/mainboard/asrock/g41c-gs/hda_verb.c A src/mainboard/asrock/g41c-gs/romstage.c 18 files changed, 878 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/18993/9 -- To view, visit https://review.coreboot.org/18993 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I992ee07b742dfc59733ce0f3a9be202a530ec6cc Gerrit-PatchSet: 9 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mainboard: Add ASRock G41C-GS
by Arthur Heymans (Code Review) 09 May '17

09 May '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/18993 ) Change subject: mainboard: Add ASRock G41C-GS ...................................................................... Patch Set 8: > > Got myself this board and S3 resume works fine with latest > patchset. > > I fail to get serial output both in Linux and in coreboot so I > guess > > something is wrong with either my board or my usb2serial. > > There's a TODO about GPIOs on superio, you might want to check that > before expecting anything to work ;) I remember roda/rk9 which has > some GPIO controlled muxing on the UART lines... I always end up forgetting those... (it worked) -- To view, visit https://review.coreboot.org/18993 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I992ee07b742dfc59733ce0f3a9be202a530ec6cc Gerrit-PatchSet: 8 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: vexpress: add gfx init
by build bot (Jenkins) (Code Review) 09 May '17

09 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/13749 ) Change subject: vexpress: add gfx init ...................................................................... Patch Set 6: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/53456/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/9253/ : SUCCESS -- To view, visit https://review.coreboot.org/13749 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I0eff29b74d7df331dcbf2c25799eaae4911e54fc Gerrit-PatchSet: 6 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: qemu/vexpress-a9: Discover RAM size.
by build bot (Jenkins) (Code Review) 09 May '17

09 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/13754 ) Change subject: qemu/vexpress-a9: Discover RAM size. ...................................................................... Patch Set 4: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/53455/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/9252/ : SUCCESS -- To view, visit https://review.coreboot.org/13754 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ib411f0a068bd247a9e0cd0a59689a3896921483e Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: qemu/vexpress-a9: Discover RAM size.
by Vladimir Serbinenko (Code Review) 09 May '17

09 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/13754 to look at the new patch set (#5). Change subject: qemu/vexpress-a9: Discover RAM size. ...................................................................... qemu/vexpress-a9: Discover RAM size. Probe RAM to find its size instead of hardcoding 1024M. Also properly export it to memory map. Change-Id: Ib411f0a068bd247a9e0cd0a59689a3896921483e Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- M src/mainboard/emulation/qemu-armv7/Kconfig M src/mainboard/emulation/qemu-armv7/cbmem.c A src/mainboard/emulation/qemu-armv7/mainboard.c A src/mainboard/emulation/qemu-armv7/mainboard.h 4 files changed, 108 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/13754/5 -- To view, visit https://review.coreboot.org/13754 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ib411f0a068bd247a9e0cd0a59689a3896921483e Gerrit-PatchSet: 5 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in libhwbase[master]: ada/dynamic_mmio: Explicitly set SPARK_Mode => Off
by Patrick Georgi (Code Review) 09 May '17

09 May '17

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/19624 ) Change subject: ada/dynamic_mmio: Explicitly set SPARK_Mode => Off ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/19624 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I56a3fcadce59713fb03a089d192d2022bfb1d378 Gerrit-PatchSet: 2 Gerrit-Project: libhwbase Gerrit-Branch: master Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Adrian-Ken Rueegsegger <ken(a)codelabs.ch> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-HasComments: No

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Change in coreboot[master]: mainboard: Add ASRock G41C-GS
by build bot (Jenkins) (Code Review) 09 May '17

09 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18993 ) Change subject: mainboard: Add ASRock G41C-GS ...................................................................... Patch Set 8: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53454/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/9251/ : SUCCESS -- To view, visit https://review.coreboot.org/18993 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I992ee07b742dfc59733ce0f3a9be202a530ec6cc Gerrit-PatchSet: 8 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: mainboard: Add ASRock G41C-GS
by Arthur Heymans (Code Review) 09 May '17

09 May '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/18993 ) Change subject: mainboard: Add ASRock G41C-GS ...................................................................... Patch Set 8: Got myself this board and S3 resume works fine with latest patchset. I fail to get serial output both in Linux and in coreboot so I guess something is wrong with either my board or my usb2serial. -- To view, visit https://review.coreboot.org/18993 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I992ee07b742dfc59733ce0f3a9be202a530ec6cc Gerrit-PatchSet: 8 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: mainboard: Add ASRock G41C-GS
by Arthur Heymans (Code Review) 09 May '17

09 May '17

Hello Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/18993 to look at the new patch set (#8). Change subject: mainboard: Add ASRock G41C-GS ...................................................................... mainboard: Add ASRock G41C-GS Start-point is Gigabyte GA-G41M-ES2L. This board features a G41 northbridge and an ICH7 southbridge. This board has slots for both DDR2 and DDR3 (cannot run concurrently though) but only DDR2 is implemented in coreboot. The SPI flash resides in a DIP-8 socket. Tested and working: * DDR2 dual channel (PC2 5300 and PC2 6400, though raminit is picky with assymetric dimm setups); * 3,5" IDE; * SATA; * PCIe x16 (with some patches up for review); * Uart, PS2 Keyboard; * USB, ethernet, audio; * Native graphic init; * Fan control; * Reboot, poweroff, S3 resume; * Flashrom (vendor and coreboot). Tested but fails: * DDR3 (not implemented in coreboot). Tests were run with SeaBIOS and Debian sid, using Linux 4.9.0. Change-Id: I992ee07b742dfc59733ce0f3a9be202a530ec6cc Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A src/mainboard/asrock/g41c-gs/Kconfig A src/mainboard/asrock/g41c-gs/Kconfig.name A src/mainboard/asrock/g41c-gs/Makefile.inc A src/mainboard/asrock/g41c-gs/acpi/ec.asl A src/mainboard/asrock/g41c-gs/acpi/ich7_pci_irqs.asl A src/mainboard/asrock/g41c-gs/acpi/platform.asl A src/mainboard/asrock/g41c-gs/acpi/superio.asl A src/mainboard/asrock/g41c-gs/acpi/x4x_pci_irqs.asl A src/mainboard/asrock/g41c-gs/acpi_tables.c A src/mainboard/asrock/g41c-gs/board_info.txt A src/mainboard/asrock/g41c-gs/cmos.default A src/mainboard/asrock/g41c-gs/cmos.layout A src/mainboard/asrock/g41c-gs/cstates.c A src/mainboard/asrock/g41c-gs/devicetree.cb A src/mainboard/asrock/g41c-gs/dsdt.asl A src/mainboard/asrock/g41c-gs/gpio.c A src/mainboard/asrock/g41c-gs/hda_verb.c A src/mainboard/asrock/g41c-gs/romstage.c 18 files changed, 869 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/18993/8 -- To view, visit https://review.coreboot.org/18993 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I992ee07b742dfc59733ce0f3a9be202a530ec6cc Gerrit-PatchSet: 8 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit May 2017