coreboot-gerrit May 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: rockchip/rk3399: Add MIPI driver
by Anonymous Coward (Code Review) 09 May '17

09 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19477 to look at the new patch set (#5). Change subject: rockchip/rk3399: Add MIPI driver ...................................................................... rockchip/rk3399: Add MIPI driver This patch configures clock for mipi and then adds mipi driver for support innolux-p079zca mipi panel in rk3399 scarlet. Change-Id: I02475eefb187c619c614b1cd20e97074bc8d917f Signed-off-by: Nickey Yang <nickey.yang(a)rock-chips.com> --- M src/soc/rockchip/common/include/soc/vop.h M src/soc/rockchip/common/vop.c M src/soc/rockchip/rk3399/Makefile.inc M src/soc/rockchip/rk3399/chip.h M src/soc/rockchip/rk3399/clock.c M src/soc/rockchip/rk3399/display.c M src/soc/rockchip/rk3399/include/soc/addressmap.h M src/soc/rockchip/rk3399/include/soc/clock.h A src/soc/rockchip/rk3399/include/soc/mipi.h A src/soc/rockchip/rk3399/mipi.c 10 files changed, 797 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/19477/5 -- To view, visit https://review.coreboot.org/19477 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I02475eefb187c619c614b1cd20e97074bc8d917f Gerrit-PatchSet: 5 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: nickey.yang(a)rock-chips.com Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sean Paul <seanpaul(a)chromium.org> Gerrit-Reviewer: Shunqian Zheng <zhengsq(a)rock-chips.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nickey.yang(a)rock-chips.com

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Change in coreboot[master]: mainboard/google/poppy/variants/soraka: Enable H1 I2C TPM
by Furquan Shaikh (Code Review) 09 May '17

09 May '17

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/19519 ) Change subject: mainboard/google/poppy/variants/soraka: Enable H1 I2C TPM ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/19519/3//COMMIT_MSG Commit Message: Line 8: > Tested how? Haven't verified it yet. Hence the -2 for code review. -- To view, visit https://review.coreboot.org/19519 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Id9947dce9b7f755971f0199f043af8d251d275ab Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: mainboard/google/poppy/variants/soraka: Enable H1 I2C TPM
by build bot (Jenkins) (Code Review) 09 May '17

09 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19519 ) Change subject: mainboard/google/poppy/variants/soraka: Enable H1 I2C TPM ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53480/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/9275/ : SUCCESS -- To view, visit https://review.coreboot.org/19519 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Id9947dce9b7f755971f0199f043af8d251d275ab Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/google/poppy/variants/soraka: Enable H1 I2C TPM
by Furquan Shaikh (Code Review) 09 May '17

09 May '17

Hello Aaron Durbin, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19519 to look at the new patch set (#4). Change subject: mainboard/google/poppy/variants/soraka: Enable H1 I2C TPM ...................................................................... mainboard/google/poppy/variants/soraka: Enable H1 I2C TPM 1. Add a separate devicetree file for soraka variant and add H1 node. 2. Correct I2C bus # for H1 TPM. 3. Enable H1 TPM for soraka. BUG=b:36265511 Change-Id: Id9947dce9b7f755971f0199f043af8d251d275ab Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/mainboard/google/poppy/Kconfig A src/mainboard/google/poppy/variants/soraka/devicetree.cb 2 files changed, 435 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/19519/4 -- To view, visit https://review.coreboot.org/19519 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: Id9947dce9b7f755971f0199f043af8d251d275ab Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: rockchip/rk3399: enable DPLL SSC for DDR EMI test on bob
by build bot (Jenkins) (Code Review) 09 May '17

09 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19557 ) Change subject: rockchip/rk3399: enable DPLL SSC for DDR EMI test on bob ...................................................................... Patch Set 7: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53479/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/9274/ : SUCCESS -- To view, visit https://review.coreboot.org/19557 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I75461d4235bcf55324e6664a1220754e770b4786 Gerrit-PatchSet: 7 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: google/gru: support 800M/928M frequency for bob
by build bot (Jenkins) (Code Review) 09 May '17

09 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19558 ) Change subject: google/gru: support 800M/928M frequency for bob ...................................................................... Patch Set 7: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53478/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/9273/ : SUCCESS -- To view, visit https://review.coreboot.org/19558 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I613050292a09ff56f4636d7af285075e32259ef4 Gerrit-PatchSet: 7 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: src/include: remove the __ROMCC__ to enable snprintf
by build bot (Jenkins) (Code Review) 09 May '17

09 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19622 ) Change subject: src/include: remove the __ROMCC__ to enable snprintf ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53477/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/9272/ : SUCCESS -- To view, visit https://review.coreboot.org/19622 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I6966dc8ebc911b954bc5ea8981df093df226dd6c Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: google/gru: support 800M/928M frequency for bob
by Caesar Wang (Code Review) 09 May '17

09 May '17

Caesar Wang has posted comments on this change. ( https://review.coreboot.org/19558 ) Change subject: google/gru: support 800M/928M frequency for bob ...................................................................... Patch Set 7: (2 comments) https://review.coreboot.org/#/c/19558/6/src/mainboard/google/gru/sdram_conf… File src/mainboard/google/gru/sdram_configs.c: Line 39: > ...and still you have two tables? The whole point of using snprintf was tha Done Line 53: ramcode = ram_code(); > nit: would be better to factor out into a separate function, I think (i.e. Done -- To view, visit https://review.coreboot.org/19558 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I613050292a09ff56f4636d7af285075e32259ef4 Gerrit-PatchSet: 7 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: google/gru: support 800M/928M frequency for bob
by Caesar Wang (Code Review) 09 May '17

09 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19558 to look at the new patch set (#7). Change subject: google/gru: support 800M/928M frequency for bob ...................................................................... google/gru: support 800M/928M frequency for bob The coreboot had no supported the different frequency for gru yet. e.g: we can't support the bob to run ddr 800M for rev3 board and run 928M for rev4 board. So, in order to support the 800M and 928M ddr frequency for bob different boards. We will use the ram_id and board_id to select the board on bob. Change-Id: I613050292a09ff56f4636d7af285075e32259ef4 Signed-off-by: Caesar Wang <wxt(a)rock-chips.com> --- M src/mainboard/google/gru/Kconfig M src/mainboard/google/gru/Makefile.inc M src/mainboard/google/gru/sdram_configs.c R src/mainboard/google/gru/sdram_params/Makefile.inc R src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-928.c R src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-2GB-800.c R src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-2GB-928.c R src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-4GB-800.c R src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-4GB-928.c R src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-2GB-24EB-800.c R src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-2GB-24EB-928.c R src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-4GB-04EB-800.c R src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-4GB-04EB-928.c D src/mainboard/google/gru/sdram_params_933/Makefile.inc 14 files changed, 35 insertions(+), 48 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/19558/7 -- To view, visit https://review.coreboot.org/19558 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I613050292a09ff56f4636d7af285075e32259ef4 Gerrit-PatchSet: 7 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: drivers/i2c: Add new driver for RTC type RX6110 SA
by Werner Zeh (Code Review) 09 May '17

09 May '17

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/19625 ) Change subject: drivers/i2c: Add new driver for RTC type RX6110 SA ...................................................................... Patch Set 1: (11 comments) https://review.coreboot.org/#/c/19625/1/src/drivers/i2c/rx6110sa/chip.h File src/drivers/i2c/rx6110sa/chip.h: PS1, Line 19: unsigned char user_weekday; /* User day of the week to set */ Can you please add in the comment, that the weekday has to have the value 0..6 as the weekday register in the RTC is encoded in single set bits. https://review.coreboot.org/#/c/19625/1/src/drivers/i2c/rx6110sa/rx6110sa.c File src/drivers/i2c/rx6110sa/rx6110sa.c: PS1, Line 16: #include <device/smbus.h> The whole driver references I2C transfaers. Do we need smbus.h here at all? PS1, Line 18: #include <soc/i2c.h> You don't have to use soc/i2c.h as your driver completely relies on device/i2c.h. Or did I missed something? PS1, Line 81: error status "power loss event"? PS1, Line 85: detect detected, PS1, Line 88: detect detected, PS1, Line 95: F lower case PS1, Line 95: Timer Enable Bit In the other comments you have used lower case for bit descriptions. Want to sync that? PS1, Line 122: clock Maybe better call it "RTC" here as the complete RTC is initialized now? PS1, Line 123: i2c_readb(I2C_BUS_NUM, I2C_DEV_NUM, CTRL_REG, &reg); : reg &= ~STOP_BIT; : i2c_writeb(I2C_BUS_NUM, I2C_DEV_NUM, CTRL_REG, reg); In Line 107 you have written STOP_BIT to control register. With that write access the only set bit in that register is bit 6. To start the RTC now you don't have to read the control register back again as the value is known. Just write 0x0 to it. Or did I missed something? https://review.coreboot.org/#/c/19625/1/src/drivers/i2c/rx6110sa/rx6110sa.h File src/drivers/i2c/rx6110sa/rx6110sa.h: PS1, Line 54: V lower case -- To view, visit https://review.coreboot.org/19625 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I1290a10c2d5ad76a317c99c8b92a013309a605d6 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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coreboot-gerrit May 2017