coreboot-gerrit May 2017

coreboot-gerrit@coreboot.org

1 participants
3888 discussions

Change in coreboot[master]: soc/intel/skylake: Use common/blocks/uart code
by build bot (Jenkins) (Code Review) 10 May '17

10 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19492 ) Change subject: soc/intel/skylake: Use common/blocks/uart code ...................................................................... Patch Set 7: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53496/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/9291/ : SUCCESS -- To view, visit https://review.coreboot.org/19492 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I53ed687dc49524e001889f091825b2cc530546a3 Gerrit-PatchSet: 7 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/skylake: Use intel/common/block/smbus code
by Martin Roth (Code Review) 10 May '17

10 May '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19373 ) Change subject: soc/intel/skylake: Use intel/common/block/smbus code ...................................................................... soc/intel/skylake: Use intel/common/block/smbus code Change-Id: I2ca32ab594552424e4f1358302641f159a3d7e62 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> Reviewed-on: https://review.coreboot.org/19373 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/Makefile.inc M src/soc/intel/skylake/bootblock/pch.c D src/soc/intel/skylake/bootblock/smbus.c D src/soc/intel/skylake/early_smbus.c M src/soc/intel/skylake/include/soc/bootblock.h M src/soc/intel/skylake/include/soc/pm.h M src/soc/intel/skylake/include/soc/smbus.h D src/soc/intel/skylake/smbus.c D src/soc/intel/skylake/smbus_common.c 10 files changed, 8 insertions(+), 369 deletions(-) Approvals: Aaron Durbin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index fba6f7f..475c883 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -58,6 +58,7 @@ select SOC_INTEL_COMMON_BLOCK_PCR select SOC_INTEL_COMMON_BLOCK_RTC select SOC_INTEL_COMMON_BLOCK_SA + select SOC_INTEL_COMMON_BLOCK_SMBUS select SOC_INTEL_COMMON_BLOCK_UART select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_LPSS_I2C diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 1d8fe16..d25332c 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -14,7 +14,6 @@ bootblock-y += bootblock/i2c.c bootblock-y += bootblock/pch.c bootblock-y += bootblock/report_platform.c -bootblock-y += bootblock/smbus.c bootblock-$(CONFIG_UART_DEBUG) += bootblock/uart.c bootblock-$(CONFIG_UART_DEBUG) += uart_debug.c bootblock-y += gpio.c @@ -44,8 +43,6 @@ romstage-y += pei_data.c romstage-y += pmutil.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c -romstage-y += smbus_common.c -romstage-y += early_smbus.c romstage-y += spi.c romstage-y += tsc_freq.c romstage-$(CONFIG_UART_DEBUG) += uart_debug.c @@ -77,8 +74,6 @@ ramstage-y += sata.c ramstage-y += sd.c ramstage-y += sgx.c -ramstage-y += smbus.c -ramstage-y += smbus_common.c ramstage-y += smi.c ramstage-y += smmrelocate.c ramstage-y += spi.c diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index a92e4cf..780c4aa 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -22,6 +22,7 @@ #include <intelblocks/itss.h> #include <intelblocks/pcr.h> #include <intelblocks/rtc.h> +#include <intelblocks/smbus.h> #include <soc/bootblock.h> #include <soc/iomap.h> #include <soc/lpc.h> @@ -182,14 +183,14 @@ /* Disable TCO in SMBUS Device first before changing Base Address */ reg32 = pci_read_config32(PCH_DEV_SMBUS, TCOCTL); - reg32 &= ~SMBUS_TCO_EN; + reg32 &= ~TCO_EN; pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32); /* Program TCO Base */ pci_write_config32(PCH_DEV_SMBUS, TCOBASE, TCO_BASE_ADDDRESS); /* Enable TCO in SMBUS */ - pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32 | SMBUS_TCO_EN); + pci_write_config32(PCH_DEV_SMBUS, TCOCTL, reg32 | TCO_EN); /* * Program "TCO Base Address" PCR[DMI] + 2778h[15:5, 1] @@ -269,7 +270,7 @@ pch_enable_lpc(); /* Program SMBUS_BASE_ADDRESS and Enable it */ - enable_smbus(); + smbus_common_init(); /* Set up GPE configuration */ pmc_gpe_init(); diff --git a/src/soc/intel/skylake/bootblock/smbus.c b/src/soc/intel/skylake/bootblock/smbus.c deleted file mode 100644 index 14a9666..0000000 --- a/src/soc/intel/skylake/bootblock/smbus.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <device/pci_ids.h> -#include <device/pci_def.h> -#include <reg_script.h> -#include <soc/bootblock.h> -#include <soc/iomap.h> -#include <soc/pci_devs.h> -#include <soc/smbus.h> - -static const struct reg_script smbus_init_script[] = { - /* Set SMBUS I/O base address */ - REG_PCI_WRITE32(SMB_BASE, SMBUS_BASE_ADDRESS | 1), - /* Set SMBUS enable */ - REG_PCI_WRITE8(HOSTC, HST_EN), - /* Enable I/O access */ - REG_PCI_WRITE16(PCI_COMMAND, PCI_COMMAND_IO), - /* Disable interrupts */ - REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTCTL, 0), - /* Clear errors */ - REG_IO_WRITE8(SMBUS_BASE_ADDRESS + SMBHSTSTAT, 0xff), - /* Indicate the end of this array by REG_SCRIPT_END */ - REG_SCRIPT_END, -}; - -void enable_smbus(void) -{ - reg_script_run_on_dev(PCH_DEV_SMBUS, smbus_init_script); -} diff --git a/src/soc/intel/skylake/early_smbus.c b/src/soc/intel/skylake/early_smbus.c deleted file mode 100644 index 6df971a..0000000 --- a/src/soc/intel/skylake/early_smbus.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <device/smbus_def.h> -#include <device/early_smbus.h> -#include <soc/smbus.h> -#include <soc/iomap.h> - -u8 smbus_read_byte(u32 smbus_dev, u8 addr, u8 offset) -{ - return do_smbus_read_byte(SMBUS_BASE_ADDRESS, addr, offset); -} - -u8 smbus_write_byte(u32 smbus_dev, u8 addr, u8 offset, u8 value) -{ - return do_smbus_write_byte(SMBUS_BASE_ADDRESS, addr, offset, value); -} diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h index f290d0f..10c8de1 100644 --- a/src/soc/intel/skylake/include/soc/bootblock.h +++ b/src/soc/intel/skylake/include/soc/bootblock.h @@ -30,7 +30,6 @@ void pch_uart_init(void); /* Bootblock post console init programing */ -void enable_smbus(void); void i2c_early_init(void); void pch_early_init(void); void pch_early_iorange_init(void); diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 7112c77..15c291c 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -51,7 +51,7 @@ #define INTEL_USB2_EN (1 << 18) #define LEGACY_USB2_EN (1 << 17) #define PERIODIC_EN (1 << 14) -#define TCO_EN (1 << 13) +#define TCO_SMI_EN (1 << 13) #define MCSMI_EN (1 << 11) #define BIOS_RLS (1 << 7) #define SWSMI_TMR_EN (1 << 6) diff --git a/src/soc/intel/skylake/include/soc/smbus.h b/src/soc/intel/skylake/include/soc/smbus.h index 1e4d59b..ad5ae26 100644 --- a/src/soc/intel/skylake/include/soc/smbus.h +++ b/src/soc/intel/skylake/include/soc/smbus.h @@ -20,14 +20,12 @@ #define _SOC_SMBUS_H_ /* PCI Configuration Space (D31:F3): SMBus */ -#define SMB_BASE 0x20 -#define HOSTC 0x40 -#define HST_EN (1 << 0) #define SMB_RCV_SLVA 0x09 + /* SMBUS TCO base address. */ #define TCOBASE 0x50 #define TCOCTL 0x54 -#define SMBUS_TCO_EN (1 << 8) +#define TCO_EN (1 << 8) /* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ #define TCO1_STS 0x04 @@ -39,24 +37,6 @@ #define TCO_TMR_HLT (1 << 11) /* SMBus I/O bits. */ -#define SMBHSTSTAT 0x0 -#define SMBHSTCTL 0x2 -#define SMBHSTCMD 0x3 -#define SMBXMITADD 0x4 -#define SMBHSTDAT0 0x5 -#define SMBHSTDAT1 0x6 -#define SMBBLKDAT 0x7 -#define SMBTRNSADD 0x9 -#define SMBSLVDATA 0xa -#define SMLINK_PIN_CTL 0xe -#define SMBUS_PIN_CTL 0xf - -#define SMBUS_TIMEOUT (10 * 1000 * 100) #define SMBUS_SLAVE_ADDR 0x24 - -int do_smbus_read_byte(unsigned int smbus_base, unsigned int device, - unsigned int address); -int do_smbus_write_byte(unsigned int smbus_base, unsigned int device, - unsigned int address, unsigned int data); #endif diff --git a/src/soc/intel/skylake/smbus.c b/src/soc/intel/skylake/smbus.c deleted file mode 100644 index dc6c435..0000000 --- a/src/soc/intel/skylake/smbus.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <device/device.h> -#include <device/path.h> -#include <device/smbus.h> -#include <device/smbus_def.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <soc/iomap.h> -#include <soc/ramstage.h> -#include <soc/smbus.h> - -static void pch_smbus_init(device_t dev) -{ - struct resource *res; - u16 reg16; - - /* Enable clock gating */ - reg16 = pci_read_config32(dev, 0x80); - reg16 &= ~((1 << 8)|(1 << 10)|(1 << 12)|(1 << 14)); - pci_write_config32(dev, 0x80, reg16); - - /* Set Receive Slave Address */ - res = find_resource(dev, PCI_BASE_ADDRESS_4); - if (res) - outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA); -} - -static int lsmbus_read_byte(device_t dev, u8 address) -{ - u16 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); - - return do_smbus_read_byte(res->base, device, address); -} - -static int lsmbus_write_byte(device_t dev, u8 address, u8 data) -{ - u16 device; - struct resource *res; - struct bus *pbus; - - device = dev->path.i2c.device; - pbus = get_pbus_smbus(dev); - res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4); - return do_smbus_write_byte(res->base, device, address, data); -} - -static struct smbus_bus_operations lops_smbus_bus = { - .read_byte = lsmbus_read_byte, - .write_byte = lsmbus_write_byte, -}; - -static void smbus_read_resources(device_t dev) -{ - struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4); - res->base = SMBUS_BASE_ADDRESS; - res->size = 32; - res->limit = res->base + res->size - 1; - res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | - IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - /* Also add MMIO resource */ - res = pci_get_resource(dev, PCI_BASE_ADDRESS_0); -} - -static struct device_operations smbus_ops = { - .read_resources = &smbus_read_resources, - .set_resources = &pci_dev_set_resources, - .enable_resources = &pci_dev_enable_resources, - .scan_bus = &scan_smbus, - .init = &pch_smbus_init, - .ops_smbus_bus = &lops_smbus_bus, - .ops_pci = &soc_pci_ops, -}; - -static const unsigned short pci_device_ids[] = { - 0x9d23, /* SunRisePoint LP */ - 0xa123, /* SunRisePoint H */ - 0 -}; - -static const struct pci_driver pch_smbus __pci_driver = { - .ops = &smbus_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, -}; diff --git a/src/soc/intel/skylake/smbus_common.c b/src/soc/intel/skylake/smbus_common.c deleted file mode 100644 index 63a4f8a..0000000 --- a/src/soc/intel/skylake/smbus_common.c +++ /dev/null @@ -1,151 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2005 Yinghai Lu <yinghailu(a)gmail.com> - * Copyright (C) 2008-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <device/device.h> -#include <device/path.h> -#include <device/smbus_def.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <soc/ramstage.h> -#include <soc/smbus.h> - -static void smbus_delay(void) -{ - inb(0x80); -} - -static int smbus_wait_until_ready(u16 smbus_base) -{ - unsigned int loops = SMBUS_TIMEOUT; - unsigned char byte; - do { - smbus_delay(); - if (--loops == 0) - break; - byte = inb(smbus_base + SMBHSTSTAT); - } while (byte & 1); - return loops ? 0 : -1; -} - -static int smbus_wait_until_done(u16 smbus_base) -{ - unsigned int loops = SMBUS_TIMEOUT; - unsigned char byte; - do { - smbus_delay(); - if (--loops == 0) - break; - byte = inb(smbus_base + SMBHSTSTAT); - } while ((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0); - return loops ? 0 : -1; -} - -int do_smbus_read_byte(unsigned int smbus_base, unsigned int device, - unsigned int address) -{ - unsigned char global_status_register; - unsigned char byte; - - if (smbus_wait_until_ready(smbus_base) < 0) - return SMBUS_WAIT_UNTIL_READY_TIMEOUT; - - /* Setup transaction */ - /* Disable interrupts */ - outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL); - /* Set the device I'm talking too */ - outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD); - /* Set the command/address... */ - outb(address & 0xff, smbus_base + SMBHSTCMD); - /* Set up for a byte data read */ - outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2), - (smbus_base + SMBHSTCTL)); - /* Clear any lingering errors, so the transaction will run */ - outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT); - - /* Clear the data byte... */ - outb(0, smbus_base + SMBHSTDAT0); - - /* Start the command */ - outb((inb(smbus_base + SMBHSTCTL) | 0x40), - smbus_base + SMBHSTCTL); - - /* Poll for transaction completion */ - if (smbus_wait_until_done(smbus_base) < 0) - return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; - - global_status_register = inb(smbus_base + SMBHSTSTAT); - - /* Ignore the "In Use" status... */ - global_status_register &= ~(3 << 5); - - /* Read results of transaction */ - byte = inb(smbus_base + SMBHSTDAT0); - if (global_status_register != (1 << 1)) - return SMBUS_ERROR; - return byte; -} - -int do_smbus_write_byte(unsigned int smbus_base, unsigned int device, - unsigned int address, unsigned int data) -{ - unsigned char global_status_register; - - if (smbus_wait_until_ready(smbus_base) < 0) - return SMBUS_WAIT_UNTIL_READY_TIMEOUT; - - /* Setup transaction */ - /* Disable interrupts */ - outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL); - /* Set the device I'm talking too */ - outb(((device & 0x7f) << 1) & ~0x01, smbus_base + SMBXMITADD); - /* Set the command/address... */ - outb(address & 0xff, smbus_base + SMBHSTCMD); - /* Set up for a byte data read */ - outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2), - (smbus_base + SMBHSTCTL)); - /* Clear any lingering errors, so the transaction will run */ - outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT); - - /* Clear the data byte... */ - outb(data, smbus_base + SMBHSTDAT0); - - /* Start the command */ - outb((inb(smbus_base + SMBHSTCTL) | 0x40), - smbus_base + SMBHSTCTL); - - /* Poll for transaction completion */ - if (smbus_wait_until_done(smbus_base) < 0) { - printk(BIOS_ERR, "SMBUS transaction timeout\n"); - return SMBUS_WAIT_UNTIL_DONE_TIMEOUT; - } - - global_status_register = inb(smbus_base + SMBHSTSTAT); - - /* Ignore the "In Use" status... */ - global_status_register &= ~(3 << 5); - - /* Read results of transaction */ - if (global_status_register != (1 << 1)) { - printk(BIOS_ERR, "SMBUS transaction error\n"); - return SMBUS_ERROR; - } - - return 0; -} -- To view, visit https://review.coreboot.org/19373 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I2ca32ab594552424e4f1358302641f159a3d7e62 Gerrit-PatchSet: 14 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: soc/intel/skylake: Use intel/common/block/smbus code
by build bot (Jenkins) (Code Review) 10 May '17

10 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19373 ) Change subject: soc/intel/skylake: Use intel/common/block/smbus code ...................................................................... Patch Set 13: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53493/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/9288/ : SUCCESS -- To view, visit https://review.coreboot.org/19373 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I2ca32ab594552424e4f1358302641f159a3d7e62 Gerrit-PatchSet: 13 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

1 0

Change in coreboot[master]: google/sand: Add keyboard backlight support
by Martin Roth (Code Review) 10 May '17

10 May '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19479 ) Change subject: google/sand: Add keyboard backlight support ...................................................................... google/sand: Add keyboard backlight support BUG=None TEST=emerge-sand coreboot chromeos-bootimage and verify the keyboard backlight can be bright and alt+f6, alt+f7 function keys can be used. Change-Id: I86a35551a9348ff6ad26dfccd3b2786282d56069 Signed-off-by: Katherine Hsieh <Katherine.Hsieh(a)quantatw.com> Reviewed-on: https://review.coreboot.org/19479 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- M src/mainboard/google/reef/variants/sand/include/variant/ec.h 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: Aaron Durbin: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/mainboard/google/reef/variants/sand/include/variant/ec.h b/src/mainboard/google/reef/variants/sand/include/variant/ec.h index 80cf806..e4377c8 100644 --- a/src/mainboard/google/reef/variants/sand/include/variant/ec.h +++ b/src/mainboard/google/reef/variants/sand/include/variant/ec.h @@ -62,6 +62,9 @@ /* Enable EC backed ALS device in ACPI */ #define EC_ENABLE_ALS_DEVICE +/* Enable EC backed Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT + /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE -- To view, visit https://review.coreboot.org/19479 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I86a35551a9348ff6ad26dfccd3b2786282d56069 Gerrit-PatchSet: 5 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Katherine Hsieh <Katherine.Hsieh(a)quantatw.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: soc/intel/skylake/chip.h: Reorder declarations
by build bot (Jenkins) (Code Review) 10 May '17

10 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19637 ) Change subject: soc/intel/skylake/chip.h: Reorder declarations ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53490/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/9285/ : SUCCESS -- To view, visit https://review.coreboot.org/19637 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Idff2b628d19ce1a80294b28c55c05ba4157d07e0 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/skylake/chip.h: Provide some enums
by build bot (Jenkins) (Code Review) 10 May '17

10 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19636 ) Change subject: soc/intel/skylake/chip.h: Provide some enums ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53491/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/9286/ : SUCCESS -- To view, visit https://review.coreboot.org/19636 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Iff551565647f28ecb226e1df633b4deec0ab0a7f Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

1 0

Change in coreboot[master]: NOTFORMERGE soc/intel/skylake/pei_data: Comment about obsole...
by build bot (Jenkins) (Code Review) 10 May '17

10 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19638 ) Change subject: NOTFORMERGE soc/intel/skylake/pei_data: Comment about obsoleted struct ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53492/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/9287/ : SUCCESS -- To view, visit https://review.coreboot.org/19638 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I6bfd1708b532ab8a59442a46a471fbc5e4f88697 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

1 0

Change in coreboot[master]: fsp1_1: Force per SoC definition of FSP_IMAGE_ID_STRING
by build bot (Jenkins) (Code Review) 10 May '17

10 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19635 ) Change subject: fsp1_1: Force per SoC definition of FSP_IMAGE_ID_STRING ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53489/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/9284/ : SUCCESS -- To view, visit https://review.coreboot.org/19635 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ic86229e7f0c2d0525b8a79add292c6c81a349aa6 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

1 0

Change in coreboot[master]: mainboard: Add ASRock G41C-GS
by Arthur Heymans (Code Review) 09 May '17

09 May '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/18993 ) Change subject: mainboard: Add ASRock G41C-GS ...................................................................... Patch Set 12: (1 comment) https://review.coreboot.org/#/c/18993/10/src/mainboard/asrock/g41c-gs/romst… File src/mainboard/asrock/g41c-gs/romstage.c: Line 69: } > Did you confirm that the reserved bits have the same value as you According to datasheets those reserved bits are 0 by default. It still seemed to work fine. -- To view, visit https://review.coreboot.org/18993 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I992ee07b742dfc59733ce0f3a9be202a530ec6cc Gerrit-PatchSet: 12 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

1 0

Change in coreboot[master]: drivers/i2c: Add new driver for RTC type RX6110 SA
by Mario Scheithauer (Code Review) 09 May '17

09 May '17

Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/19625 ) Change subject: drivers/i2c: Add new driver for RTC type RX6110 SA ...................................................................... Patch Set 2: (11 comments) Thanks for the review! https://review.coreboot.org/#/c/19625/1//COMMIT_MSG Commit Message: PS1, Line 9: th > the Done PS1, Line 11: us > in the Done https://review.coreboot.org/#/c/19625/1/src/drivers/i2c/rx6110sa/chip.h File src/drivers/i2c/rx6110sa/chip.h: PS1, Line 19: /* The day (of the week) is indicated by 7 bits, bit 0 to bit > Can you please add in the comment, that the weekday has to have the value 0 Done https://review.coreboot.org/#/c/19625/1/src/drivers/i2c/rx6110sa/rx6110sa.c File src/drivers/i2c/rx6110sa/rx6110sa.c: PS1, Line 16: #include <device/i2c.h> > The whole driver references I2C transfaers. is not used - removed PS1, Line 18: #include <version.h> > You don't have to use soc/i2c.h as your driver completely relies on device/ changed with #include <device/device.h> PS1, Line 81: data loss, s > "power loss event"? Done PS1, Line 85: > detected, Done PS1, Line 88: > detected, Done PS1, Line 95: b(I2C_BUS_NUM, I > In the other comments you have used lower case for bit descriptions. Want t Done PS1, Line 122: > Maybe better call it "RTC" here as the complete RTC is initialized now? Done PS1, Line 123: i2c_writeb(I2C_BUS_NUM, I2C_DEV_NUM, HOUR_REG, 1); : i2c_writeb(I2C_BUS_NUM, I2C_DEV_NUM, MINUTE_REG, 0); : i2c_writeb(I2C_BUS_NUM, I2C_DEV_NUM, SECOND_REG, 0); > In Line 107 you have written STOP_BIT to control register. Done -- To view, visit https://review.coreboot.org/19625 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I1290a10c2d5ad76a317c99c8b92a013309a605d6 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit May 2017