coreboot-gerrit May 2017

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Change in coreboot[master]: mb/lenovo/x201: Add support for ThinkLight
by build bot (Jenkins) (Code Review) 10 May '17

10 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19644 ) Change subject: mb/lenovo/x201: Add support for ThinkLight ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53502/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/9297/ : SUCCESS -- To view, visit https://review.coreboot.org/19644 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I80285f6630b5830766d82e3ecd174c4a51aa9066 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Stefan Ott <coreboot(a)desire.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: mb/lenovo/x201: Add support for ThinkLight
by Stefan Ott (Code Review) 10 May '17

10 May '17

Stefan Ott has uploaded a new change for review. ( https://review.coreboot.org/19644 ) Change subject: mb/lenovo/x201: Add support for ThinkLight ...................................................................... mb/lenovo/x201: Add support for ThinkLight The thinkpad-acpi driver uses the UCMS (CMOS) ACPI method to control the ThinkLight from the Operating System. This patch adds partial support for that method, enough to enable or disable the ThinkLight: echo on >/proc/acpi/ibm/light echo off >/proc/acpi/ibm/light With the original BIOS the UCMS method exposes a wide range of values through a generic /proc/acpi/ibm/cmos interface. With the changes suggested in this patch that interface is also exposed but only accepts the commands to enable or disable the ThinkLight; all other commands are ignored. This change would potentially benefit all currently supported Thinkpad models, I only have an X201 available for tests though. Change-Id: I80285f6630b5830766d82e3ecd174c4a51aa9066 Signed-off-by: Stefan Ott <stefan(a)ott.net> --- M src/ec/lenovo/h8/acpi/ec.asl M src/mainboard/lenovo/x201/acpi/platform.asl 2 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/19644/1 diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl index ed62afe..eed0e16 100644 --- a/src/ec/lenovo/h8/acpi/ec.asl +++ b/src/ec/lenovo/h8/acpi/ec.asl @@ -107,6 +107,11 @@ Store(Arg0, USPW) } + Method (LGHT, 1, NotSerialized) + { + Store(Arg0, KBLT) + } + /* Sleep Button pressed */ Method(_Q13, 0, NotSerialized) diff --git a/src/mainboard/lenovo/x201/acpi/platform.asl b/src/mainboard/lenovo/x201/acpi/platform.asl index 3aa12e9..0a6d5f3 100644 --- a/src/mainboard/lenovo/x201/acpi/platform.asl +++ b/src/mainboard/lenovo/x201/acpi/platform.asl @@ -67,6 +67,21 @@ Return(Package(){0,0}) } +Method(UCMS, 1, Serialized) +{ + Switch(ToInteger(Arg0)) + { + Case (0x0c) /* Turn on ThinkLight */ + { + \_SB.PCI0.LPCB.EC.LGHT(1) + } + Case (0x0d) /* Turn off ThinkLight */ + { + \_SB.PCI0.LPCB.EC.LGHT(0) + } + } +} + /* System Bus */ Scope(\_SB) -- To view, visit https://review.coreboot.org/19644 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I80285f6630b5830766d82e3ecd174c4a51aa9066 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Stefan Ott <coreboot(a)desire.ch>

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Change in coreboot[master]: drivers/storage: Fix array references
by build bot (Jenkins) (Code Review) 10 May '17

10 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19643 ) Change subject: drivers/storage: Fix array references ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53501/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/9296/ : SUCCESS -- To view, visit https://review.coreboot.org/19643 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ie5c96e78417b667438a00ee22c70894a00d13291 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: drivers/storage: Fix array references
by Lee Leahy (Code Review) 10 May '17

10 May '17

Lee Leahy has uploaded a new change for review. ( https://review.coreboot.org/19643 ) Change subject: drivers/storage: Fix array references ...................................................................... drivers/storage: Fix array references Reduce the loop index by 1 to make coverity happy. The analysis indicated that it was possible to exit the loop without meeting the condition. While this would not happen in the real world the reference beyond the end of the arrays can be eliminated by reducing the index by 1. Coverity Issues: * 1374931 * 1374932 * 1374933 * 1374934 TEST=Build and run on Galileo Gen2 Change-Id: Ie5c96e78417b667438a00ee22c70894a00d13291 Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com> --- M src/drivers/storage/storage.c 1 file changed, 7 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/19643/1 diff --git a/src/drivers/storage/storage.c b/src/drivers/storage/storage.c index 57477f9..daab655 100644 --- a/src/drivers/storage/storage.c +++ b/src/drivers/storage/storage.c @@ -72,6 +72,7 @@ uint64_t capacity; uint64_t decimal_divisor; const char *decimal_units; + int entries; uint64_t hex_divisor; const char *hex_units; int index; @@ -86,9 +87,9 @@ separator = ": "; /* Determine the decimal divisor for the capacity */ - ASSERT(ARRAY_SIZE(decimal_capacity_table) - == ARRAY_SIZE(decimal_unit_name)); - for (index = 0; index < ARRAY_SIZE(decimal_capacity_table); index++) { + entries = ARRAY_SIZE(decimal_capacity_table); + ASSERT(entries == ARRAY_SIZE(decimal_unit_name)); + for (index = 0; index < entries - 1; index++) { if (capacity >= decimal_capacity_table[index]) break; } @@ -96,8 +97,9 @@ decimal_units = decimal_unit_name[index]; /* Determine the hex divisor for the capacity */ - ASSERT(ARRAY_SIZE(hex_capacity_table) == ARRAY_SIZE(hex_unit_name)); - for (index = 0; index < ARRAY_SIZE(hex_capacity_table); index++) { + entries = ARRAY_SIZE(hex_capacity_table); + ASSERT(entries == ARRAY_SIZE(hex_unit_name)); + for (index = 0; index < entries - 1; index++) { if (capacity >= hex_capacity_table[index]) break; } -- To view, visit https://review.coreboot.org/19643 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Ie5c96e78417b667438a00ee22c70894a00d13291 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Lee Leahy <leroy.p.leahy(a)intel.com>

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Change in coreboot[master]: drivers/storage: Make DRVR_CAP_8BIT controller independent
by build bot (Jenkins) (Code Review) 10 May '17

10 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19642 ) Change subject: drivers/storage: Make DRVR_CAP_8BIT controller independent ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53500/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/9295/ : SUCCESS -- To view, visit https://review.coreboot.org/19642 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I51e4c990d3941a9f31915a5703095f92309760f1 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: drivers/storage: Make DRVR_CAP_8BIT controller independent
by Lee Leahy (Code Review) 10 May '17

10 May '17

Lee Leahy has uploaded a new change for review. ( https://review.coreboot.org/19642 ) Change subject: drivers/storage: Make DRVR_CAP_8BIT controller independent ...................................................................... drivers/storage: Make DRVR_CAP_8BIT controller independent Promote DRVR_CAP_8BIT from controller specific to controller independent TEST=Build and run on Galileo Gen2 Change-Id: I51e4c990d3941a9f31915a5703095f92309760f1 Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com> --- M src/include/device/sd_mmc_ctrlr.h M src/include/device/sdhci.h 2 files changed, 18 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/19642/1 diff --git a/src/include/device/sd_mmc_ctrlr.h b/src/include/device/sd_mmc_ctrlr.h index b7541da..2ca2d0f 100644 --- a/src/include/device/sd_mmc_ctrlr.h +++ b/src/include/device/sd_mmc_ctrlr.h @@ -176,16 +176,17 @@ * start at 0x00010000 */ #define DRVR_CAP_4BIT 0x00000001 -#define DRVR_CAP_AUTO_CMD12 0x00000002 -#define DRVR_CAP_HC 0x00000004 -#define DRVR_CAP_HS 0x00000008 -#define DRVR_CAP_HS52 0x00000010 -#define DRVR_CAP_HS200 0x00000020 -#define DRVR_CAP_HS400 0x00000040 -#define DRVR_CAP_ENHANCED_STROBE 0x00000080 -#define DRVR_CAP_REMOVABLE 0x00000100 -#define DRVR_CAP_DMA_64BIT 0x00000200 -#define DRVR_CAP_HS200_TUNING 0x00000400 +#define DRVR_CAP_8BIT 0x00000002 +#define DRVR_CAP_AUTO_CMD12 0x00000004 +#define DRVR_CAP_HC 0x00000008 +#define DRVR_CAP_HS 0x00000010 +#define DRVR_CAP_HS52 0x00000020 +#define DRVR_CAP_HS200 0x00000040 +#define DRVR_CAP_HS400 0x00000080 +#define DRVR_CAP_ENHANCED_STROBE 0x00000100 +#define DRVR_CAP_REMOVABLE 0x00000200 +#define DRVR_CAP_DMA_64BIT 0x00000400 +#define DRVR_CAP_HS200_TUNING 0x00000800 uint32_t b_max; uint32_t timing; diff --git a/src/include/device/sdhci.h b/src/include/device/sdhci.h index f11e589..a86582d 100644 --- a/src/include/device/sdhci.h +++ b/src/include/device/sdhci.h @@ -24,14 +24,13 @@ /* Driver specific capabilities */ #define DRVR_CAP_1V8_VDD 0x00010000 #define DRVR_CAP_32BIT_DMA_ADDR 0x00020000 -#define DRVR_CAP_8BIT 0x00040000 -#define DRVR_CAP_BROKEN_R1B 0x00080000 -#define DRVR_CAP_NO_CD 0x00100000 -#define DRVR_CAP_NO_HISPD_BIT 0x00200000 -#define DRVR_CAP_NO_SIMULT_VDD_AND_POWER 0x00400000 -#define DRVR_CAP_REG32_RW 0x00800000 -#define DRVR_CAP_SPI 0x01000000 -#define DRVR_CAP_WAIT_SEND_CMD 0x02000000 +#define DRVR_CAP_BROKEN_R1B 0x00040000 +#define DRVR_CAP_NO_CD 0x00080000 +#define DRVR_CAP_NO_HISPD_BIT 0x00100000 +#define DRVR_CAP_NO_SIMULT_VDD_AND_POWER 0x00200000 +#define DRVR_CAP_REG32_RW 0x00400000 +#define DRVR_CAP_SPI 0x00800000 +#define DRVR_CAP_WAIT_SEND_CMD 0x01000000 /* ADMA packet descriptor */ struct sdhci_adma { -- To view, visit https://review.coreboot.org/19642 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I51e4c990d3941a9f31915a5703095f92309760f1 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Lee Leahy <leroy.p.leahy(a)intel.com>

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Change in coreboot[master]: drivers/storage: Remove set_control_reg
by Lee Leahy (Code Review) 10 May '17

10 May '17

Lee Leahy has submitted this change and it was merged. ( https://review.coreboot.org/19629 ) Change subject: drivers/storage: Remove set_control_reg ...................................................................... drivers/storage: Remove set_control_reg Remove unused field in generic SD/MMC controller data structure. TEST=Build and run on Galileo Gen2 Change-Id: I7169dca07509a6f2513d62b593742daf764010b2 Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/19629 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- M src/drivers/storage/sdhci.c M src/include/device/sd_mmc_ctrlr.h 2 files changed, 0 insertions(+), 4 deletions(-) Approvals: Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/drivers/storage/sdhci.c b/src/drivers/storage/sdhci.c index f05a47e..c17aa27 100644 --- a/src/drivers/storage/sdhci.c +++ b/src/drivers/storage/sdhci.c @@ -550,9 +550,6 @@ u32 bus_width; int version; - if (ctrlr->set_control_reg) - ctrlr->set_control_reg(ctrlr); - /* Set the clock frequency */ if (ctrlr->bus_hz != ctrlr->request_hz) sdhci_set_clock(sdhci_ctrlr, ctrlr->request_hz); diff --git a/src/include/device/sd_mmc_ctrlr.h b/src/include/device/sd_mmc_ctrlr.h index c3b4f60..b7541da 100644 --- a/src/include/device/sd_mmc_ctrlr.h +++ b/src/include/device/sd_mmc_ctrlr.h @@ -127,7 +127,6 @@ int (*send_cmd)(struct sd_mmc_ctrlr *ctrlr, struct mmc_command *cmd, struct mmc_data *data); void (*set_ios)(struct sd_mmc_ctrlr *ctrlr); - void (*set_control_reg)(struct sd_mmc_ctrlr *ctrlr); void (*tuning_start)(struct sd_mmc_ctrlr *ctrlr, int retune); int (*is_tuning_complete)(struct sd_mmc_ctrlr *ctrlr, int *successful); -- To view, visit https://review.coreboot.org/19629 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I7169dca07509a6f2513d62b593742daf764010b2 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: google/gru: support 800M/928M frequency for bob
by Julius Werner (Code Review) 10 May '17

10 May '17

Julius Werner has posted comments on this change. ( https://review.coreboot.org/19558 ) Change subject: google/gru: support 800M/928M frequency for bob ...................................................................... Patch Set 7: Code-Review+2 Thanks, looks good now I think. -- To view, visit https://review.coreboot.org/19558 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I613050292a09ff56f4636d7af285075e32259ef4 Gerrit-PatchSet: 7 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: mainboard: Add ASRock G41C-GS
by Arthur Heymans (Code Review) 10 May '17

10 May '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/18993 ) Change subject: mainboard: Add ASRock G41C-GS ...................................................................... Patch Set 12: (1 comment) https://review.coreboot.org/#/c/18993/10/src/mainboard/asrock/g41c-gs/romst… File src/mainboard/asrock/g41c-gs/romstage.c: Line 69: } > Those are usually reset defaults. The bits may be set later by hardware. seems like reset default is 0x00090404. -- To view, visit https://review.coreboot.org/18993 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I992ee07b742dfc59733ce0f3a9be202a530ec6cc Gerrit-PatchSet: 12 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: rockchip/rk3399: enable DPLL SSC for DDR EMI test on bob
by Julius Werner (Code Review) 10 May '17

10 May '17

Julius Werner has posted comments on this change. ( https://review.coreboot.org/19557 ) Change subject: rockchip/rk3399: enable DPLL SSC for DDR EMI test on bob ...................................................................... Patch Set 8: (6 comments) https://review.coreboot.org/#/c/19557/4/src/soc/rockchip/rk3399/clock.c File src/soc/rockchip/rk3399/clock.c: Line 373: /* > 0x31f / (2 << 24) == 0.00024% of the intended rate (i.e. 22KHz)? =====> tha Right, I missed that the fraction is additive (not multiplicative) somehow. You're right then, 0 is the correct value. https://review.coreboot.org/#/c/19557/8/src/soc/rockchip/rk3399/clock.c File src/soc/rockchip/rk3399/clock.c: Line 361: * hang in assert() with reboot tests. Which assert() is failing in the failure case? The one below? (That wouldn't really make sense...) Line 382: (PLL_FRACDIV_MASK << PLL_FRACDIV_SHIFT) & I don't really get what the top part here means. Are you trying to only write the 23:0 bits? Then you'd have to use clrsetbits_le32(), since this is not a normal Rockchip write mask register. But since the rest of the bits are RO anyway, I think it should be fine to just set the whole thing to 0. PS8, Line 407: 0 Can you not set spreadamp to 8 here already? PS8, Line 414: Assert This should actually read "Deassert reset", right? Line 423: divval << PLL_SSMOD_DIVVAL_SHIFT)); You're already writing divval above, why write it again? -- To view, visit https://review.coreboot.org/19557 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I75461d4235bcf55324e6664a1220754e770b4786 Gerrit-PatchSet: 8 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Caesar Wang <wxt(a)rock-chips.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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coreboot-gerrit May 2017