coreboot-gerrit May 2017

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Change in coreboot[master]: amd/pi/hudson: Clean up makefile.inc
by build bot (Jenkins) (Code Review) 10 May '17

10 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19640 ) Change subject: amd/pi/hudson: Clean up makefile.inc ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/53497/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/9292/ : SUCCESS -- To view, visit https://review.coreboot.org/19640 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ic8c6ca2b57527fcc96c135cc801a098201bf0465 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/google/poppy/variants/soraka: Enable H1 I2C TPM
by Rajneesh Bhardwaj (Code Review) 10 May '17

10 May '17

Rajneesh Bhardwaj has posted comments on this change. ( https://review.coreboot.org/19519 ) Change subject: mainboard/google/poppy/variants/soraka: Enable H1 I2C TPM ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/19519 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Id9947dce9b7f755971f0199f043af8d251d275ab Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.corp-partner.google.com> Gerrit-Reviewer: Nicolas Boichat <drinkcat(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rajneesh Bhardwaj <rajneesh.bhardwaj(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: amd/pi/hudson: Clean up makefile.inc
by Marc Jones (Code Review) 10 May '17

10 May '17

Marc Jones has uploaded a new change for review. ( https://review.coreboot.org/19640 ) Change subject: amd/pi/hudson: Clean up makefile.inc ...................................................................... amd/pi/hudson: Clean up makefile.inc Sort makefile.inc into rom, ram, ver, smm stages and alphabetize. Change-Id: Ic8c6ca2b57527fcc96c135cc801a098201bf0465 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- M src/southbridge/amd/pi/hudson/Makefile.inc 1 file changed, 26 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/19640/1 diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index f6d7305..4405958 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -28,36 +28,37 @@ # #***************************************************************************** -romstage-y += smbus.c smbus_spd.c -ramstage-y += hudson.c -ramstage-y += usb.c -ramstage-y += lpc.c -ramstage-y += sm.c -ramstage-y += ide.c -ramstage-y += sata.c +romstage-y += early_setup.c +romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c +romstage-y += smbus.c +romstage-y += smbus_spd.c +romstage-$(CONFIG_HUDSON_UART) += uart.c + +verstage-y += early_setup.c +verstage-y += reset.c +verstage-$(CONFIG_HUDSON_UART) += uart.c + +ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c +ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) += gpio.c ramstage-y += hda.c +ramstage-y += hudson.c +ramstage-y += ide.c +ramstage-$(CONFIG_HUDSON_IMC_FWM) += imc.c +ramstage-y += lpc.c ramstage-y += pci.c ramstage-y += pcie.c -ramstage-y += sd.c -ramstage-$(CONFIG_SOUTHBRIDGE_AMD_PI_KERN) += gpio.c - -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c ramstage-y += reset.c -romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c -ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c -romstage-y += early_setup.c -ifeq ($(CONFIG_HUDSON_IMC_FWM), y) -romstage-y += imc.c -ramstage-y += imc.c -endif +ramstage-y += sata.c +ramstage-y += sd.c +ramstage-y += sm.c +ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c +ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c +ramstage-$(CONFIG_HUDSON_UART) += uart.c +ramstage-y += usb.c -ifeq ($(CONFIG_HUDSON_UART), y) -romstage-y += uart.c -ramstage-y += uart.c -endif - -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c smi_util.c -ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smi_util.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c # ROMSIG At ROMBASE + 0x20000: # +-----------+---------------+----------------+------------+ -- To view, visit https://review.coreboot.org/19640 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Ic8c6ca2b57527fcc96c135cc801a098201bf0465 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>

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Change in coreboot[master]: mb/gigabyte/ga-b75m-d3h: Add tpm support for its onboard tpm...
by Martin Roth (Code Review) 10 May '17

10 May '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19521 ) Change subject: mb/gigabyte/ga-b75m-d3h: Add tpm support for its onboard tpm socket ...................................................................... mb/gigabyte/ga-b75m-d3h: Add tpm support for its onboard tpm socket Tested against a lenovo-manufactured tpm 1.2 module: a /dev/tpm0 visible inside GNU/Linux, but there is no menu items in SeaBIOS' interface, which seems a common issue of SeaBIOS on ivb boards. Change-Id: Id0dee74d945bae5d77eb669d8b9d468a67aee508 Signed-off-by: Bill XIE <persmule(a)gmail.com> Reviewed-on: https://review.coreboot.org/19521 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/gigabyte/ga-b75m-d3h/Kconfig M src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb 2 files changed, 6 insertions(+), 0 deletions(-) Approvals: Philipp Deppenwiese: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig index a9fd50d..4b4909a 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig @@ -18,6 +18,8 @@ select UDELAY_TSC select SERIRQ_CONTINUOUS_MODE select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_LPC_TPM + select TPM config MMCONF_BASE_ADDRESS hex diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb index 2cd3816..3659354 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -109,6 +109,10 @@ device pnp 2e.7 off end # GPIO device pnp 2e.a off end # IR end + + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end end device pci 1f.2 on # SATA Controller 1 subsystemid 0x1458 0xb005 -- To view, visit https://review.coreboot.org/19521 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: Id0dee74d945bae5d77eb669d8b9d468a67aee508 Gerrit-PatchSet: 12 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: superio/ite/it8728f: Hook up common environment-controller d...
by Martin Roth (Code Review) 10 May '17

10 May '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19293 ) Change subject: superio/ite/it8728f: Hook up common environment-controller driver ...................................................................... superio/ite/it8728f: Hook up common environment-controller driver This replaces the custom environment controller handling in the it8728 driver with the common library. It also updates the two existing boards with hwm register settings in their devicetree config so they better match their vendor BIOS fan control settings. Change-Id: Idf0c8908ba5ad6ff552b8302bffc638aa9052941 Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Reviewed-on: https://review.coreboot.org/19293 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb M src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb M src/superio/ite/it8728f/Kconfig M src/superio/ite/it8728f/Makefile.inc M src/superio/ite/it8728f/chip.h D src/superio/ite/it8728f/it8728f_hwm.c M src/superio/ite/it8728f/superio.c 7 files changed, 48 insertions(+), 93 deletions(-) Approvals: Felix Held: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb index d942445..e1fbc51 100644 --- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb +++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb @@ -58,12 +58,22 @@ device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d chip superio/ite/it8728f - register hwm_ctl_register = "0xc0" - register hwm_main_ctl_register = "0x33" - register hwm_adc_temp_chan_en_reg = "0x38" - register hwm_fan1_ctl_pwm = "0x00" - register hwm_fan2_ctl_pwm = "0x00" - register hwm_fan3_ctl_pwm = "0x00" + register "TMPIN1" = "THERMAL_RESISTOR" + register "TMPIN2" = "THERMAL_RESISTOR" + register "TMPIN3" = "THERMAL_RESISTOR" + + register "FAN1.mode" = "FAN_SMART_AUTOMATIC" + register "FAN1.smart.tmpin" = "1" + register "FAN1.smart.tmp_off" = "0x80" # never + register "FAN1.smart.tmp_start" = "20" + register "FAN1.smart.tmp_full" = "70" + register "FAN1.smart.tmp_delta" = "0" + register "FAN1.smart.smoothing" = "1" + register "FAN1.smart.pwm_start" = "20" + register "FAN1.smart.slope" = "32" + + # Enable tacho reading for chassis fan. + register "FAN2.mode" = "FAN_MODE_OFF" device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb index d83f466..128ff18 100644 --- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb +++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb @@ -58,12 +58,22 @@ device pci 14.2 on end # HDA 0x4383 device pci 14.3 on # LPC 0x439d chip superio/ite/it8728f - register hwm_ctl_register = "0xc0" - register hwm_main_ctl_register = "0x33" - register hwm_adc_temp_chan_en_reg = "0x38" - register hwm_fan1_ctl_pwm = "0x00" - register hwm_fan2_ctl_pwm = "0x00" - register hwm_fan3_ctl_pwm = "0x00" + register "TMPIN1" = "THERMAL_RESISTOR" + register "TMPIN2" = "THERMAL_RESISTOR" + register "TMPIN3" = "THERMAL_RESISTOR" + + register "FAN1.mode" = "FAN_SMART_AUTOMATIC" + register "FAN1.smart.tmpin" = "1" + register "FAN1.smart.tmp_off" = "0x80" # never + register "FAN1.smart.tmp_start" = "20" + register "FAN1.smart.tmp_full" = "70" + register "FAN1.smart.tmp_delta" = "0" + register "FAN1.smart.smoothing" = "1" + register "FAN1.smart.pwm_start" = "20" + register "FAN1.smart.slope" = "32" + + # Enable tacho reading for chassis fan. + register "FAN2.mode" = "FAN_MODE_OFF" device pnp 2e.0 off # Floppy io 0x60 = 0x3f0 diff --git a/src/superio/ite/it8728f/Kconfig b/src/superio/ite/it8728f/Kconfig index 12af418..90c3b50 100644 --- a/src/superio/ite/it8728f/Kconfig +++ b/src/superio/ite/it8728f/Kconfig @@ -17,3 +17,7 @@ config SUPERIO_ITE_IT8728F bool select SUPERIO_ITE_COMMON_ROMSTAGE + select SUPERIO_ITE_ENV_CTRL + select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 + select SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG + select SUPERIO_ITE_ENV_CTRL_8BIT_PWM diff --git a/src/superio/ite/it8728f/Makefile.inc b/src/superio/ite/it8728f/Makefile.inc index e0e26f4..fb75418 100644 --- a/src/superio/ite/it8728f/Makefile.inc +++ b/src/superio/ite/it8728f/Makefile.inc @@ -14,5 +14,4 @@ ## GNU General Public License for more details. ## -ramstage-$(CONFIG_SUPERIO_ITE_IT8728F) += it8728f_hwm.c ramstage-$(CONFIG_SUPERIO_ITE_IT8728F) += superio.c diff --git a/src/superio/ite/it8728f/chip.h b/src/superio/ite/it8728f/chip.h index c925c85..3442439 100644 --- a/src/superio/ite/it8728f/chip.h +++ b/src/superio/ite/it8728f/chip.h @@ -17,14 +17,10 @@ #ifndef SUPERIO_ITE_IT8728F_CHIP_H #define SUPERIO_ITE_IT8728F_CHIP_H +#include <superio/ite/common/env_ctrl_chip.h> + struct superio_ite_it8728f_config { - /* HWM configuration registers */ - uint8_t hwm_ctl_register; - uint8_t hwm_main_ctl_register; - uint8_t hwm_adc_temp_chan_en_reg; - uint8_t hwm_fan1_ctl_pwm; - uint8_t hwm_fan2_ctl_pwm; - uint8_t hwm_fan3_ctl_pwm; + struct ite_ec_config ec; }; #endif /* SUPERIO_ITE_IT8728F_CHIP_H */ diff --git a/src/superio/ite/it8728f/it8728f_hwm.c b/src/superio/ite/it8728f/it8728f_hwm.c deleted file mode 100644 index 5ab4a39..0000000 --- a/src/superio/ite/it8728f/it8728f_hwm.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pnp.h> -#include "chip.h" -#include "it8728f_internal.h" - -/* - * FAN controller configuration register index's - */ -#define HWM_MAIN_CTL_REG 0x13 /* default 0x07 */ -#define HWM_CTL_REG 0x14 /* default 0x40 */ -#define HWM_FAN1_CTL_PWM 0x15 /* default 0x00 */ -#define HWM_FAN2_CTL_PWM 0x16 /* default 0x00 */ -#define HWM_FAN3_CTL_PWM 0x17 /* default 0x00 */ -#define HWM_ADC_TEMP_CHAN_EN_REG 0x51 /* default 0x00 */ - -void it8728f_hwm_ec_init(struct device *dev) -{ - struct superio_ite_it8728f_config *conf = dev->chip_info; - struct resource *res = find_resource(dev, PNP_IDX_IO0); - - if (!res) { - printk(BIOS_WARNING, "Super I/O HWM: No HWM resource found.\n"); - return; - } - /* I/O port for HWM is at base + 5 */ - u16 port = res->base + 5; - - printk(BIOS_INFO, - "ITE IT8728F Super I/O HWM: Initializing Hardware Monitor..\n"); - printk(BIOS_DEBUG, - "ITE IT8728F Super I/O HWM: Base Address at 0x%x\n", port); - - pnp_enter_conf_mode(dev); - pnp_set_logical_device(dev); - - /* ITE IT8728F HWM (ordered) programming sequence. */ - - /* configure fan polarity */ - pnp_write_index(port, HWM_CTL_REG, conf->hwm_ctl_register); - - /* enable fans 1-3 */ - pnp_write_index(port, HWM_MAIN_CTL_REG, conf->hwm_main_ctl_register); - - /* enable termistor temps for temp1-temp3 */ - pnp_write_index(port, HWM_ADC_TEMP_CHAN_EN_REG, conf->hwm_adc_temp_chan_en_reg); - - /* configure which fanX uses which tempY */ - pnp_write_index(port, HWM_FAN1_CTL_PWM, conf->hwm_fan1_ctl_pwm); - pnp_write_index(port, HWM_FAN2_CTL_PWM, conf->hwm_fan2_ctl_pwm); - pnp_write_index(port, HWM_FAN3_CTL_PWM, conf->hwm_fan3_ctl_pwm); - - pnp_exit_conf_mode(dev); -} diff --git a/src/superio/ite/it8728f/superio.c b/src/superio/ite/it8728f/superio.c index 9a1ceb1..b8c5b22 100644 --- a/src/superio/ite/it8728f/superio.c +++ b/src/superio/ite/it8728f/superio.c @@ -21,6 +21,7 @@ #include <console/console.h> #include <pc80/keyboard.h> #include <stdlib.h> +#include <superio/ite/common/env_ctrl.h> #include "chip.h" #include "it8728f.h" @@ -28,13 +29,19 @@ static void it8728f_init(struct device *dev) { + const struct superio_ite_it8728f_config *conf = dev->chip_info; + const struct resource *res; + if (!dev->enabled) return; switch(dev->path.pnp.device) { - /* TODO: Might potentially need code for HWM or FDC etc. */ + /* TODO: Might potentially need code for FDC etc. */ case IT8728F_EC: - it8728f_hwm_ec_init(dev); + res = find_resource(dev, PNP_IDX_IO0); + if (!conf || !res) + break; + ite_ec_init(res->base, &conf->ec); break; case IT8728F_KBCK: set_kbc_ps2_mode(); -- To view, visit https://review.coreboot.org/19293 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: Idf0c8908ba5ad6ff552b8302bffc638aa9052941 Gerrit-PatchSet: 8 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rudolf Marek <r.marek(a)assembler.cz> Gerrit-Reviewer: Sergej Ivanov <getinaks(a)gmail.com> Gerrit-Reviewer: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/skylake: Use common/blocks/uart code
by Martin Roth (Code Review) 10 May '17

10 May '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19492 ) Change subject: soc/intel/skylake: Use common/blocks/uart code ...................................................................... soc/intel/skylake: Use common/blocks/uart code Change-Id: I53ed687dc49524e001889f091825b2cc530546a3 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> Reviewed-on: https://review.coreboot.org/19492 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- M src/soc/intel/skylake/uart.c 1 file changed, 2 insertions(+), 28 deletions(-) Approvals: Aaron Durbin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/skylake/uart.c b/src/soc/intel/skylake/uart.c index 88bb784..07326d5 100644 --- a/src/soc/intel/skylake/uart.c +++ b/src/soc/intel/skylake/uart.c @@ -14,20 +14,17 @@ * GNU General Public License for more details. */ -#include <device/device.h> #include <device/pci.h> -#include <device/pci_ids.h> -#include <stdlib.h> +#include <intelblocks/uart.h> #include <soc/iomap.h> #include <soc/pci_devs.h> -#include <soc/ramstage.h> static int pch_uart_is_debug(struct device *dev) { return dev->path.pci.devfn == PCH_DEVFN_UART2; } -static void pch_uart_read_resources(struct device *dev) +void pch_uart_read_resources(struct device *dev) { pci_dev_read_resources(dev); @@ -41,26 +38,3 @@ IORESOURCE_FIXED; } } - -static struct device_operations device_ops = { - .read_resources = &pch_uart_read_resources, - .set_resources = &pci_dev_set_resources, - .enable_resources = &pci_dev_enable_resources, - .ops_pci = &soc_pci_ops, -}; - -static const unsigned short pci_device_ids[] = { - 0x9d27, /* UART0 */ - 0x9d28, /* UART1 */ - 0x9d66, /* UART2 */ - 0xa127, /* KBL-H UART0 */ - 0xa128, /* KBL-H UART1 */ - 0xa166, /* KBL-H UART2 */ - 0 -}; - -static const struct pci_driver pch_uart __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, -}; -- To view, visit https://review.coreboot.org/19492 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I53ed687dc49524e001889f091825b2cc530546a3 Gerrit-PatchSet: 8 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/apollolake: Use common/block/uart code
by Martin Roth (Code Review) 10 May '17

10 May '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19491 ) Change subject: soc/intel/apollolake: Use common/block/uart code ...................................................................... soc/intel/apollolake: Use common/block/uart code Change-Id: I92c654d59f1642bcd7c95de80dcc641bf816b542 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> Reviewed-on: https://review.coreboot.org/19491 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- M src/soc/intel/apollolake/include/soc/pci_ids.h M src/soc/intel/apollolake/uart.c 2 files changed, 2 insertions(+), 28 deletions(-) Approvals: Aaron Durbin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/apollolake/include/soc/pci_ids.h b/src/soc/intel/apollolake/include/soc/pci_ids.h index 8e1ac9f..25e7f94 100644 --- a/src/soc/intel/apollolake/include/soc/pci_ids.h +++ b/src/soc/intel/apollolake/include/soc/pci_ids.h @@ -35,10 +35,6 @@ #define PCI_DEVICE_ID_APOLLOLAKE_I2C5 0x5ab6 /* 00:17.1 */ #define PCI_DEVICE_ID_APOLLOLAKE_I2C6 0x5ab8 /* 00:17.2 */ #define PCI_DEVICE_ID_APOLLOLAKE_I2C7 0x5aba /* 00:17.3 */ -#define PCI_DEVICE_ID_APOLLOLAKE_UART0 0x5abc /* 00:18.0 */ -#define PCI_DEVICE_ID_APOLLOLAKE_UART1 0x5abe /* 00:18.1 */ -#define PCI_DEVICE_ID_APOLLOLAKE_UART2 0x5ac0 /* 00:18.2 */ -#define PCI_DEVICE_ID_APOLLOLAKE_UART3 0x5aee /* 00:18.3 */ #define PCI_DEVICE_ID_APOLLOLAKE_SPI0 0x5ac2 /* 00:19.0 */ #define PCI_DEVICE_ID_APOLLOLAKE_SPI1 0x5ac4 /* 00:19.1 */ #define PCI_DEVICE_ID_APOLLOLAKE_SPI2 0x5ac6 /* 00:19.2 */ diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c index 70d034f..3db460a 100644 --- a/src/soc/intel/apollolake/uart.c +++ b/src/soc/intel/apollolake/uart.c @@ -20,14 +20,12 @@ * shouldn't cause any fragmentation. */ -#include <console/uart.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_ids.h> -#include <soc/pci_ids.h> +#include <intelblocks/uart.h> #include <soc/pci_devs.h> -static void aplk_uart_read_resources(struct device *dev) +void pch_uart_read_resources(struct device *dev) { pci_dev_read_resources(dev); @@ -39,23 +37,3 @@ CONFIG_CONSOLE_UART_BASE_ADDRESS >> 10, 4, 0); } } - -static struct device_operations uart_ops = { - .read_resources = aplk_uart_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = pci_dev_init, - .enable = DEVICE_NOOP -}; - -static const unsigned short uart_ids[] = { - PCI_DEVICE_ID_APOLLOLAKE_UART0, PCI_DEVICE_ID_APOLLOLAKE_UART1, - PCI_DEVICE_ID_APOLLOLAKE_UART2, PCI_DEVICE_ID_APOLLOLAKE_UART3, - 0 -}; - -static const struct pci_driver uart_driver __pci_driver = { - .ops = &uart_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = uart_ids -}; -- To view, visit https://review.coreboot.org/19491 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I92c654d59f1642bcd7c95de80dcc641bf816b542 Gerrit-PatchSet: 8 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/apollolake: Use common/block/uart code
by build bot (Jenkins) (Code Review) 10 May '17

10 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19491 ) Change subject: soc/intel/apollolake: Use common/block/uart code ...................................................................... Patch Set 7: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53495/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/9290/ : SUCCESS -- To view, visit https://review.coreboot.org/19491 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I92c654d59f1642bcd7c95de80dcc641bf816b542 Gerrit-PatchSet: 7 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common: Add PCI configuration code for UART
by Martin Roth (Code Review) 10 May '17

10 May '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19490 ) Change subject: soc/intel/common: Add PCI configuration code for UART ...................................................................... soc/intel/common: Add PCI configuration code for UART Add PCI configuration code support for intel/common/ block/uart module. Change-Id: Ibce5623ffb879f2427b759106d1f350601837e4b Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> Reviewed-on: https://review.coreboot.org/19490 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- M src/soc/intel/common/block/include/intelblocks/uart.h M src/soc/intel/common/block/uart/Makefile.inc M src/soc/intel/common/block/uart/uart.c 3 files changed, 41 insertions(+), 2 deletions(-) Approvals: Aaron Durbin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/common/block/include/intelblocks/uart.h b/src/soc/intel/common/block/include/intelblocks/uart.h index ed4c7f0..b46edd7 100644 --- a/src/soc/intel/common/block/include/intelblocks/uart.h +++ b/src/soc/intel/common/block/include/intelblocks/uart.h @@ -17,8 +17,11 @@ #define SOC_INTEL_COMMON_BLOCK_UART_H #include <arch/io.h> +#include <device/device.h> void uart_common_init(device_t dev, uintptr_t baseaddr, uint32_t clk_m_val, uint32_t clk_n_val); +void pch_uart_read_resources(struct device *dev); + #endif /* SOC_INTEL_COMMON_BLOCK_UART_H */ diff --git a/src/soc/intel/common/block/uart/Makefile.inc b/src/soc/intel/common/block/uart/Makefile.inc index 13f5da8..0ec5314 100644 --- a/src/soc/intel/common/block/uart/Makefile.inc +++ b/src/soc/intel/common/block/uart/Makefile.inc @@ -1 +1,2 @@ -bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_UART) += uart.c \ No newline at end of file +bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_UART) += uart.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_UART) += uart.c \ No newline at end of file diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 729a31b..8c5e454 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -12,8 +12,10 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ - +#include <device/device.h> +#include <device/pci.h> #include <device/pci_def.h> +#include <device/pci_ids.h> #include <intelblocks/lpss.h> #include <intelblocks/uart.h> @@ -33,3 +35,36 @@ /* Set M and N divisor inputs and enable clock */ lpss_clk_update(baseaddr, clk_m_val, clk_n_val); } + +#if ENV_RAMSTAGE + +__attribute__((weak)) void pch_uart_read_resources(struct device *dev) +{ + pci_dev_read_resources(dev); +} + +static struct device_operations device_ops = { + .read_resources = &pch_uart_read_resources, + .set_resources = &pci_dev_set_resources, + .enable_resources = &pci_dev_enable_resources, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_SPT_UART0, + PCI_DEVICE_ID_INTEL_SPT_UART1, + PCI_DEVICE_ID_INTEL_SPT_UART2, + PCI_DEVICE_ID_INTEL_KBP_H_UART0, + PCI_DEVICE_ID_INTEL_KBP_H_UART1, + PCI_DEVICE_ID_INTEL_KBP_H_UART2, + PCI_DEVICE_ID_INTEL_APL_UART0, + PCI_DEVICE_ID_INTEL_APL_UART1, + PCI_DEVICE_ID_INTEL_APL_UART2, + PCI_DEVICE_ID_INTEL_APL_UART3, +}; + +static const struct pci_driver pch_uart __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; +#endif /* ENV_RAMSTAGE */ -- To view, visit https://review.coreboot.org/19490 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: Ibce5623ffb879f2427b759106d1f350601837e4b Gerrit-PatchSet: 8 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/common: Add PCI configuration code for UART
by build bot (Jenkins) (Code Review) 10 May '17

10 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19490 ) Change subject: soc/intel/common: Add PCI configuration code for UART ...................................................................... Patch Set 7: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53494/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/9289/ : SUCCESS -- To view, visit https://review.coreboot.org/19490 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ibce5623ffb879f2427b759106d1f350601837e4b Gerrit-PatchSet: 7 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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