build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19558 )
Change subject: google/gru: support 800M/928M frequency for bob
......................................................................
Patch Set 9: Verified+1
Build Successful
https://qa.coreboot.org/job/coreboot-gerrit/53505/ : SUCCESS
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19557 )
Change subject: rockchip/rk3399: enable DPLL SSC for DDR EMI test on bob
......................................................................
Patch Set 9: Verified+1
Build Successful
https://qa.coreboot.org/job/coreboot-gerrit/53503/ : SUCCESS
https://qa.coreboot.org/job/coreboot-checkpatch/9298/ : SUCCESS
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Change subject: google/gru: support 800M/928M frequency for bob
......................................................................
Patch Set 8: Verified-1
Build Failed
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https://qa.coreboot.org/job/coreboot-checkpatch/9299/ : SUCCESS
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Hello Julius Werner, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/19558
to look at the new patch set (#9).
Change subject: google/gru: support 800M/928M frequency for bob
......................................................................
google/gru: support 800M/928M frequency for bob
The coreboot had no supported the different frequency for gru yet.
e.g:
we can't support the bob to run ddr 800M for rev3 board and
run 928M for rev4 board.
So, in order to support the 800M and 928M ddr frequency for bob different
boards. We will use the ram_id and board_id to select the board on bob.
Change-Id: I613050292a09ff56f4636d7af285075e32259ef4
Signed-off-by: Caesar Wang <wxt(a)rock-chips.com>
---
M src/mainboard/google/gru/Kconfig
M src/mainboard/google/gru/Makefile.inc
M src/mainboard/google/gru/sdram_configs.c
R src/mainboard/google/gru/sdram_params/Makefile.inc
R src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-928.c
R src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-2GB-800.c
R src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-2GB-928.c
R src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-4GB-800.c
R src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-4GB-928.c
R src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-2GB-24EB-800.c
R src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-2GB-24EB-928.c
R src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-4GB-04EB-800.c
R src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-4GB-04EB-928.c
D src/mainboard/google/gru/sdram_params_933/Makefile.inc
14 files changed, 37 insertions(+), 48 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/19558/9
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Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
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Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Hello Julius Werner, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/19558
to look at the new patch set (#8).
Change subject: google/gru: support 800M/928M frequency for bob
......................................................................
google/gru: support 800M/928M frequency for bob
The coreboot had no supported the different frequency for gru yet.
e.g:
we can't support the bob to run ddr 800M for rev3 board and
run 928M for rev4 board.
So, in order to support the 800M and 928M ddr frequency for bob different
boards. We will use the ram_id and board_id to select the board on bob.
BRANCH=none
BUG=b:36666655
TEST=boot from bob, tested with memtester/s2r/reboot on bob.
Change-Id: I613050292a09ff56f4636d7af285075e32259ef4
Signed-off-by: Caesar Wang <wxt(a)rock-chips.com>
---
M src/mainboard/google/gru/Kconfig
M src/mainboard/google/gru/Makefile.inc
M src/mainboard/google/gru/sdram_configs.c
R src/mainboard/google/gru/sdram_params/Makefile.inc
R src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-928.c
R src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-2GB-800.c
R src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-2GB-928.c
R src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-4GB-800.c
R src/mainboard/google/gru/sdram_params/sdram-lpddr3-micron-4GB-928.c
R src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-2GB-24EB-800.c
R src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-2GB-24EB-928.c
R src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-4GB-04EB-800.c
R src/mainboard/google/gru/sdram_params/sdram-lpddr3-samsung-4GB-04EB-928.c
D src/mainboard/google/gru/sdram_params_933/Makefile.inc
14 files changed, 37 insertions(+), 48 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/19558/8
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Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
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Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/19557
to look at the new patch set (#9).
Change subject: rockchip/rk3399: enable DPLL SSC for DDR EMI test on bob
......................................................................
rockchip/rk3399: enable DPLL SSC for DDR EMI test on bob
Spread Spectrum Modulator (SSMOD) is a fully-digital circuit used to
modulate the frequency of the Silicon Creations’ Fractional PLL in order
to reduce EMI.
We need to turn the DPLL spread spectrum feature on to
reduce the EMI noise for DDR on bob.
Change-Id: I75461d4235bcf55324e6664a1220754e770b4786
Signed-off-by: Xing Zheng <zhengxing(a)rock-chips.com>
Signed-off-by: Caesar Wang <wxt(a)rock-chips.com>
---
M src/mainboard/google/gru/Kconfig
M src/soc/rockchip/rk3399/Kconfig
M src/soc/rockchip/rk3399/clock.c
3 files changed, 110 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/19557/9
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Caesar Wang has abandoned this change. ( https://review.coreboot.org/19622 )
Change subject: src/include: remove the __ROMCC__ to enable snprintf
......................................................................
Abandoned
Okay, fixes it with other patches.
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Caesar Wang has posted comments on this change. ( https://review.coreboot.org/19558 )
Change subject: google/gru: support 800M/928M frequency for bob
......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/#/c/19558/6/src/mainboard/google/gru/sdram_para…
File src/mainboard/google/gru/sdram_params/Makefile.inc:
Line 22: sdram-params += sdram-lpddr3-samsung-2GB-24EB-928
> Sorry, forget it. Do we need change it?
Done
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Caesar Wang has posted comments on this change. ( https://review.coreboot.org/19558 )
Change subject: google/gru: support 800M/928M frequency for bob
......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/#/c/19558/6/src/mainboard/google/gru/sdram_para…
File src/mainboard/google/gru/sdram_params/Makefile.inc:
Line 22: sdram-params += sdram-lpddr3-samsung-2GB-24EB-928
> nit: would look better grouping all frequencies of the same chip together,
Sorry, forget it. Do we need change it?
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Caesar Wang has posted comments on this change. ( https://review.coreboot.org/19557 )
Change subject: rockchip/rk3399: enable DPLL SSC for DDR EMI test on bob
......................................................................
Patch Set 8:
(3 comments)
https://review.coreboot.org/#/c/19557/8/src/soc/rockchip/rk3399/clock.c
File src/soc/rockchip/rk3399/clock.c:
Line 361: * hang in assert() with reboot tests.
> Which assert() is failing in the failure case? The one below? (That wouldn'
Yes, it's related to "assert(dpll_cfg->refdiv && dpll_cfg->refdiv <= 6);"
As the previous said:"
+ if (!(dpll_cfg->refdiv && dpll_cfg->refdiv <=6)) {
+ printk(BIOS_ERR,"%s: failed to get refdiv(%d)\n",__func__,
+ dpll_cfg->refdiv);
+ return;
+ }
That's fine from the short test. I don't see the error log.
That's weird, we should printf the log if the assert() failed."
e.g: assert(0) should output the error log.
PS8, Line 414: Assert
> This should actually read "Deassert reset", right?
oh, right.
Line 423: divval << PLL_SSMOD_DIVVAL_SHIFT));
> You're already writing divval above, why write it again?
Okay. drop it.
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