Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/18985 )
Change subject: [WIP] mainboards/hp: Add HP Elitebook 8470p
......................................................................
Patch Set 6:
(8 comments)
A few nits but it looks quite alright.
https://review.coreboot.org/#/c/18985/6//COMMIT_MSG
Commit Message:
PS6, Line 25: - AC and battery status
vendor DSDT might hold the answer to that (in the hope that no SMM is used for that...)?
https://review.coreboot.org/#/c/18985/6/src/mainboard/hp/8470p/Kconfig
File src/mainboard/hp/8470p/Kconfig:
PS6, Line 37: config VGA_BIOS_FILE
: string
: default "pci8086,0166.rom"
should be set automatically by VGA_BIOS_ID
https://review.coreboot.org/#/c/18985/6/src/mainboard/hp/8470p/acpi/platfor…
File src/mainboard/hp/8470p/acpi/platform.asl:
Line 1: Method(_WAK,1)
licence header.
https://review.coreboot.org/#/c/18985/6/src/mainboard/hp/8470p/board_info.t…
File src/mainboard/hp/8470p/board_info.txt:
Line 1: Category: laptop
maybe add link to vendor website page for this device?
https://review.coreboot.org/#/c/18985/6/src/mainboard/hp/8470p/devicetree.cb
File src/mainboard/hp/8470p/devicetree.cb:
PS6, Line 16: 0x0d9c0d9c
just a suggestion: if you don't want to be at full brightness (annyoing in the dark) you could lower duty cycle = lower 16 bits divided by upper 16 bits. so 50% would be 0x0d9c06ce
https://review.coreboot.org/#/c/18985/6/src/mainboard/hp/8470p/gpio.c
File src/mainboard/hp/8470p/gpio.c:
Line 1: /*
you could use https://review.coreboot.org/#/c/19508/ to generate this file again so entries that that are very meaningful are omitted.
https://review.coreboot.org/#/c/18985/6/src/mainboard/hp/8470p/mainboard.c
File src/mainboard/hp/8470p/mainboard.c:
PS6, Line 37: nstall_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
: }
split line.
https://review.coreboot.org/#/c/18985/6/src/mainboard/hp/8470p/romstage.c
File src/mainboard/hp/8470p/romstage.c:
PS6, Line 16: #include <stdint.h>
: #include <string.h>
: #include <lib.h>
: #include <timestamp.h>
: #include <arch/byteorder.h>
: #include <arch/io.h>
: #include <device/pci_def.h>
: #include <device/pnp_def.h>
: #include <cpu/x86/lapic.h>
: #include <arch/acpi.h>
: #include <console/console.h>
: #include "northbridge/intel/sandybridge/sandybridge.h"
: #include "northbridge/intel/sandybridge/raminit_native.h"
: #include "southbridge/intel/bd82x6x/pch.h"
: #include <southbridge/intel/common/gpio.h>
: #include <arch/cpu.h>
: #include <cpu/x86/msr.h>
I think the only ones needed would be #include <arch/io.h> and #include <northbridge/intel/sandybridge/raminit_native.h>.
Better also #include <southbridge/intel/bd82x6x/pch.h> and #include <northbridge/intel/sandybridge/sandybridge.h>
since that is where the actual stuff you need is.
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Hello Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/18241
to look at the new patch set (#19).
Change subject: [WIP] mainboards/hp: Add HP Elitebook 2760p
......................................................................
[WIP] mainboards/hp: Add HP Elitebook 2760p
The code is generated by autoport.
The flash chip is socketed beside the WLAN slot. The EHCI debug port
is on right side of the laptop beside the RJ11 connector.
Things that work:
- memory: 0+8G, 4G+8G
- Linux (Linux Mint 18.1 with Linux 4.4)
- native graphics init + SeaBIOS payload with SeaVGABIOS
- all 3 USB ports
- WLAN
- WWAN
- expresscard
- S3 suspend and resume
- internal flashing after IFD is unlocked and coreboot is flashed
- keyboard, trackpoint and touchpad
- fan control
Things that don't work:
- AC and battery status
- wacom digitizer
Things that are not tested:
- WWAN
- SD card reader
- smart card reader
- cable modem
(EC) blobs:
This laptop uses SMSC KBC1126-NU as EC. It needs two blobs in the
flash chip. You can use the tools in util/kbc1126 to extract them
from OEM firmware, and use the following configuration to insert
them to coreboot image:
-> Chipset
-> Add firmware images for KBC1126 firmware
Change-Id: I3ffdb9f9c71f6c9a84e896abc3c424c8dd4bed0e
Signed-off-by: Iru Cai <mytbk920423(a)gmail.com>
---
A src/mainboard/hp/2760p/Kconfig
A src/mainboard/hp/2760p/Kconfig.name
A src/mainboard/hp/2760p/Makefile.inc
A src/mainboard/hp/2760p/acpi/ec.asl
A src/mainboard/hp/2760p/acpi/platform.asl
A src/mainboard/hp/2760p/acpi/superio.asl
A src/mainboard/hp/2760p/acpi_tables.c
A src/mainboard/hp/2760p/board_info.txt
A src/mainboard/hp/2760p/devicetree.cb
A src/mainboard/hp/2760p/dsdt.asl
A src/mainboard/hp/2760p/gma-mainboard.ads
A src/mainboard/hp/2760p/gpio.c
A src/mainboard/hp/2760p/hda_verb.c
A src/mainboard/hp/2760p/mainboard.c
A src/mainboard/hp/2760p/romstage.c
15 files changed, 798 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/18241/19
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19523 )
Change subject: mb/lenovo/s230u: fix sata port map for the msata port
......................................................................
Patch Set 11:
Build Successful
https://qa.coreboot.org/job/coreboot-gerrit/53506/ : SUCCESS
https://qa.coreboot.org/job/coreboot-checkpatch/9300/ : SUCCESS
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/16902 )
Change subject: soc/intel/skylake: Implement Global Reset MEI message
......................................................................
Patch Set 9:
(1 comment)
https://review.coreboot.org/#/c/16902/9/src/soc/intel/skylake/me.c
File src/soc/intel/skylake/me.c:
Line 588: status = recv_heci_packet(&head, message + (cur >> 2),
> Ya. It looks to still be using bytes and dwords in the wrong place.
we shall get rid of this code very soon as and when we migrate into common CSE code for big core platform as well. This is next target. if you need this to be fixed now, need to look
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