coreboot-gerrit May 2017

coreboot-gerrit@coreboot.org

1 participants
3888 discussions

Change in coreboot[master]: soc/intel/skylake: C-state interrupt response time
by Subrata Banik (Code Review) 12 May '17

12 May '17

Subrata Banik has uploaded a new change for review. ( https://review.coreboot.org/19675 ) Change subject: soc/intel/skylake: C-state interrupt response time ...................................................................... soc/intel/skylake: C-state interrupt response time Program C3/C7/C10 interrupt response time for all cores. Change-Id: I4f47502e1c212118d7cc89d4de60a1854072964a Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/skylake/cpu.c 1 file changed, 41 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/19675/1 diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 2f35635..38fe54c 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -360,6 +360,44 @@ } } +static void configure_c_states(void) +{ + msr_t msr; + + /* C-state Interrupt Response Latency Control 0 - package C3 latency */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_0_LIMIT; + wrmsr(MSR_C_STATE_LATENCY_CONTROL_0, msr); + + /* C-state Interrupt Response Latency Control 1 */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_1_LIMIT; + wrmsr(MSR_C_STATE_LATENCY_CONTROL_1, msr); + + /* C-state Interrupt Response Latency Control 2 - package C6/C7 short */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_1024_NS | C_STATE_LATENCY_CONTROL_2_LIMIT; + wrmsr(MSR_C_STATE_LATENCY_CONTROL_2, msr); + + /* C-state Interrupt Response Latency Control 3 - package C8 */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_1024_NS | + C_STATE_LATENCY_CONTROL_3_LIMIT; + wrmsr(MSR_C_STATE_LATENCY_CONTROL_3, msr); + + /* C-state Interrupt Response Latency Control 4 - package C9 */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_1024_NS | + C_STATE_LATENCY_CONTROL_4_LIMIT; + wrmsr(MSR_C_STATE_LATENCY_CONTROL_4, msr); + + /* C-state Interrupt Response Latency Control 5 - package C10 */ + msr.hi = 0; + msr.lo = IRTL_VALID | IRTL_1024_NS | + C_STATE_LATENCY_CONTROL_5_LIMIT; + wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr); +} + /* All CPUs including BSP will run the following function. */ static void cpu_core_init(device_t cpu) { @@ -370,6 +408,9 @@ enable_lapic_tpr(); setup_lapic(); + /* Configure c-state interrupt response time */ + configure_c_states(); + /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); -- To view, visit https://review.coreboot.org/19675 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I4f47502e1c212118d7cc89d4de60a1854072964a Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

1 0

Change in coreboot[master]: cpu/intel/turbo: Add option to disable turbo
by Subrata Banik (Code Review) 12 May '17

12 May '17

Subrata Banik has uploaded a new change for review. ( https://review.coreboot.org/19674 ) Change subject: cpu/intel/turbo: Add option to disable turbo ...................................................................... cpu/intel/turbo: Add option to disable turbo disable_turbo function use to disable turbo mode on each processor by settings MSR 0x1A0 bit 38. This option will help to perform some quick test without enabling turbo mode. Change-Id: If3e387e16e9fa6f63cb0ffff6ab2759b447e7c5c Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/cpu/intel/turbo/turbo.c M src/include/cpu/intel/turbo.h 2 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/19674/1 diff --git a/src/cpu/intel/turbo/turbo.c b/src/cpu/intel/turbo/turbo.c index ac66273..3fae3f0 100644 --- a/src/cpu/intel/turbo/turbo.c +++ b/src/cpu/intel/turbo/turbo.c @@ -106,3 +106,20 @@ printk(BIOS_INFO, "Turbo has been enabled\n"); } } + +/* + * Try to disable Turbo mode. + */ +void disable_turbo(void) +{ + msr_t msr; + + /* Set Turbo Disable bit in Misc Enables */ + msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr.hi |= H_MISC_DISABLE_TURBO; + wrmsr(MSR_IA32_MISC_ENABLES, msr); + + /* Update cached turbo state */ + set_global_turbo_state(TURBO_UNAVAILABLE); + printk(BIOS_INFO, "Turbo has been disabled\n"); +} diff --git a/src/include/cpu/intel/turbo.h b/src/include/cpu/intel/turbo.h index 6626cb1..58f4831 100644 --- a/src/include/cpu/intel/turbo.h +++ b/src/include/cpu/intel/turbo.h @@ -39,4 +39,7 @@ /* Enable turbo */ void enable_turbo(void); +/* Disable turbo */ +void disable_turbo(void); + #endif -- To view, visit https://review.coreboot.org/19674 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: If3e387e16e9fa6f63cb0ffff6ab2759b447e7c5c Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

1 0

Change in coreboot[master]: soc/intel/common/block:[WIP] Add GPIO common code
by build bot (Jenkins) (Code Review) 12 May '17

12 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18917 ) Change subject: soc/intel/common/block:[WIP] Add GPIO common code ...................................................................... Patch Set 21: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53573/ : SUCCESS -- To view, visit https://review.coreboot.org/18917 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I3a1d56df46668bfb08206ca4a99202db5cd1da7c Gerrit-PatchSet: 21 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brenton Dong <brenton.m.dong(a)intel.com> Gerrit-Reviewer: Dhaval Sharma <dhaval.v.sharma(a)intel.com> Gerrit-Reviewer: Divya Chellappa <divya.chellappa(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Han Lim Ng <nhlhanlim93(a)gmail.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Marc Herbert <marc.herbert(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: sowmya v <sowmyav235(a)gmail.com> Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/common/block:[WIP] Add GPIO common code
by Hannah Williams (Code Review) 12 May '17

12 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/18917 to look at the new patch set (#21). Change subject: soc/intel/common/block:[WIP] Add GPIO common code ...................................................................... soc/intel/common/block:[WIP] Add GPIO common code Here are some differences between APL and SKL GPIO registers DW0: PMODE: SKL[11:10] and APL[12:10] RXTXENCFG: APL[21:20] and RSVD in SKL PREGFRXSEL: APL[24] and RSVD in SKL DW1: SKL only has INTSEL and TERM whereas APL and GLK share same bit definitions for rest of the bits that are reserved in SKL EVMAP and EVOUTEN are not there on SKL DW1_PAD_TOL has been used only in SKL Change-Id: I3a1d56df46668bfb08206ca4a99202db5cd1da7c Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- A src/soc/intel/common/block/gpio/Kconfig A src/soc/intel/common/block/gpio/Makefile.inc A src/soc/intel/common/block/gpio/gpio.c A src/soc/intel/common/block/include/intelblocks/gpio.h A src/soc/intel/common/block/include/intelblocks/gpio_defs.h 5 files changed, 842 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/18917/21 -- To view, visit https://review.coreboot.org/18917 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I3a1d56df46668bfb08206ca4a99202db5cd1da7c Gerrit-PatchSet: 21 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brenton Dong <brenton.m.dong(a)intel.com> Gerrit-Reviewer: Dhaval Sharma <dhaval.v.sharma(a)intel.com> Gerrit-Reviewer: Divya Chellappa <divya.chellappa(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Han Lim Ng <nhlhanlim93(a)gmail.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Marc Herbert <marc.herbert(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: sowmya v <sowmyav235(a)gmail.com>

1 0

Change in coreboot[master]: toolchain.inc: Use -Wstack-usage only on gcc
by Edward O'Callaghan (Code Review) 12 May '17

12 May '17

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/19657 ) Change subject: toolchain.inc: Use -Wstack-usage only on gcc ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/19657 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I2c22171dedc77df24e739ec26335010f0f443963 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

1 0

Change in coreboot[master]: intel/common: drop duplicate initializer
by Edward O'Callaghan (Code Review) 12 May '17

12 May '17

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/19656 ) Change subject: intel/common: drop duplicate initializer ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/19656 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I99d0bd7d9b897a10edce35316e095e0223522c54 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/skylake: Use Intel PCIe common code
by build bot (Jenkins) (Code Review) 12 May '17

12 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19666 ) Change subject: soc/intel/skylake: Use Intel PCIe common code ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9365/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/53572/ : SUCCESS -- To view, visit https://review.coreboot.org/19666 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ia9fa22c30fffb1907320667ac37f55db9f3cb7b3 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/skylake: Use Intel PCIe common code
by Aamir Bohra (Code Review) 12 May '17

12 May '17

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/19666 ) Change subject: soc/intel/skylake: Use Intel PCIe common code ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/19666/1/src/soc/intel/skylake/Kconfig File src/soc/intel/skylake/Kconfig: PS1, Line 58: select SOC_INTEL_COMMON_BLOCK_PCR > order? Done -- To view, visit https://review.coreboot.org/19666 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ia9fa22c30fffb1907320667ac37f55db9f3cb7b3 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

1 0

Change in coreboot[master]: soc/intel/skylake: Use Intel PCIe common code
by Aamir Bohra (Code Review) 12 May '17

12 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19666 to look at the new patch set (#3). Change subject: soc/intel/skylake: Use Intel PCIe common code ...................................................................... soc/intel/skylake: Use Intel PCIe common code Change-Id: Ia9fa22c30fffb1907320667ac37f55db9f3cb7b3 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/Makefile.inc D src/soc/intel/skylake/pcie.c 3 files changed, 1 insertion(+), 113 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/19666/3 -- To view, visit https://review.coreboot.org/19666 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ia9fa22c30fffb1907320667ac37f55db9f3cb7b3 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: rockchip/rk3399: Add MIPI driver
by build bot (Jenkins) (Code Review) 12 May '17

12 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19477 ) Change subject: rockchip/rk3399: Add MIPI driver ...................................................................... Patch Set 7: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9364/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/53571/ : SUCCESS -- To view, visit https://review.coreboot.org/19477 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I02475eefb187c619c614b1cd20e97074bc8d917f Gerrit-PatchSet: 7 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: nickey.yang(a)rock-chips.com Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sean Paul <seanpaul(a)chromium.org> Gerrit-Reviewer: Shunqian Zheng <zhengsq(a)rock-chips.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nickey.yang(a)rock-chips.com Gerrit-HasComments: No

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit May 2017