coreboot-gerrit May 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/common: Add Intel PCIe common code
by build bot (Jenkins) (Code Review) 12 May '17

12 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19665 ) Change subject: soc/intel/common: Add Intel PCIe common code ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9373/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/53581/ : SUCCESS -- To view, visit https://review.coreboot.org/19665 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I0c374317a3fe0be0bb1c5d9b16fcbc5cad83ca42 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Use Intel PCIe common code
by build bot (Jenkins) (Code Review) 12 May '17

12 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19666 ) Change subject: soc/intel/skylake: Use Intel PCIe common code ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9374/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/53582/ : SUCCESS -- To view, visit https://review.coreboot.org/19666 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ia9fa22c30fffb1907320667ac37f55db9f3cb7b3 Gerrit-PatchSet: 5 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Use Intel PCIe common code
by Aamir Bohra (Code Review) 12 May '17

12 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19666 to look at the new patch set (#5). Change subject: soc/intel/skylake: Use Intel PCIe common code ...................................................................... soc/intel/skylake: Use Intel PCIe common code Change-Id: Ia9fa22c30fffb1907320667ac37f55db9f3cb7b3 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/Makefile.inc D src/soc/intel/skylake/pcie.c 3 files changed, 13 insertions(+), 113 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/19666/5 -- To view, visit https://review.coreboot.org/19666 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ia9fa22c30fffb1907320667ac37f55db9f3cb7b3 Gerrit-PatchSet: 5 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/common: Add Intel PCIe common code
by Aamir Bohra (Code Review) 12 May '17

12 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19665 to look at the new patch set (#3). Change subject: soc/intel/common: Add Intel PCIe common code ...................................................................... soc/intel/common: Add Intel PCIe common code Change-Id: I0c374317a3fe0be0bb1c5d9b16fcbc5cad83ca42 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- A src/soc/intel/common/block/pcie/Kconfig A src/soc/intel/common/block/pcie/Makefile.inc A src/soc/intel/common/block/pcie/pcie.c 3 files changed, 158 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/19665/3 -- To view, visit https://review.coreboot.org/19665 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I0c374317a3fe0be0bb1c5d9b16fcbc5cad83ca42 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/skylake: Use Intel PCIe common code
by build bot (Jenkins) (Code Review) 12 May '17

12 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19666 ) Change subject: soc/intel/skylake: Use Intel PCIe common code ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9372/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/53580/ : SUCCESS -- To view, visit https://review.coreboot.org/19666 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ia9fa22c30fffb1907320667ac37f55db9f3cb7b3 Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common: Add Intel PCIe common code
by build bot (Jenkins) (Code Review) 12 May '17

12 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19665 ) Change subject: soc/intel/common: Add Intel PCIe common code ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9371/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/53579/ : SUCCESS -- To view, visit https://review.coreboot.org/19665 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I0c374317a3fe0be0bb1c5d9b16fcbc5cad83ca42 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common: Add Intel PCIe common code
by Aamir Bohra (Code Review) 12 May '17

12 May '17

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/19665 ) Change subject: soc/intel/common: Add Intel PCIe common code ...................................................................... Patch Set 2: (4 comments) https://review.coreboot.org/#/c/19665/1/src/soc/intel/common/block/pcie/pci… File src/soc/intel/common/block/pcie/pcie.c: PS1, Line 35: > can you use macro, i guess this is bit definition Done.Revised to use macro for value representing cache line size. PS1, Line 40: date_config16(d > why not use kconfig option for more debug pcie Done PS1, Line 61: > is that fix for all socs Yes,for existing SOCs.Revised implementation and moved it to soc/Kconfig to provide provision to change,if it changes for upcoming SOCs. PS1, Line 73: .read_resources > remove if not needed Done -- To view, visit https://review.coreboot.org/19665 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I0c374317a3fe0be0bb1c5d9b16fcbc5cad83ca42 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/common: Add Intel PCIe common code
by Aamir Bohra (Code Review) 12 May '17

12 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19665 to look at the new patch set (#2). Change subject: soc/intel/common: Add Intel PCIe common code ...................................................................... soc/intel/common: Add Intel PCIe common code Change-Id: I0c374317a3fe0be0bb1c5d9b16fcbc5cad83ca42 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- A src/soc/intel/common/block/pcie/Kconfig A src/soc/intel/common/block/pcie/Makefile.inc A src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/skylake/Kconfig 4 files changed, 169 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/19665/2 -- To view, visit https://review.coreboot.org/19665 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I0c374317a3fe0be0bb1c5d9b16fcbc5cad83ca42 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: nb/intel/gm45: Add romstage timestamps
by build bot (Jenkins) (Code Review) 12 May '17

12 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19678 ) Change subject: nb/intel/gm45: Add romstage timestamps ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9370/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/53578/ : SUCCESS -- To view, visit https://review.coreboot.org/19678 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I558e6c63caf95ec5279ec5a866b54fb199116469 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/gm45: Add romstage timestamps
by Arthur Heymans (Code Review) 12 May '17

12 May '17

Arthur Heymans has uploaded a new change for review. ( https://review.coreboot.org/19678 ) Change subject: nb/intel/gm45: Add romstage timestamps ...................................................................... nb/intel/gm45: Add romstage timestamps Change-Id: I558e6c63caf95ec5279ec5a866b54fb199116469 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/t400/romstage.c M src/mainboard/lenovo/x200/romstage.c M src/mainboard/roda/rk9/romstage.c M src/northbridge/intel/gm45/raminit.c 4 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/19678/1 diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index 31a80a4..1a5c17c 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -31,6 +31,7 @@ #include <console/console.h> #include <southbridge/intel/i82801ix/i82801ix.h> #include <northbridge/intel/gm45/gm45.h> +#include <timestamp.h> #include "dock.h" #include "gpio.h" @@ -60,6 +61,9 @@ int cbmem_initted; u16 reg16; + timestamp_init(timestamp_get()); + timestamp_add_now(TS_START_ROMSTAGE); + /* basic northbridge setup, including MMCONF BAR */ gm45_early_init(); diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c index 49c5528..02f7116 100644 --- a/src/mainboard/lenovo/x200/romstage.c +++ b/src/mainboard/lenovo/x200/romstage.c @@ -32,6 +32,7 @@ #include <southbridge/intel/i82801ix/i82801ix.h> #include <northbridge/intel/gm45/gm45.h> #include "gpio.h" +#include <timestamp.h> #define LPC_DEV PCI_DEV(0, 0x1f, 0) #define MCH_DEV PCI_DEV(0, 0, 0) @@ -58,6 +59,9 @@ int cbmem_initted; u16 reg16; + timestamp_init(timestamp_get()); + timestamp_add_now(TS_START_ROMSTAGE); + /* basic northbridge setup, including MMCONF BAR */ gm45_early_init(); diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index 720f628..9a8e34b 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -32,6 +32,7 @@ #include <southbridge/intel/i82801ix/i82801ix.h> #include <northbridge/intel/gm45/gm45.h> #include <superio/smsc/lpc47n227/lpc47n227.h> +#include <timestamp.h> #define LPC_DEV PCI_DEV(0, 0x1f, 0) #define SERIAL_DEV PNP_DEV(0x2e, LPC47N227_SP1) @@ -124,6 +125,9 @@ int cbmem_initted; u16 reg16; + timestamp_init(timestamp_get()); + timestamp_add_now(TS_START_ROMSTAGE); + /* basic northbridge setup, including MMCONF BAR */ gm45_early_init(); diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 30e9297..d2da3b0 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -25,6 +25,7 @@ #include <console/console.h> #include <lib.h> #include <delay.h> +#include <timestamp.h> #include "gm45.h" #include "chip.h" @@ -1713,6 +1714,7 @@ int ch; u8 reg8; + timestamp_add_now(TS_BEFORE_INITRAM); /* Wait for some bit, maybe TXT clear. */ if (sysinfo->txt_enabled) { @@ -1825,4 +1827,6 @@ raminit_thermal(sysinfo); init_igd(sysinfo); + + timestamp_add_now(TS_AFTER_INITRAM); } -- To view, visit https://review.coreboot.org/19678 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I558e6c63caf95ec5279ec5a866b54fb199116469 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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coreboot-gerrit May 2017