coreboot-gerrit May 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: qemu/vexpress-a9: Discover RAM size.
by Arthur Heymans (Code Review) 12 May '17

12 May '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/13754 ) Change subject: qemu/vexpress-a9: Discover RAM size. ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/#/c/13754/5/src/mainboard/emulation/qemu-armv7/… File src/mainboard/emulation/qemu-armv7/mainboard.c: PS5, Line 28: while (1); #include <halt.h> and halt(); ? -- To view, visit https://review.coreboot.org/13754 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ib411f0a068bd247a9e0cd0a59689a3896921483e Gerrit-PatchSet: 5 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: vexpress: add gfx init
by Arthur Heymans (Code Review) 12 May '17

12 May '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/13749 ) Change subject: vexpress: add gfx init ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/13749 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I0eff29b74d7df331dcbf2c25799eaae4911e54fc Gerrit-PatchSet: 7 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: rockchip/rk3399: Add MIPI driver
by Anonymous Coward (Code Review) 12 May '17

12 May '17

nickey.yang(a)rock-chips.com has posted comments on this change. ( https://review.coreboot.org/19477 ) Change subject: rockchip/rk3399: Add MIPI driver ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/#/c/19477/5/src/soc/rockchip/rk3399/mipi.c File src/soc/rockchip/rk3399/mipi.c: Line 432: return; > So this is a panel-dependent value? Isn't there anything in the datasheet a Done -- To view, visit https://review.coreboot.org/19477 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I02475eefb187c619c614b1cd20e97074bc8d917f Gerrit-PatchSet: 7 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: nickey.yang(a)rock-chips.com Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sean Paul <seanpaul(a)chromium.org> Gerrit-Reviewer: Shunqian Zheng <zhengsq(a)rock-chips.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nickey.yang(a)rock-chips.com Gerrit-HasComments: Yes

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Change in coreboot[master]: sb/intel/lynxpoint: Use reset defaults PIRQ routing
by Arthur Heymans (Code Review) 12 May '17

12 May '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/19677 ) Change subject: sb/intel/lynxpoint: Use reset defaults PIRQ routing ...................................................................... Patch Set 1: Some things are not documented so I made some sane assumptions. Maybe generating it in C code based on devices found is a cool idea... -- To view, visit https://review.coreboot.org/19677 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I4e5ecfddd23264580784a33b0f87d66011529e77 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: sb/intel/lynxpoint: Use reset defaults PIRQ routing
by build bot (Jenkins) (Code Review) 12 May '17

12 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19677 ) Change subject: sb/intel/lynxpoint: Use reset defaults PIRQ routing ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9369/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/53577/ : SUCCESS -- To view, visit https://review.coreboot.org/19677 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I4e5ecfddd23264580784a33b0f87d66011529e77 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: sb/intel/lynxpoint: Use reset defaults PIRQ routing
by Arthur Heymans (Code Review) 12 May '17

12 May '17

Arthur Heymans has uploaded a new change for review. ( https://review.coreboot.org/19677 ) Change subject: sb/intel/lynxpoint: Use reset defaults PIRQ routing ...................................................................... sb/intel/lynxpoint: Use reset defaults PIRQ routing This makes it possible to use common code ACPI. Change-Id: I4e5ecfddd23264580784a33b0f87d66011529e77 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- D src/mainboard/google/beltino/acpi/haswell_pci_irqs.asl M src/mainboard/google/beltino/romstage.c D src/mainboard/google/slippy/acpi/haswell_pci_irqs.asl M src/mainboard/google/slippy/variants/falco/romstage.c M src/mainboard/google/slippy/variants/leon/romstage.c M src/mainboard/google/slippy/variants/peppy/romstage.c M src/mainboard/google/slippy/variants/wolf/romstage.c D src/mainboard/intel/baskingridge/acpi/haswell_pci_irqs.asl M src/mainboard/intel/baskingridge/romstage.c M src/northbridge/intel/haswell/acpi/hostbridge.asl A src/southbridge/intel/lynxpoint/acpi/default_pci_irqs.asl M src/southbridge/intel/lynxpoint/acpi/pch.asl 12 files changed, 95 insertions(+), 429 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/19677/1 diff --git a/src/mainboard/google/beltino/acpi/haswell_pci_irqs.asl b/src/mainboard/google/beltino/acpi/haswell_pci_irqs.asl deleted file mode 100644 index 68ea474..0000000 --- a/src/mainboard/google/beltino/acpi/haswell_pci_irqs.asl +++ /dev/null @@ -1,82 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for Haswell */ - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // Mini-HD Audio 0:3.0 - Package() { 0x0003ffff, 0, 0, 16 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 22 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 16 }, - Package() { 0x001cffff, 1, 0, 17 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - // EHCI 0:1d.0 - Package() { 0x001dffff, 0, 0, 19 }, - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, 0, 18 }, - // LPC devices 0:1f.0 - Package() { 0x001fffff, 0, 0, 22 }, - Package() { 0x001fffff, 1, 0, 18 }, - Package() { 0x001fffff, 2, 0, 17 }, - Package() { 0x001fffff, 3, 0, 16 }, - // Serial IO 0:15.0 - Package() { 0x0015ffff, 0, 0, 20 }, - Package() { 0x0015ffff, 1, 0, 21 }, - Package() { 0x0015ffff, 2, 0, 21 }, - Package() { 0x0015ffff, 3, 0, 21 }, - // SDIO 0:17.0 - Package() { 0x0017ffff, 0, 0, 23 }, - }) - } Else { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // Mini-HD Audio 0:3.0 - Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - // EHCI 0:1d.0 - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, - // Serial IO 0:15.0 - Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, - Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 }, - // SDIO 0:17.0 - Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - }) - } -} diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index 2ddb9b1..bd42a12 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -30,39 +30,6 @@ #include "onboard.h" const struct rcba_config_instruction rcba_config[] = { - - /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P1IP PCIE INTA -> PIRQA - * D29IP_E1P EHCI INTA -> PIRQD - * D20IP_XHCI XHCI INTA -> PIRQC (MSI) - * D31IP_SIP SATA INTA -> PIRQF (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQG - * D31IP_TTIP THRT INTC -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQG (MSI) - */ - - /* Device interrupt pin register (board specific) */ - RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), - RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)), - RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | - (INTB << D28IP_P4IP)), - RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)), - RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)), - RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)), - RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)), - - /* Device interrupt route registers */ - RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */ - RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */ - RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */ - RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */ - RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */ - RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */ - RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */ - RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */ - /* Disable unused devices (board specific) */ RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), diff --git a/src/mainboard/google/slippy/acpi/haswell_pci_irqs.asl b/src/mainboard/google/slippy/acpi/haswell_pci_irqs.asl deleted file mode 100644 index 68ea474..0000000 --- a/src/mainboard/google/slippy/acpi/haswell_pci_irqs.asl +++ /dev/null @@ -1,82 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for Haswell */ - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // Mini-HD Audio 0:3.0 - Package() { 0x0003ffff, 0, 0, 16 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 22 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 16 }, - Package() { 0x001cffff, 1, 0, 17 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - // EHCI 0:1d.0 - Package() { 0x001dffff, 0, 0, 19 }, - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, 0, 18 }, - // LPC devices 0:1f.0 - Package() { 0x001fffff, 0, 0, 22 }, - Package() { 0x001fffff, 1, 0, 18 }, - Package() { 0x001fffff, 2, 0, 17 }, - Package() { 0x001fffff, 3, 0, 16 }, - // Serial IO 0:15.0 - Package() { 0x0015ffff, 0, 0, 20 }, - Package() { 0x0015ffff, 1, 0, 21 }, - Package() { 0x0015ffff, 2, 0, 21 }, - Package() { 0x0015ffff, 3, 0, 21 }, - // SDIO 0:17.0 - Package() { 0x0017ffff, 0, 0, 23 }, - }) - } Else { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // Mini-HD Audio 0:3.0 - Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - // EHCI 0:1d.0 - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, - // Serial IO 0:15.0 - Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, - Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 }, - // SDIO 0:17.0 - Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - }) - } -} diff --git a/src/mainboard/google/slippy/variants/falco/romstage.c b/src/mainboard/google/slippy/variants/falco/romstage.c index 8254bc2..17cd846 100644 --- a/src/mainboard/google/slippy/variants/falco/romstage.c +++ b/src/mainboard/google/slippy/variants/falco/romstage.c @@ -28,39 +28,6 @@ #include "../../variant.h" const struct rcba_config_instruction rcba_config[] = { - - /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P1IP PCIE INTA -> PIRQA - * D29IP_E1P EHCI INTA -> PIRQD - * D20IP_XHCI XHCI INTA -> PIRQC (MSI) - * D31IP_SIP SATA INTA -> PIRQF (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQG - * D31IP_TTIP THRT INTC -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQG (MSI) - */ - - /* Device interrupt pin register (board specific) */ - RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), - RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)), - RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | - (INTB << D28IP_P4IP)), - RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)), - RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)), - RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)), - RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)), - - /* Device interrupt route registers */ - RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */ - RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */ - RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */ - RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */ - RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */ - RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */ - RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */ - RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */ - /* Disable unused devices (board specific) */ RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c index c9cf07b..66f0e46 100644 --- a/src/mainboard/google/slippy/variants/leon/romstage.c +++ b/src/mainboard/google/slippy/variants/leon/romstage.c @@ -28,39 +28,6 @@ #include "../../variant.h" const struct rcba_config_instruction rcba_config[] = { - - /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P1IP PCIE INTA -> PIRQA - * D29IP_E1P EHCI INTA -> PIRQD - * D20IP_XHCI XHCI INTA -> PIRQC (MSI) - * D31IP_SIP SATA INTA -> PIRQF (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQG - * D31IP_TTIP THRT INTC -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQG (MSI) - */ - - /* Device interrupt pin register (board specific) */ - RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), - RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)), - RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | - (INTB << D28IP_P4IP)), - RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)), - RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)), - RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)), - RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)), - - /* Device interrupt route registers */ - RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */ - RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */ - RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */ - RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */ - RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */ - RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */ - RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */ - RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */ - /* Disable unused devices (board specific) */ RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c index 4a39101..859ce9b 100644 --- a/src/mainboard/google/slippy/variants/peppy/romstage.c +++ b/src/mainboard/google/slippy/variants/peppy/romstage.c @@ -31,39 +31,6 @@ #include "../../variant.h" const struct rcba_config_instruction rcba_config[] = { - - /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P1IP PCIE INTA -> PIRQA - * D29IP_E1P EHCI INTA -> PIRQD - * D20IP_XHCI XHCI INTA -> PIRQC (MSI) - * D31IP_SIP SATA INTA -> PIRQF (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQG - * D31IP_TTIP THRT INTC -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQG (MSI) - */ - - /* Device interrupt pin register (board specific) */ - RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), - RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)), - RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | - (INTB << D28IP_P4IP)), - RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)), - RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)), - RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)), - RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)), - - /* Device interrupt route registers */ - RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */ - RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */ - RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */ - RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */ - RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */ - RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */ - RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */ - RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */ - /* Disable unused devices (board specific) */ RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c index 4bdde31..7e98d83 100644 --- a/src/mainboard/google/slippy/variants/wolf/romstage.c +++ b/src/mainboard/google/slippy/variants/wolf/romstage.c @@ -30,39 +30,6 @@ #include "../../variant.h" const struct rcba_config_instruction rcba_config[] = { - - /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P1IP PCIE INTA -> PIRQA - * D29IP_E1P EHCI INTA -> PIRQD - * D20IP_XHCI XHCI INTA -> PIRQC (MSI) - * D31IP_SIP SATA INTA -> PIRQF (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQG - * D31IP_TTIP THRT INTC -> PIRQA - * D27IP_ZIP HDA INTA -> PIRQG (MSI) - */ - - /* Device interrupt pin register (board specific) */ - RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), - RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)), - RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | - (INTB << D28IP_P4IP)), - RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)), - RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)), - RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)), - RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)), - - /* Device interrupt route registers */ - RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */ - RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */ - RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */ - RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */ - RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */ - RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */ - RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */ - RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */ - /* Disable unused devices (board specific) */ RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), diff --git a/src/mainboard/intel/baskingridge/acpi/haswell_pci_irqs.asl b/src/mainboard/intel/baskingridge/acpi/haswell_pci_irqs.asl deleted file mode 100644 index 3e841e0..0000000 --- a/src/mainboard/intel/baskingridge/acpi/haswell_pci_irqs.asl +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for IvyBridge */ - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 22 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 17 }, - Package() { 0x001cffff, 1, 0, 18 }, - Package() { 0x001cffff, 2, 0, 19 }, - Package() { 0x001cffff, 3, 0, 20 }, - // EHCI #1 0:1d.0 - Package() { 0x001dffff, 0, 0, 19 }, - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, 0, 20 }, - // LPC devices 0:1f.0 - Package() { 0x001fffff, 0, 0, 21 }, - Package() { 0x001fffff, 1, 0, 22 }, - Package() { 0x001fffff, 2, 0, 23 }, - Package() { 0x001fffff, 3, 0, 16 }, - }) - } Else { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 }, - // EHCI #1 0:1d.0 - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, - }) - } -} diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index 11e7444..6a7a2c7 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -24,39 +24,6 @@ #include "gpio.h" const struct rcba_config_instruction rcba_config[] = { - /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P1IP WLAN INTA -> PIRQB - * D28IP_P4IP ETH0 INTB -> PIRQC - * D29IP_E1P EHCI1 INTA -> PIRQD - * D26IP_E2P EHCI2 INTA -> PIRQE - * D31IP_SIP SATA INTA -> PIRQF (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQG - * D31IP_TTIP THRT INTC -> PIRQH - * D27IP_ZIP HDA INTA -> PIRQG (MSI) - */ - - /* Device interrupt pin register (board specific) */ - RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), - RCBA_SET_REG_32(D30IP, (NOINT << D30IP_PIP)), - RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)), - RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | - (INTB << D28IP_P4IP)), - RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)), - RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)), - RCBA_SET_REG_32(D25IP, (NOINT << D25IP_LIP)), - RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)), - - /* Device interrupt route registers */ - RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQF, PIRQG, PIRQH, PIRQA)), - RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG)), - RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE)), - RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQH, PIRQA, PIRQB)), - RCBA_SET_REG_32(D26IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), - RCBA_SET_REG_32(D25IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - /* Disable unused devices (board specific) */ RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 2565851..1ebdf28 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -455,6 +455,3 @@ Return (MCRS) } - -/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */ -#include "acpi/haswell_pci_irqs.asl" diff --git a/src/southbridge/intel/lynxpoint/acpi/default_pci_irqs.asl b/src/southbridge/intel/lynxpoint/acpi/default_pci_irqs.asl new file mode 100644 index 0000000..c416727 --- /dev/null +++ b/src/southbridge/intel/lynxpoint/acpi/default_pci_irqs.asl @@ -0,0 +1,92 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* PIRQ routing based on default DxxIP and DxxIR */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 }, + // XHCI 0:14.0 + Package() { 0x0014ffff, 0, 0, 16 }, + // Serial IO (Not in datasheet) 0:15.0 + Package() { 0x0015ffff, 0, 0, 16 }, + Package() { 0x0015ffff, 1, 0, 17 }, + Package() { 0x0015ffff, 2, 0, 18 }, + Package() { 0x0015ffff, 3, 0, 19 }, + // MEI 0:16.x + Package() { 0x0016ffff, 0, 0, 16 }, /* PINA: MEI #1 */ + Package() { 0x0016ffff, 1, 0, 17 }, /* PINB: MEI #2 */ + Package() { 0x0016ffff, 2, 0, 18 }, /* PINB: IDE-R */ + Package() { 0x0016ffff, 3, 0, 19 }, /* PIN: Keyboard text */ + // SDIO (Not in datasheet) 0:17.0 + Package() { 0x0017ffff, 0, 0, 16 }, + // GBE LAN 0:19.0 + Package() { 0x0019ffff, 0, 0, 16 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, 0, 16 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 16 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 16 }, /* PINA: PCIEe #1, #5 */ + Package() { 0x001cffff, 1, 0, 17 }, /* PINB: PCIe #2, #6 */ + Package() { 0x001cffff, 2, 0, 18 }, /* PINC: PCIe: #3 */ + Package() { 0x001cffff, 3, 0, 19 }, /* PIND: PCIe: #4 */ + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, 0, 16 }, + // LPC devices 0:1f.0 + Package() { 0x001fffff, 1, 0, 17 }, /* PINB: Sata 2, Sata */ + Package() { 0x001fffff, 2, 0, 18 }, /* PINC: SMBUS */ + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // XHCI 0:14.0 + Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:15.0 + Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + // MEI 0:16.x + Package() { 0x0016ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0016ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0016ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0016ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + // SDIO 0:17.0 + Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // SDIO 0:19.0 + Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + }) + } +} diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index c30bfa4..e5094ec 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -77,6 +77,9 @@ } } +// Default PIRQ routing +#include "default_pci_irqs.asl" + // High Definition Audio (Azalia) 0:1b.0 #include "audio.asl" -- To view, visit https://review.coreboot.org/19677 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I4e5ecfddd23264580784a33b0f87d66011529e77 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

1 0

Change in coreboot[master]: soc/intel/skylake: C-state interrupt response time
by build bot (Jenkins) (Code Review) 12 May '17

12 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19675 ) Change subject: soc/intel/skylake: C-state interrupt response time ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9367/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/53575/ : SUCCESS -- To view, visit https://review.coreboot.org/19675 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I4f47502e1c212118d7cc89d4de60a1854072964a Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/skylake: Option to enable/disable EIST
by build bot (Jenkins) (Code Review) 12 May '17

12 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19676 ) Change subject: soc/intel/skylake: Option to enable/disable EIST ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9368/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/53576/ : SUCCESS -- To view, visit https://review.coreboot.org/19676 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I2b7374a8a04b596edcc88165b64980b7aa09e2a7 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: No

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Change in coreboot[master]: cpu/intel/turbo: Add option to disable turbo
by build bot (Jenkins) (Code Review) 12 May '17

12 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19674 ) Change subject: cpu/intel/turbo: Add option to disable turbo ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9366/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/53574/ : SUCCESS -- To view, visit https://review.coreboot.org/19674 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: If3e387e16e9fa6f63cb0ffff6ab2759b447e7c5c Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/skylake: Option to enable/disable EIST
by Subrata Banik (Code Review) 12 May '17

12 May '17

Subrata Banik has uploaded a new change for review. ( https://review.coreboot.org/19676 ) Change subject: soc/intel/skylake: Option to enable/disable EIST ...................................................................... soc/intel/skylake: Option to enable/disable EIST Set MSR 0x1A0 bit[16] based on EIST config option. Default HWP enabled on SKL hence disable EIST and ACPI P-state table. Change-Id: I2b7374a8a04b596edcc88165b64980b7aa09e2a7 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/chip_fsp20.c M src/soc/intel/skylake/cpu.c 4 files changed, 19 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/19676/1 diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index e8d0c16..64438bd 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -523,9 +523,10 @@ generate_c_state_entries(is_s0ix_enable, max_c_state); - /* Generate P-state tables */ - generate_p_state_entries(core_id, - cores_per_package); + if (config->eist_enable) + /* Generate P-state tables */ + generate_p_state_entries(core_id, + cores_per_package); acpigen_pop_len(); } diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index b474ca2..43c921e 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -459,6 +459,12 @@ /* Enable SGX feature */ u8 sgx_enable; + + /* Enable/Disable EIST + * 1b - Enabled + * 0b - Disabled + */ + u8 eist_enable; }; typedef struct soc_intel_skylake_config config_t; diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 2d9b864..8a7cb21 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -261,6 +261,9 @@ /* Enable PMC XRAM read */ tconfig->PchPmPmcReadDisable = config->PchPmPmcReadDisable; + /* Enable/Disable EIST */ + tconfig->Eist = config->eist_enable; + soc_irq_settings(params); } diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 38fe54c..588ffab 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -245,12 +245,17 @@ static void configure_misc(void) { + device_t dev = SA_DEV_ROOT; + config_t *conf = dev->chip_info; msr_t msr; msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 0); /* Fast String enable */ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + if (conf->eist_enable) + msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ + else + msr.lo &= ~(1 << 16); /* Enhanced SpeedStep Disable */ wrmsr(IA32_MISC_ENABLE, msr); /* Disable Thermal interrupts */ -- To view, visit https://review.coreboot.org/19676 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I2b7374a8a04b596edcc88165b64980b7aa09e2a7 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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coreboot-gerrit May 2017