coreboot-gerrit May 2017

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Change in coreboot[master]: soc/intel/common: Add Intel PCIe common code
by Aamir Bohra (Code Review) 12 May '17

12 May '17

Aamir Bohra has uploaded a new change for review. ( https://review.coreboot.org/19665 ) Change subject: soc/intel/common: Add Intel PCIe common code ...................................................................... soc/intel/common: Add Intel PCIe common code Change-Id: I0c374317a3fe0be0bb1c5d9b16fcbc5cad83ca42 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- A src/soc/intel/common/block/pcie/Kconfig A src/soc/intel/common/block/pcie/Makefile.inc A src/soc/intel/common/block/pcie/pcie.c 3 files changed, 147 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/19665/1 diff --git a/src/soc/intel/common/block/pcie/Kconfig b/src/soc/intel/common/block/pcie/Kconfig new file mode 100644 index 0000000..d494411 --- /dev/null +++ b/src/soc/intel/common/block/pcie/Kconfig @@ -0,0 +1,4 @@ +config SOC_INTEL_COMMON_BLOCK_PCIE + bool + help + Intel Processor common PCIE support diff --git a/src/soc/intel/common/block/pcie/Makefile.inc b/src/soc/intel/common/block/pcie/Makefile.inc new file mode 100644 index 0000000..ac311a7 --- /dev/null +++ b/src/soc/intel/common/block/pcie/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE) += pcie.c diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c new file mode 100644 index 0000000..e2fe169 --- /dev/null +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -0,0 +1,142 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/pci.h> +#include <device/pciexp.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> + +static void pch_pcie_init(struct device *dev) +{ + u16 reg16; + + printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n"); + + /* Enable SERR */ + pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_SERR); + + /* Enable Bus Master */ + pci_or_config32(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + + /* Set Cache Line Size to 0x10 */ + pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 0x10); + + /* disable parity error response, enable ISA */ + pci_update_config16(dev, PCI_BRIDGE_CONTROL, ~(1), 1<<2); + +#ifdef EVEN_MORE_DEBUG + printk(BIOS_SPEW, " MBL = 0x%08x\n", + pci_read_config32(dev, PCI_MEMORY_BASE)); + printk(BIOS_SPEW, " PMBL = 0x%08x\n", + pci_read_config32(dev, PCI_PREF_MEMORY_BASE)); + printk(BIOS_SPEW, " PMBU32 = 0x%08x\n", + pci_read_config32(dev, PCI_PREF_BASE_UPPER32)); + printk(BIOS_SPEW, " PMLU32 = 0x%08x\n", + pci_read_config32(dev, PCI_PREF_LIMIT_UPPER32)); +#endif + + /* Clear errors in status registers */ + reg16 = pci_read_config16(dev, PCI_STATUS); + pci_write_config16(dev, PCI_STATUS, reg16); + reg16 = pci_read_config16(dev, PCI_SEC_STATUS); + pci_write_config16(dev, PCI_SEC_STATUS, reg16); +} + +static void pcie_set_L1_ss_max_latency(device_t dev, unsigned int offset) +{ + /* Set max snoop and non-snoop latency for the SOC */ + pci_write_config32(dev, offset, 0x10031003); +} + +static struct pci_operations pcie_ops = { + .set_L1_ss_latency = pcie_set_L1_ss_max_latency, +}; + +static struct device_operations device_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = pch_pcie_init, + .enable = NULL, + .scan_bus = pciexp_scan_bridge, + .ops_pci = &pcie_ops, +}; + +static const unsigned short pcie_device_ids[] = { + PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1, + PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP2, + PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP3, + PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP4, + PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP5, + PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP6, + PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP7, + PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP8, + PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP9, + PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP10, + PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP11, + PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP12, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP1, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP2, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP3, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP4, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP5, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP6, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP7, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP8, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP9, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP10, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP11, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP12, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP13, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP14, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP15, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP16, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP17, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP18, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP19, + PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP20, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP1, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP2, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP3, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP4, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP5, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP6, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP7, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP8, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP9, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP10, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP11, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP12, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP13, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP14, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP15, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP16, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP17, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP18, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP19, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP20, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP21, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP22, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP23, + PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP24, + 0 +}; + +static const struct pci_driver pch_pcie __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pcie_device_ids, +}; -- To view, visit https://review.coreboot.org/19665 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I0c374317a3fe0be0bb1c5d9b16fcbc5cad83ca42 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: src/include/device: Add PCIe root ports device ids
by Aamir Bohra (Code Review) 12 May '17

12 May '17

Aamir Bohra has uploaded a new change for review. ( https://review.coreboot.org/19664 ) Change subject: src/include/device: Add PCIe root ports device ids ...................................................................... src/include/device: Add PCIe root ports device ids Change-Id: Ic2df7fb1e4a3d3c52561b949c4b359ea59824387 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/include/device/pci_ids.h 1 file changed, 60 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/19664/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index f243414..5a2e1b2 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2673,6 +2673,66 @@ #define PCI_DEVICE_ID_INTEL_KBP_LP_Y_PREMIUM 0x9d56 #define PCI_DEVICE_ID_INTEL_APL_LPC 0x5ae8 +/* Intel PCIE device ids */ +#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 0x9d10 +#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP2 0x9d11 +#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP3 0x9d12 +#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP4 0x9d13 +#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP5 0x9d14 +#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP6 0x9d15 +#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP7 0x9d16 +#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP8 0x9d17 +#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP9 0x9d18 +#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP10 0x9d19 +#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP11 0x9d1a +#define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP12 0x9d1b + +#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP1 0xa110 +#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP2 0xa111 +#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP3 0xa112 +#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP4 0xa113 +#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP5 0xa114 +#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP6 0xa115 +#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP7 0xa116 +#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP8 0xa117 +#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP9 0xa118 +#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP10 0xa119 +#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP11 0xa11a +#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP12 0xa11b +#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP13 0xa11c +#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP14 0xa11d +#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP15 0xa11e +#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP16 0xa11f +#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP17 0xa167 +#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP18 0xa168 +#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP19 0xa169 +#define PCI_DEVICE_ID_INTEL_SPT_H_PCIE_RP20 0xa16a + +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP1 0xa290 +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP2 0xa291 +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP3 0xa292 +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP4 0xa293 +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP5 0xa294 +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP6 0xa295 +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP7 0xa296 +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP8 0xa297 +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP9 0xa298 +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP10 0xa299 +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP11 0xa29a +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP12 0xa29b +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP13 0xa29c +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP14 0xa29d +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP15 0xa29e +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP16 0xa29f +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP17 0xa2e7 +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP18 0xa2e8 +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP19 0xa2e9 +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP20 0xa2ea +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP21 0xa2eb +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP22 0xa2ec +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP23 0xa2ed +#define PCI_DEVICE_ID_INTEL_KBP_H_PCIE_RP24 0xa2ee + /* Intel SATA device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_U_SATA 0x9d03 #define PCI_DEVICE_ID_INTEL_SPT_U_Y_PREMIUM_SATA 0x9d07 -- To view, visit https://review.coreboot.org/19664 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Ic2df7fb1e4a3d3c52561b949c4b359ea59824387 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: src/sb/bd82x6x: Use default DxxIP and DxxIR
by Arthur Heymans (Code Review) 12 May '17

12 May '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/19662 ) Change subject: src/sb/bd82x6x: Use default DxxIP and DxxIR ...................................................................... Patch Set 10: (3 comments) https://review.coreboot.org/#/c/19662/10/src/southbridge/intel/bd82x6x/acpi… File src/southbridge/intel/bd82x6x/acpi/default_irq_route.asl: PS10, Line 23: /* GFX PCIe INTA -> PIRQA (MSI) */ > I don't think these comments are still useful, do you? nope not useful. On the ich7 equivalent I added a comment to which function the INT is connected. might be good to do so here too. PS10, Line 26: ivy only > Actually, Panther Point only, no matter the CPU. makes sense Line 44: Package() { 0x001fffff, 1, 0, 17 }, /* D31IP_SMIP SMBUS INTB -> PIRQB */ > Did you check actual register values, my datasheet (7-series) is No sandy board here anymore (I tried to port a Dell for the fun of it but it died before I could complete the port). Actually not a bad idea and likely very generic. -- To view, visit https://review.coreboot.org/19662 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I7660c03dca0b7db34cf725488b6d6538fdfde62d Gerrit-PatchSet: 10 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: drivers/pc80/rtc: Rename mc146818rtc_early.c -> _romcc.c
by Raptor Engineering Automated Test Stand (Code Review) 12 May '17

12 May '17

Raptor Engineering Automated Test Stand has posted comments on this change. ( https://review.coreboot.org/19663 ) Change subject: drivers/pc80/rtc: Rename mc146818rtc_early.c -> _romcc.c ...................................................................... Patch Set 2: Verified+1 ASUS KFSN4-DRE: Boot and extended test successful. Boot log: https://testlab.coreboot.org/raptor/1494518154-0-19663,2.log.bz2 QEMU x86_64 Q35: Boot successful. Boot log: https://testlab.coreboot.org/raptor/1494518233-1-19663,2.log.bz2 ASUS KGPE-D16: Boot and extended test successful. Boot log: https://testlab.coreboot.org/raptor/1494518873-3-19663,2.log.bz2 -- To view, visit https://review.coreboot.org/19663 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I54ea08de034766c8140b320075d36d5e811582fa Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Gerrit-Reviewer: Timothy Pearson <tpearson(a)raptorengineering.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-Reviewer: lava.coreboot.org <lavacoreboot(a)gmail.com> Gerrit-HasComments: No

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Change in coreboot[master]: mainboard: Add ASRock G41C-GS
by Arthur Heymans (Code Review) 12 May '17

12 May '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/18993 ) Change subject: mainboard: Add ASRock G41C-GS ...................................................................... Patch Set 14: Let's just merge this one? I'll rebase PIRQ patches on top of it. -- To view, visit https://review.coreboot.org/18993 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I992ee07b742dfc59733ce0f3a9be202a530ec6cc Gerrit-PatchSet: 14 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: drivers/pc80/rtc: Rename mc146818rtc_early.c -> _romcc.c
by build bot (Jenkins) (Code Review) 12 May '17

12 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19663 ) Change subject: drivers/pc80/rtc: Rename mc146818rtc_early.c -> _romcc.c ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9355/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/53562/ : SUCCESS -- To view, visit https://review.coreboot.org/19663 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I54ea08de034766c8140b320075d36d5e811582fa Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: sb/intel/i82801gx: Consolidate interrupt routing
by build bot (Jenkins) (Code Review) 12 May '17

12 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19017 ) Change subject: sb/intel/i82801gx: Consolidate interrupt routing ...................................................................... Patch Set 11: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9354/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/53561/ : SUCCESS -- To view, visit https://review.coreboot.org/19017 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I46838d2249c6fefedf9e2c63ade0812d22e7d627 Gerrit-PatchSet: 11 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-HasComments: No

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Change in coreboot[master]: sb/intel/i82801gx: Consolidate interrupt routing
by Arthur Heymans (Code Review) 12 May '17

12 May '17

Hello Vladimir Serbinenko, Paul Menzel, build bot (Jenkins), coreboot org, I'd like you to reexamine a change. Please visit https://review.coreboot.org/19017 to look at the new patch set (#11). Change subject: sb/intel/i82801gx: Consolidate interrupt routing ...................................................................... sb/intel/i82801gx: Consolidate interrupt routing The current code tries to make routing per-board, presumably for optimizing IRQ balancing but instead fails at providing an error-free default. Rewrite in unified and simplified way at the cost of minor performance hit on very old OS. This uses the default DxxIP and DxxIR to set up PCI IRQ routing and sets ACPI accordingly. Change-Id: I46838d2249c6fefedf9e2c63ade0812d22e7d627 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/apple/macbook21/Kconfig D src/mainboard/apple/macbook21/acpi/i945_pci_irqs.asl M src/mainboard/apple/macbook21/devicetree.cb M src/mainboard/apple/macbook21/romstage.c M src/mainboard/asus/p5gc-mx/Kconfig M src/mainboard/asus/p5gc-mx/devicetree.cb M src/mainboard/getac/p470/Kconfig D src/mainboard/getac/p470/acpi/i945_pci_irqs.asl M src/mainboard/getac/p470/devicetree.cb M src/mainboard/getac/p470/romstage.c D src/mainboard/gigabyte/ga-945gcm-s2l/acpi/i945_pci_irqs.asl M src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c M src/mainboard/gigabyte/ga-g41m-es2l/Kconfig D src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl M src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c M src/mainboard/ibase/mb899/Kconfig D src/mainboard/ibase/mb899/acpi/i945_pci_irqs.asl M src/mainboard/ibase/mb899/devicetree.cb M src/mainboard/ibase/mb899/romstage.c M src/mainboard/intel/d510mo/Kconfig D src/mainboard/intel/d510mo/acpi/pineview_pci_irqs.asl M src/mainboard/intel/d510mo/devicetree.cb M src/mainboard/intel/d510mo/romstage.c M src/mainboard/intel/d945gclf/Kconfig D src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl M src/mainboard/intel/d945gclf/devicetree.cb M src/mainboard/intel/d945gclf/romstage.c M src/mainboard/kontron/986lcd-m/Kconfig D src/mainboard/kontron/986lcd-m/acpi/i945_pci_irqs.asl M src/mainboard/kontron/986lcd-m/devicetree.cb M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/lenovo/t60/Kconfig D src/mainboard/lenovo/t60/acpi/i945_pci_irqs.asl M src/mainboard/lenovo/t60/devicetree.cb M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/x60/Kconfig D src/mainboard/lenovo/x60/acpi/i945_pci_irqs.asl M src/mainboard/lenovo/x60/devicetree.cb M src/mainboard/lenovo/x60/romstage.c M src/mainboard/roda/rk886ex/Kconfig D src/mainboard/roda/rk886ex/acpi/i945_pci_irqs.asl M src/mainboard/roda/rk886ex/devicetree.cb M src/mainboard/roda/rk886ex/romstage.c M src/northbridge/intel/i945/acpi/hostbridge.asl M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/pineview/acpi/hostbridge.asl M src/northbridge/intel/pineview/early_init.c M src/northbridge/intel/x4x/acpi/hostbridge.asl M src/southbridge/intel/i82801gx/acpi/ich7.asl R src/southbridge/intel/i82801gx/acpi/irq.asl M src/southbridge/intel/i82801gx/chip.h M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801gx/lpc.c 55 files changed, 384 insertions(+), 1,249 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/19017/11 -- To view, visit https://review.coreboot.org/19017 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I46838d2249c6fefedf9e2c63ade0812d22e7d627 Gerrit-PatchSet: 11 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com>

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Change in coreboot[master]: util/autoport: Don't include default_irq_route.asl in DSDT d...
by build bot (Jenkins) (Code Review) 12 May '17

12 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19667 ) Change subject: util/autoport: Don't include default_irq_route.asl in DSDT directly ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9352/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/53559/ : SUCCESS -- To view, visit https://review.coreboot.org/19667 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I48c1d9c789713f8ca42f237b6551bc1701c01c21 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: src/sb/bd82x6x: Use default DxxIP and DxxIR
by build bot (Jenkins) (Code Review) 12 May '17

12 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19662 ) Change subject: src/sb/bd82x6x: Use default DxxIP and DxxIR ...................................................................... Patch Set 10: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9353/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/53560/ : SUCCESS -- To view, visit https://review.coreboot.org/19662 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I7660c03dca0b7db34cf725488b6d6538fdfde62d Gerrit-PatchSet: 10 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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coreboot-gerrit May 2017