Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/19662
to look at the new patch set (#10).
Change subject: src/sb/bd82x6x: Use default DxxIP and DxxIR
......................................................................
src/sb/bd82x6x: Use default DxxIP and DxxIR
The defaults only use PIRQ A, B, C and D for PCI devices which does
not conflict with PIRQ needed on some chromebooks needed for trackpad
and/or light sensor.
This also affects ibexpeak which uses the same code and has the same
defaults.
Change-Id: I7660c03dca0b7db34cf725488b6d6538fdfde62d
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/mainboard/apple/macbookair4_2/dsdt.asl
M src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl
M src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl
D src/mainboard/google/butterfly/acpi/sandybridge_pci_irqs.asl
M src/mainboard/google/butterfly/dsdt.asl
M src/mainboard/google/butterfly/romstage.c
D src/mainboard/google/link/acpi/ivybridge_pci_irqs.asl
D src/mainboard/google/link/acpi/sandybridge_pci_irqs.asl
M src/mainboard/google/link/dsdt.asl
M src/mainboard/google/link/romstage.c
D src/mainboard/google/parrot/acpi/ivybridge_pci_irqs.asl
D src/mainboard/google/parrot/acpi/sandybridge_pci_irqs.asl
M src/mainboard/google/parrot/dsdt.asl
M src/mainboard/google/parrot/romstage.c
D src/mainboard/google/stout/acpi/sandybridge_pci_irqs.asl
M src/mainboard/google/stout/dsdt.asl
M src/mainboard/google/stout/romstage.c
D src/mainboard/intel/emeraldlake2/acpi/ivybridge_pci_irqs.asl
M src/mainboard/intel/emeraldlake2/dsdt.asl
M src/mainboard/intel/emeraldlake2/romstage.c
M src/mainboard/kontron/ktqm77/dsdt.asl
M src/mainboard/lenovo/l520/dsdt.asl
M src/mainboard/lenovo/s230u/dsdt.asl
M src/mainboard/lenovo/t420/dsdt.asl
M src/mainboard/lenovo/t420s/dsdt.asl
M src/mainboard/lenovo/t430s/dsdt.asl
M src/mainboard/lenovo/t520/dsdt.asl
M src/mainboard/lenovo/t530/dsdt.asl
M src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl
M src/mainboard/lenovo/x201/dsdt.asl
M src/mainboard/lenovo/x201/romstage.c
M src/mainboard/lenovo/x220/dsdt.asl
M src/mainboard/lenovo/x230/dsdt.asl
M src/mainboard/packardbell/ms2290/dsdt.asl
M src/mainboard/packardbell/ms2290/romstage.c
M src/mainboard/roda/rv11/dsdt.asl
D src/mainboard/samsung/lumpy/acpi/sandybridge_pci_irqs.asl
M src/mainboard/samsung/lumpy/devicetree.cb
M src/mainboard/samsung/lumpy/dsdt.asl
M src/mainboard/samsung/lumpy/romstage.c
D src/mainboard/samsung/stumpy/acpi/sandybridge_pci_irqs.asl
M src/mainboard/samsung/stumpy/dsdt.asl
M src/mainboard/samsung/stumpy/romstage.c
M src/mainboard/sapphire/pureplatinumh61/dsdt.asl
M src/northbridge/intel/sandybridge/romstage.c
M src/southbridge/intel/bd82x6x/Makefile.inc
M src/southbridge/intel/bd82x6x/acpi/default_irq_route.asl
M src/southbridge/intel/bd82x6x/acpi/pch.asl
D src/southbridge/intel/bd82x6x/early_rcba.c
M src/southbridge/intel/ibexpeak/Makefile.inc
50 files changed, 42 insertions(+), 931 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/19662/10
--
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To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I7660c03dca0b7db34cf725488b6d6538fdfde62d
Gerrit-PatchSet: 10
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Hello Vladimir Serbinenko, Paul Menzel, build bot (Jenkins), coreboot org,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/19017
to look at the new patch set (#10).
Change subject: sb/intel/i82801gx: Consolidate interrupt routing
......................................................................
sb/intel/i82801gx: Consolidate interrupt routing
The current code tries to make routing per-board, presumably for optimizing
IRQ balancing but instead fails at providing an error-free default.
Rewrite in unified and simplified way at the cost of minor performance hit
on very old OS.
This uses the default DxxIP and DxxIR to set up PCI IRQ routing and
sets ACPI accordingly.
Change-Id: I46838d2249c6fefedf9e2c63ade0812d22e7d627
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/mainboard/apple/macbook21/Kconfig
D src/mainboard/apple/macbook21/acpi/i945_pci_irqs.asl
M src/mainboard/apple/macbook21/devicetree.cb
M src/mainboard/apple/macbook21/romstage.c
M src/mainboard/asus/p5gc-mx/Kconfig
M src/mainboard/asus/p5gc-mx/devicetree.cb
M src/mainboard/getac/p470/Kconfig
D src/mainboard/getac/p470/acpi/i945_pci_irqs.asl
M src/mainboard/getac/p470/devicetree.cb
M src/mainboard/getac/p470/romstage.c
D src/mainboard/gigabyte/ga-945gcm-s2l/acpi/i945_pci_irqs.asl
M src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb
M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
M src/mainboard/gigabyte/ga-g41m-es2l/Kconfig
D src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl
M src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb
M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
M src/mainboard/ibase/mb899/Kconfig
D src/mainboard/ibase/mb899/acpi/i945_pci_irqs.asl
M src/mainboard/ibase/mb899/devicetree.cb
M src/mainboard/ibase/mb899/romstage.c
M src/mainboard/intel/d510mo/Kconfig
D src/mainboard/intel/d510mo/acpi/pineview_pci_irqs.asl
M src/mainboard/intel/d510mo/devicetree.cb
M src/mainboard/intel/d510mo/romstage.c
M src/mainboard/intel/d945gclf/Kconfig
D src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl
M src/mainboard/intel/d945gclf/devicetree.cb
M src/mainboard/intel/d945gclf/romstage.c
M src/mainboard/kontron/986lcd-m/Kconfig
D src/mainboard/kontron/986lcd-m/acpi/i945_pci_irqs.asl
M src/mainboard/kontron/986lcd-m/devicetree.cb
M src/mainboard/kontron/986lcd-m/romstage.c
M src/mainboard/lenovo/t60/Kconfig
D src/mainboard/lenovo/t60/acpi/i945_pci_irqs.asl
M src/mainboard/lenovo/t60/devicetree.cb
M src/mainboard/lenovo/t60/romstage.c
M src/mainboard/lenovo/x60/Kconfig
D src/mainboard/lenovo/x60/acpi/i945_pci_irqs.asl
M src/mainboard/lenovo/x60/devicetree.cb
M src/mainboard/lenovo/x60/romstage.c
M src/mainboard/roda/rk886ex/Kconfig
D src/mainboard/roda/rk886ex/acpi/i945_pci_irqs.asl
M src/mainboard/roda/rk886ex/devicetree.cb
M src/mainboard/roda/rk886ex/romstage.c
M src/northbridge/intel/i945/acpi/hostbridge.asl
M src/northbridge/intel/i945/early_init.c
M src/northbridge/intel/pineview/acpi/hostbridge.asl
M src/northbridge/intel/pineview/early_init.c
M src/northbridge/intel/x4x/acpi/hostbridge.asl
M src/northbridge/intel/x4x/early_init.c
M src/southbridge/intel/i82801gx/acpi/ich7.asl
R src/southbridge/intel/i82801gx/acpi/irq.asl
M src/southbridge/intel/i82801gx/chip.h
M src/southbridge/intel/i82801gx/i82801gx.h
M src/southbridge/intel/i82801gx/lpc.c
56 files changed, 387 insertions(+), 1,249 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/19017/10
--
To view, visit https://review.coreboot.org/19017
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I46838d2249c6fefedf9e2c63ade0812d22e7d627
Gerrit-PatchSet: 10
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Vladimir Serbinenko <phcoder(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com>
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/19652 )
Change subject: nb/intel/gm45: Fix raminit with mixed raw card types
......................................................................
nb/intel/gm45: Fix raminit with mixed raw card types
`cardF[n]` should indicate whether the DIMM in channel n is of
raw card type F. However, `cardF[1]` was initialised with the
value meant for `cardF[0]`. This patch results in the correct
initialisation of `cardF`.
Tested on a Lenovo T400 containing two DIMMs: one of raw card
type F and the other of raw card type B. Before the patch, the
system would not boot. After the patch, the system boots with all
of the memory functional.
Change-Id: I7409df0b8c67d7efbdadae39dc718c8df7a92552
Signed-off-by: Tristan Corrick <tristancorrick86(a)gmail.com>
Reviewed-on: https://review.coreboot.org/19652
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz>
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
---
M src/northbridge/intel/gm45/raminit_receive_enable_calibration.c
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
Arthur Heymans: Looks good to me, but someone else must approve
Paul Menzel: Looks good to me, but someone else must approve
build bot (Jenkins): Verified
Nico Huber: Looks good to me, approved
diff --git a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c
index c5614e1..7d57a4e 100644
--- a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c
+++ b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c
@@ -211,7 +211,7 @@
const int cardF[] = {
dimms[0].card_type == 0xf,
- dimms[0].card_type == 0xf,
+ dimms[1].card_type == 0xf,
};
const unsigned int t_bound =
--
To view, visit https://review.coreboot.org/19652
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-MessageType: merged
Gerrit-Change-Id: I7409df0b8c67d7efbdadae39dc718c8df7a92552
Gerrit-PatchSet: 2
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Tristan Corrick <tristancorrick86(a)gmail.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/19651 )
Change subject: nb/intel/gm45: Fix some errors/warnings given by checkpatch
......................................................................
nb/intel/gm45: Fix some errors/warnings given by checkpatch
This results in raminit_receive_enable_calibration.c producing
no errors or warnings with checkpatch.
The issues fixed are:
ERROR: that open brace { should be on the previous line
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
Tested by compiling after making the changes.
Change-Id: I8d2f4f1fe2f17aa44c0a7090c178eee418defe78
Signed-off-by: Tristan Corrick <tristancorrick86(a)gmail.com>
Reviewed-on: https://review.coreboot.org/19651
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz>
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
---
M src/northbridge/intel/gm45/raminit_receive_enable_calibration.c
1 file changed, 7 insertions(+), 4 deletions(-)
Approvals:
Arthur Heymans: Looks good to me, approved
Paul Menzel: Looks good to me, but someone else must approve
build bot (Jenkins): Verified
Nico Huber: Looks good to me, approved
diff --git a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c
index 0d346bf..c5614e1 100644
--- a/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c
+++ b/src/northbridge/intel/gm45/raminit_receive_enable_calibration.c
@@ -209,11 +209,14 @@
/* F */{ { 0, 0 }, { 3, 3 }, { 6, 6 }, { 5, 5 } },
};
- const int cardF[] =
- { dimms[0].card_type == 0xf, dimms[0].card_type == 0xf };
- const unsigned t_bound =
+ const int cardF[] = {
+ dimms[0].card_type == 0xf,
+ dimms[0].card_type == 0xf,
+ };
+
+ const unsigned int t_bound =
(timings->mem_clock == MEM_CLOCK_1067MT) ? 9 : 12;
- const unsigned p_bound =
+ const unsigned int p_bound =
(timings->mem_clock == MEM_CLOCK_1067MT) ? 8 : 1;
rec_timing_t rec_timings[2][4] = {
--
To view, visit https://review.coreboot.org/19651
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-MessageType: merged
Gerrit-Change-Id: I8d2f4f1fe2f17aa44c0a7090c178eee418defe78
Gerrit-PatchSet: 2
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Tristan Corrick <tristancorrick86(a)gmail.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/19071 )
Change subject: util: Add tools for dumping and inserting KBC1126 firmware images.
......................................................................
util: Add tools for dumping and inserting KBC1126 firmware images.
Change-Id: Ic521b177b9602ff042312cccaaa89371db7c5855
Signed-off-by: Iru Cai <mytbk920423(a)gmail.com>
Reviewed-on: https://review.coreboot.org/19071
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M .gitignore
A util/kbc1126/README.md
A util/kbc1126/kbc1126_ec_dump.c
A util/kbc1126/kbc1126_ec_insert.c
A util/kbc1126/makefile
5 files changed, 305 insertions(+), 0 deletions(-)
Approvals:
Arthur Heymans: Looks good to me, approved
build bot (Jenkins): Verified
diff --git a/.gitignore b/.gitignore
index 2ecbb51..ed642a3 100644
--- a/.gitignore
+++ b/.gitignore
@@ -115,6 +115,8 @@
util/vgabios/testbios
util/viatool/viatool
util/autoport/autoport
+util/kbc1126/kbc1126_ec_dump
+util/kbc1126/kbc1126_ec_insert
documentation/*.aux
documentation/*.idx
diff --git a/util/kbc1126/README.md b/util/kbc1126/README.md
new file mode 100644
index 0000000..8f39069
--- /dev/null
+++ b/util/kbc1126/README.md
@@ -0,0 +1,59 @@
+KBC1126 firmware tools
+======================
+
+Many HP laptops use 8051-based SMSC KBC1098/KBC1126 as embedded
+controller. Two blobs can be found in the HP firmware images. The
+`kbc1126_ec_dump` and `kbc1126_ec_insert` tools are used to dump the
+two blobs from the factory firmware and insert them to the firmware
+image.
+
+
+Firmware format
+---------------
+
+We can easily find the BIOS region of the HP laptop firmware from the
+HP firmware update tool, which can be downloaded from the HP
+website. Now I take HP Elitebook 8470p as an example. This laptop has
+a 16MB flash chip, the last 5MB of which is the BIOS region.
+
+I use [radare2](https://radare.org) to analyze the firmware. Open the
+firmware image, and we can see 8 bytes at `$s-0x100` (`$s` means the
+image size).
+
+ [0x00000000]> x @ $s-0x100
+ - offset - 0 1 2 3 4 5 6 7 8 9 A B C D E F 0123456789ABCDEF
+ 0x00ffff00 fff7 0008 f700 08ff 0000 0000 0000 0000 ................
+
+X86 machines map the firmware at the end of the memory address
+space. These 8 bytes tell the address of the two blobs, which we call
+FW1 (uses bytes 0-3) and FW2 (uses bytes 4-7).
+
+Let's look at FW1. The first two bytes mean the address of FW1 is
+0xfff700 (these two bytes use big endian), i.e. `$s-0x900`. Byte 2 and
+3 are just complements of byte 1 and 2 (in this case,
+0x0008=0xffff-0xfff7).
+
+ [0x00000000]> x @ $s-0x900
+ - offset - 0 1 2 3 4 5 6 7 8 9 A B C D E F 0123456789ABCDEF
+ 0x00fff700 fc07 c13e 02ff 1000 0000 0000 0000 0000 ...>............
+
+Both FW1 and FW2 use the same format: the first two bytes is payload
+length, then a two-byte checksum, then the payload. The payload length
+and checksum are both in little endian. The checksum is
+[SYSV checksum](https://en.wikipedia.org/wiki/SYSV_checksum).
+
+
+How to use the tools
+--------------------
+
+`kbc1126_ec_dump` is used to dump FW1 and FW2. Run `kbc1126_ec_dump
+bios.rom`, then bios.rom.fw1 and bios.rom.fw2 are generated in the
+working directory.
+
+`kbc1126_ec_insert` will overwrite a firmware image by inserting FW1
+and FW2 in it. Please run it for its usage. You need to specify the
+offsets for FW1 and FW2. Using negative offset is recommended, which
+means the distance to the end of the image. For example, if we want to
+insert FW1 and FW2 at `$s-0x900` and `$s-0x90000` as the hp/8470p
+factory firmware to coreboot.rom, you can run `kbc1126_ec_insert
+coreboot.rom bios.rom.fw1 bios.rom.fw2 -0x900 -0x90000`.
diff --git a/util/kbc1126/kbc1126_ec_dump.c b/util/kbc1126/kbc1126_ec_dump.c
new file mode 100644
index 0000000..7470012
--- /dev/null
+++ b/util/kbc1126/kbc1126_ec_dump.c
@@ -0,0 +1,124 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <assert.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+static void usage(const char *s)
+{
+ printf("%s <rom file>\n", s);
+ exit(1);
+}
+
+static void FseekEnd(FILE *fp, long o)
+{
+ if (fseek(fp, o, SEEK_END) != 0) {
+ puts("fseek() error!\n");
+ exit(1);
+ }
+}
+
+void dump_fw(FILE *dst, FILE *src, long offset)
+{
+ static unsigned char buf[65536];
+
+ if (offset > 0)
+ offset -= 0x1000000;
+
+ printf("Dumping firmware at -0x%lx...", -offset);
+
+ FseekEnd(src, offset);
+ unsigned short len;
+ unsigned short cksum;
+ unsigned short _cksum = 0;
+ fread(&len, 2, 1, src);
+ fread(&cksum, 2, 1, src);
+ fread(buf, len, 1, src);
+
+ for (size_t i = 0; i < len; i++) {
+ _cksum += buf[i];
+ }
+ if (_cksum == cksum) {
+ puts("checksum ok");
+ } else {
+ puts("checksum fail");
+ exit(1);
+ }
+
+ fwrite(&len, 2, 1, dst);
+ fwrite(&cksum, 2, 1, dst);
+ fwrite(buf, len, 1, dst);
+}
+
+int main(int argc, char *argv[])
+{
+ if (argc != 2)
+ usage(argv[0]);
+
+ FILE *fp = fopen(argv[1], "rb+");
+
+ if (fp == NULL) {
+ puts("Error opening file!");
+ exit(1);
+ }
+
+ char *basename = strrchr(argv[1], '/');
+ if (basename == NULL)
+ basename = argv[1];
+ else
+ basename = basename + 1;
+
+ int len = strlen(basename);
+ char fn1[len + 5], fn2[len + 5];
+ strcpy(fn1, basename);
+ strcpy(fn2, basename);
+ strcat(fn1, ".fw1");
+ strcat(fn2, ".fw2");
+
+ FILE *fw1 = fopen(fn1, "wb+");
+ FILE *fw2 = fopen(fn2, "wb+");
+
+ long romsz;
+ FseekEnd(fp, -1);
+ romsz = ftell(fp) + 1;
+ printf("size of %s: 0x%lx\n", argv[1], romsz);
+
+ if (romsz & 0xff) {
+ puts("The ROM size must be multiple of 0x100");
+ exit(1);
+ }
+
+ /* read offset of fw1 and fw2 */
+ char offs[8];
+ FseekEnd(fp, -0x100);
+ fread(offs, 8, 1, fp);
+
+ assert(offs[0] + offs[2] == '\xff');
+ assert(offs[1] + offs[3] == '\xff');
+ assert(offs[4] + offs[6] == '\xff');
+ assert(offs[5] + offs[7] == '\xff');
+ long offw1 = (offs[0] << 16) | (offs[1] << 8);
+ long offw2 = (offs[4] << 16) | (offs[5] << 8);
+
+ dump_fw(fw1, fp, offw1);
+ dump_fw(fw2, fp, offw2);
+
+ fclose(fp);
+ fclose(fw1);
+ fclose(fw2);
+ return 0;
+}
diff --git a/util/kbc1126/kbc1126_ec_insert.c b/util/kbc1126/kbc1126_ec_insert.c
new file mode 100644
index 0000000..6c19c0e
--- /dev/null
+++ b/util/kbc1126/kbc1126_ec_insert.c
@@ -0,0 +1,108 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Iru Cai <mytbk920423(a)gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+
+static void usage(const char *s)
+{
+ printf("%s <rom file> <fw1> <fw2> <fw1 offset> <fw2 offset>\n", s);
+ exit(1);
+}
+
+static void FseekEnd(FILE *fp, long o)
+{
+ if (fseek(fp, o, SEEK_END) != 0) {
+ puts("fseek() error!\n");
+ exit(1);
+ }
+}
+
+int main(int argc, char *argv[])
+{
+ if (argc < 6)
+ usage(argv[0]);
+
+ FILE *fp = fopen(argv[1], "rb+");
+ FILE *fw1 = fopen(argv[2], "rb");
+ FILE *fw2 = fopen(argv[3], "rb");
+ long offset1 = strtol(argv[4], NULL, 0);
+ long offset2 = strtol(argv[5], NULL, 0);
+
+ if (fp == NULL || fw1 == NULL || fw2 == NULL) {
+ puts("Error opening file!");
+ exit(1);
+ }
+
+ if ((offset1 & 0xff) || (offset2 & 0xff)) {
+ puts("The offsets must be aligned to 0x100");
+ exit(1);
+ }
+
+ long romsz;
+ FseekEnd(fp, -1);
+ romsz = ftell(fp) + 1;
+ printf("size of %s: 0x%lx\n", argv[1], romsz);
+
+ if (romsz & 0xff) {
+ puts("The ROM size must be multiple of 0x100");
+ exit(1);
+ }
+
+ if (offset1 > 0)
+ offset1 = offset1 - romsz;
+
+ if (offset2 > 0)
+ offset2 = offset2 - romsz;
+
+ /* write two offsets to $s-0x100 */
+ char offs[8];
+ long os;
+ os = 0x1000000 + offset1;
+ offs[0] = os >> 16;
+ offs[1] = os >> 8;
+ offs[2] = 0xff - offs[0];
+ offs[3] = 0xff - offs[1];
+ os = 0x1000000 + offset2;
+ offs[4] = os >> 16;
+ offs[5] = os >> 8;
+ offs[6] = 0xff - offs[4];
+ offs[7] = 0xff - offs[5];
+ for (size_t i = 0; i < 8; i++) {
+ printf("%02hhx ", offs[i]);
+ }
+ puts("");
+ FseekEnd(fp, -0x100);
+ printf("writing to 0x%lx\n", ftell(fp));
+ fwrite(offs, 1, 8, fp);
+
+ /* write fw1 and fw2 */
+ char c;
+ FseekEnd(fp, offset1);
+ printf("writing to 0x%lx\n", ftell(fp));
+ while (fread(&c, 1, 1, fw1) == 1) {
+ fwrite(&c, 1, 1, fp);
+ }
+ FseekEnd(fp, offset2);
+ printf("writing to 0x%lx\n", ftell(fp));
+ while (fread(&c, 1, 1, fw2) == 1) {
+ fwrite(&c, 1, 1, fp);
+ }
+
+ fclose(fp);
+ fclose(fw1);
+ fclose(fw2);
+ return 0;
+}
diff --git a/util/kbc1126/makefile b/util/kbc1126/makefile
new file mode 100644
index 0000000..4826874
--- /dev/null
+++ b/util/kbc1126/makefile
@@ -0,0 +1,12 @@
+obj = kbc1126_ec_dump kbc1126_ec_insert
+HOSTCC := $(if $(shell type gcc 2>/dev/null),gcc,cc)
+
+all: $(obj)
+
+%: %.c
+ $(HOSTCC) -Wall -o $@ $<
+
+clean:
+ rm -f kbc1126_ec_dump kbc1126_ec_insert
+
+.PHONY: all clean
--
To view, visit https://review.coreboot.org/19071
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Gerrit-MessageType: merged
Gerrit-Change-Id: Ic521b177b9602ff042312cccaaa89371db7c5855
Gerrit-PatchSet: 4
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>