coreboot-gerrit May 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: nb/intel/x4x/raminit: Rework receive enable calibration
by Arthur Heymans (Code Review) 19 May '17

19 May '17

Hello Paul Menzel, build bot (Jenkins), coreboot org, Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/18692 to look at the new patch set (#20). Change subject: nb/intel/x4x/raminit: Rework receive enable calibration ...................................................................... nb/intel/x4x/raminit: Rework receive enable calibration Moves receive enable calibration to a separate file to lighten raminit.c a bit. Receive enable calibration is quite similar to gm45 so it reuses some of its function names. The functional changes are: * the minimum coarse is now reset for each channel; * on the second fine search for DQS high, TAP overflow is handled by increasing medium. These might improve stability. TESTED on ga-g41m-es2l Change-Id: I0c970455e609d3ce96a262cbf110336a2079da4d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/Makefile.inc M src/northbridge/intel/x4x/raminit_ddr2.c A src/northbridge/intel/x4x/rcven.c M src/northbridge/intel/x4x/x4x.h 4 files changed, 370 insertions(+), 282 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/18692/20 -- To view, visit https://review.coreboot.org/18692 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I0c970455e609d3ce96a262cbf110336a2079da4d Gerrit-PatchSet: 20 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com>

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Change in coreboot[master]: mb/lenovo/*/smihandler: Get rid of mainboard_io_trap_handler
by Arthur Heymans (Code Review) 19 May '17

19 May '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/19790 ) Change subject: mb/lenovo/*/smihandler: Get rid of mainboard_io_trap_handler ...................................................................... Patch Set 1: Code-Review+2 Is that tp-smapi IO range even used somewhere (ACPI?)? -- To view, visit https://review.coreboot.org/19790 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I33fd829a7e34aefa8f76ca6020cc8e802f7aab17 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: mb/lenovo/*/smihandler: Get rid of mainboard_io_trap_handler
by build bot (Jenkins) (Code Review) 19 May '17

19 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19790 ) Change subject: mb/lenovo/*/smihandler: Get rid of mainboard_io_trap_handler ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9748/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54011/ : SUCCESS -- To view, visit https://review.coreboot.org/19790 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I33fd829a7e34aefa8f76ca6020cc8e802f7aab17 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: mb/lenovo/*/smihandler: Get rid of mainboard_io_trap_handler
by Patrick Rudolph (Code Review) 19 May '17

19 May '17

Patrick Rudolph has uploaded a new change for review. ( https://review.coreboot.org/19790 ) Change subject: mb/lenovo/*/smihandler: Get rid of mainboard_io_trap_handler ...................................................................... mb/lenovo/*/smihandler: Get rid of mainboard_io_trap_handler Get rid of mainboard_io_trap_handler. The only purpose is to enable tp-smapi, but is already done on all boards in h8_enable, as of devicetree setting config0. Change-Id: I33fd829a7e34aefa8f76ca6020cc8e802f7aab17 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/mainboard/lenovo/l520/smihandler.c M src/mainboard/lenovo/t420/smihandler.c M src/mainboard/lenovo/t420s/smihandler.c M src/mainboard/lenovo/t430/smihandler.c M src/mainboard/lenovo/t430s/smihandler.c M src/mainboard/lenovo/t520/smihandler.c M src/mainboard/lenovo/t530/smihandler.c M src/mainboard/lenovo/x1_carbon_gen1/smihandler.c M src/mainboard/lenovo/x220/smihandler.c M src/mainboard/lenovo/x230/smihandler.c 10 files changed, 0 insertions(+), 218 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/19790/1 diff --git a/src/mainboard/lenovo/l520/smihandler.c b/src/mainboard/lenovo/l520/smihandler.c index 1e463ba..d2f7cb3 100644 --- a/src/mainboard/lenovo/l520/smihandler.c +++ b/src/mainboard/lenovo/l520/smihandler.c @@ -26,25 +26,6 @@ /* FIXME: check this */ #define GPE_EC_WAKE 13 -static void mainboard_smm_init(void) -{ - printk(BIOS_DEBUG, "initializing SMI\n"); - /* Enable 0x1600/0x1600 register pair */ - ec_set_bit(0x00, 0x05); -} - -int mainboard_io_trap_handler(int smif) -{ - static int smm_initialized; - - if (!smm_initialized) { - mainboard_smm_init(); - smm_initialized = 1; - } - - return 0; -} - static void mainboard_smi_handle_ec_sci(void) { u8 status = inb(EC_SC); diff --git a/src/mainboard/lenovo/t420/smihandler.c b/src/mainboard/lenovo/t420/smihandler.c index 23a98dd..eff0daf 100644 --- a/src/mainboard/lenovo/t420/smihandler.c +++ b/src/mainboard/lenovo/t420/smihandler.c @@ -25,25 +25,6 @@ #define GPE_EC_SCI 1 #define GPE_EC_WAKE 13 -static void mainboard_smm_init(void) -{ - printk(BIOS_DEBUG, "initializing SMI\n"); - /* Enable 0x1600/0x1600 register pair */ - ec_set_bit(0x00, 0x05); -} - -int mainboard_io_trap_handler(int smif) -{ - static int smm_initialized; - - if (!smm_initialized) { - mainboard_smm_init(); - smm_initialized = 1; - } - - return 0; -} - static void mainboard_smi_handle_ec_sci(void) { u8 status = inb(EC_SC); diff --git a/src/mainboard/lenovo/t420s/smihandler.c b/src/mainboard/lenovo/t420s/smihandler.c index 45e626b..2b6e6cd 100644 --- a/src/mainboard/lenovo/t420s/smihandler.c +++ b/src/mainboard/lenovo/t420s/smihandler.c @@ -31,32 +31,6 @@ #define GPE_EC_SCI 1 #define GPE_EC_WAKE 13 -static void mainboard_smm_init(void) -{ - printk(BIOS_DEBUG, "initializing SMI\n"); - /* Enable 0x1600/0x1600 register pair */ - ec_set_bit(0x00, 0x05); -} - -int mainboard_io_trap_handler(int smif) -{ - static int smm_initialized; - - if (!smm_initialized) { - mainboard_smm_init(); - smm_initialized = 1; - } - - switch (smif) { - default: - return 0; - } - - /* On success, the IO Trap Handler returns 1 - * On failure, the IO Trap Handler returns a value != 1 */ - return 1; -} - static void mainboard_smi_brightness_up(void) { u8 value; diff --git a/src/mainboard/lenovo/t430/smihandler.c b/src/mainboard/lenovo/t430/smihandler.c index e86c3c0..7af9e7d 100644 --- a/src/mainboard/lenovo/t430/smihandler.c +++ b/src/mainboard/lenovo/t430/smihandler.c @@ -26,23 +26,6 @@ #define GPE_EC_SCI 1 #define GPE_EC_WAKE 13 -static void mainboard_smm_init(void) -{ - printk(BIOS_DEBUG, "initializing SMI\n"); -} - -int mainboard_io_trap_handler(int smif) -{ - static int smm_initialized; - - if (!smm_initialized) { - mainboard_smm_init(); - smm_initialized = 1; - } - - return 0; -} - static void mainboard_smi_handle_ec_sci(void) { u8 status = inb(EC_SC); diff --git a/src/mainboard/lenovo/t430s/smihandler.c b/src/mainboard/lenovo/t430s/smihandler.c index 6e20500..70ecab2 100644 --- a/src/mainboard/lenovo/t430s/smihandler.c +++ b/src/mainboard/lenovo/t430s/smihandler.c @@ -29,32 +29,6 @@ #define GPE_EC_SCI 1 #define GPE_EC_WAKE 13 -static void mainboard_smm_init(void) -{ - printk(BIOS_DEBUG, "initializing SMI\n"); - /* Enable 0x1600/0x1600 register pair */ - ec_set_bit(0x00, 0x05); -} - -int mainboard_io_trap_handler(int smif) -{ - static int smm_initialized; - - if (!smm_initialized) { - mainboard_smm_init(); - smm_initialized = 1; - } - - switch (smif) { - default: - return 0; - } - - /* On success, the IO Trap Handler returns 1 - * On failure, the IO Trap Handler returns a value != 1 */ - return 1; -} - static void mainboard_smi_brightness_up(void) { u8 value; diff --git a/src/mainboard/lenovo/t520/smihandler.c b/src/mainboard/lenovo/t520/smihandler.c index 24722a0..c48cf3d 100644 --- a/src/mainboard/lenovo/t520/smihandler.c +++ b/src/mainboard/lenovo/t520/smihandler.c @@ -31,27 +31,6 @@ #define GPE_EC_SCI 1 #define GPE_EC_WAKE 13 -static void mainboard_smm_init(void) -{ - printk(BIOS_DEBUG, "initializing SMI\n"); - /* Enable 0x1600/0x1600 register pair */ - ec_set_bit(0x00, 0x05); -} - -int mainboard_io_trap_handler(int smif) -{ - static int smm_initialized; - - if (!smm_initialized) { - mainboard_smm_init(); - smm_initialized = 1; - } - - /* On success, the IO Trap Handler returns 1 - * On failure, the IO Trap Handler returns a value != 1 */ - return 0; -} - static void mainboard_smi_brightness_up(void) { u8 value; diff --git a/src/mainboard/lenovo/t530/smihandler.c b/src/mainboard/lenovo/t530/smihandler.c index 08554c9..c7ca206 100644 --- a/src/mainboard/lenovo/t530/smihandler.c +++ b/src/mainboard/lenovo/t530/smihandler.c @@ -31,32 +31,6 @@ #define GPE_EC_SCI 1 #define GPE_EC_WAKE 13 -static void mainboard_smm_init(void) -{ - printk(BIOS_DEBUG, "initializing SMI\n"); - /* Enable 0x1600/0x1600 register pair */ - ec_set_bit(0x00, 0x05); -} - -int mainboard_io_trap_handler(int smif) -{ - static int smm_initialized; - - if (!smm_initialized) { - mainboard_smm_init(); - smm_initialized = 1; - } - - switch (smif) { - default: - return 0; - } - - /* On success, the IO Trap Handler returns 1 - * On failure, the IO Trap Handler returns a value != 1 */ - return 1; -} - static void mainboard_smi_brightness_up(void) { u8 value; diff --git a/src/mainboard/lenovo/x1_carbon_gen1/smihandler.c b/src/mainboard/lenovo/x1_carbon_gen1/smihandler.c index eb92556..09dcbf2 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/smihandler.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/smihandler.c @@ -25,25 +25,6 @@ #define GPE_EC_SCI 1 #define GPE_EC_WAKE 13 -static void mainboard_smm_init(void) -{ - printk(BIOS_DEBUG, "initializing SMI\n"); - /* Enable 0x1600/0x1600 register pair */ - ec_set_bit(0x00, 0x05); -} - -int mainboard_io_trap_handler(int smif) -{ - static int smm_initialized; - - if (!smm_initialized) { - mainboard_smm_init(); - smm_initialized = 1; - } - - return 0; -} - static void mainboard_smi_handle_ec_sci(void) { u8 status = inb(EC_SC); diff --git a/src/mainboard/lenovo/x220/smihandler.c b/src/mainboard/lenovo/x220/smihandler.c index e1bb376..1dfd87e 100644 --- a/src/mainboard/lenovo/x220/smihandler.c +++ b/src/mainboard/lenovo/x220/smihandler.c @@ -31,32 +31,6 @@ #define GPE_EC_SCI 1 #define GPE_EC_WAKE 13 -static void mainboard_smm_init(void) -{ - printk(BIOS_DEBUG, "initializing SMI\n"); - /* Enable 0x1600/0x1600 register pair */ - ec_set_bit(0x00, 0x05); -} - -int mainboard_io_trap_handler(int smif) -{ - static int smm_initialized; - - if (!smm_initialized) { - mainboard_smm_init(); - smm_initialized = 1; - } - - switch (smif) { - default: - return 0; - } - - /* On success, the IO Trap Handler returns 1 - * On failure, the IO Trap Handler returns a value != 1 */ - return 1; -} - static void mainboard_smi_brightness_up(void) { u8 value; diff --git a/src/mainboard/lenovo/x230/smihandler.c b/src/mainboard/lenovo/x230/smihandler.c index eb92556..09dcbf2 100644 --- a/src/mainboard/lenovo/x230/smihandler.c +++ b/src/mainboard/lenovo/x230/smihandler.c @@ -25,25 +25,6 @@ #define GPE_EC_SCI 1 #define GPE_EC_WAKE 13 -static void mainboard_smm_init(void) -{ - printk(BIOS_DEBUG, "initializing SMI\n"); - /* Enable 0x1600/0x1600 register pair */ - ec_set_bit(0x00, 0x05); -} - -int mainboard_io_trap_handler(int smif) -{ - static int smm_initialized; - - if (!smm_initialized) { - mainboard_smm_init(); - smm_initialized = 1; - } - - return 0; -} - static void mainboard_smi_handle_ec_sci(void) { u8 status = inb(EC_SC); -- To view, visit https://review.coreboot.org/19790 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I33fd829a7e34aefa8f76ca6020cc8e802f7aab17 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: mainboard/lenovo/t430: Add Thinkpad T430 support
by Patrick Rudolph (Code Review) 19 May '17

19 May '17

Patrick Rudolph has submitted this change and it was merged. ( https://review.coreboot.org/18011 ) Change subject: mainboard/lenovo/t430: Add Thinkpad T430 support ...................................................................... mainboard/lenovo/t430: Add Thinkpad T430 support Tested and working: * HDD LED * Booting GNU Linux 4.9 from HDD using SeaBios * Booting GNU Linux 4.9 from USB using SeaBios * Native GFX init * All Fn function keys * Speakers * PCIe Wifi * Camera * WWAN * Fan (Dynamic Thermal Managment) * Flashing using internal programmer * Dual memory DIMMs running at up to DDR3-1866 * AC events * Touchpad, trackball and keyboard * USB3 ports running at SuperSpeed * Ethernet * Headphone jack * Speaker mute * Microphone mute * Volume keys * Fingerprint sensor * Lid switch * Thinklight * TPM (disable SeaBios CONFIG_TCGBIOS) * CMOS options: ** power_on_after_fail ** reboot_counter ** boot_option ** gfx_uma_size ** usb_always_on Untested: * Booting Windows * Hybrid graphics * Docking station * VGA Broken: * Wifi LED is always on Change-Id: I5403cfb80a57753e873c570d95ca535cf5f45630 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/18011 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- A src/mainboard/lenovo/t430/Kconfig A src/mainboard/lenovo/t430/Kconfig.name A src/mainboard/lenovo/t430/Makefile.inc A src/mainboard/lenovo/t430/acpi/ec.asl A src/mainboard/lenovo/t430/acpi/platform.asl A src/mainboard/lenovo/t430/acpi/superio.asl A src/mainboard/lenovo/t430/acpi_tables.c A src/mainboard/lenovo/t430/board_info.txt A src/mainboard/lenovo/t430/cmos.default A src/mainboard/lenovo/t430/cmos.layout A src/mainboard/lenovo/t430/devicetree.cb A src/mainboard/lenovo/t430/dsdt.asl A src/mainboard/lenovo/t430/gpio.c A src/mainboard/lenovo/t430/hda_verb.c A src/mainboard/lenovo/t430/mainboard.c A src/mainboard/lenovo/t430/romstage.c A src/mainboard/lenovo/t430/smihandler.c A src/mainboard/lenovo/t430/thermal.h 18 files changed, 1,086 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig new file mode 100644 index 0000000..0b7dc4b --- /dev/null +++ b/src/mainboard/lenovo/t430/Kconfig @@ -0,0 +1,71 @@ +if BOARD_LENOVO_THINKPAD_T430 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select BOARD_ROMSIZE_KB_12288 + select CPU_INTEL_SOCKET_RPGA989 + select DRIVERS_RICOH_RCE822 + select EC_LENOVO_H8 + select EC_LENOVO_PMH7 + select NO_UART_ON_SUPERIO + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select MAINBOARD_HAS_LPC_TPM + select INTEL_INT15 + select NORTHBRIDGE_INTEL_IVYBRIDGE + select SANDYBRIDGE_IVYBRIDGE_LVDS + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG + select ENABLE_VMX + select DRIVERS_LENOVO_HYBRID_GRAPHICS + +config HAVE_IFD_BIN + bool + default n + +config HAVE_ME_BIN + bool + default n + +config MAINBOARD_DIR + string + default lenovo/t430 + +config MAINBOARD_PART_NUMBER + string + default "ThinkPad T430" + +config VGA_BIOS_ID + string + default "8086,0166" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x21f3 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x17aa + +config MMCONF_BASE_ADDRESS + hex + default 0xf8000000 + +config DRAM_RESET_GATE_GPIO + int + default 10 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 2 +endif diff --git a/src/mainboard/lenovo/t430/Kconfig.name b/src/mainboard/lenovo/t430/Kconfig.name new file mode 100644 index 0000000..7ae32b8 --- /dev/null +++ b/src/mainboard/lenovo/t430/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_LENOVO_THINKPAD_T430 + bool "ThinkPad T430" diff --git a/src/mainboard/lenovo/t430/Makefile.inc b/src/mainboard/lenovo/t430/Makefile.inc new file mode 100644 index 0000000..ae84209 --- /dev/null +++ b/src/mainboard/lenovo/t430/Makefile.inc @@ -0,0 +1,4 @@ +romstage-y += romstage.c +romstage-y += gpio.c +ramstage-y += acpi_tables.c +smm-y += smihandler.c diff --git a/src/mainboard/lenovo/t430/acpi/ec.asl b/src/mainboard/lenovo/t430/acpi/ec.asl new file mode 100644 index 0000000..3c7f89d --- /dev/null +++ b/src/mainboard/lenovo/t430/acpi/ec.asl @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +#define EC_LENOVO_H8_ME_WORKAROUND 1 +#define THINKPAD_EC_GPE 17 + +#include <ec/lenovo/h8/acpi/ec.asl> diff --git a/src/mainboard/lenovo/t430/acpi/platform.asl b/src/mainboard/lenovo/t430/acpi/platform.asl new file mode 100644 index 0000000..efbf0ea --- /dev/null +++ b/src/mainboard/lenovo/t430/acpi/platform.asl @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK,1) +{ + /* ME may not be up yet. */ + Store (0, \_TZ.MEB1) + Store (0, \_TZ.MEB2) + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + \_SB.PCI0.LPCB.EC.MUTE(1) + \_SB.PCI0.LPCB.EC.USBP(0) + \_SB.PCI0.LPCB.EC.RADI(0) +} diff --git a/src/mainboard/lenovo/t430/acpi/superio.asl b/src/mainboard/lenovo/t430/acpi/superio.asl new file mode 100644 index 0000000..8964c36 --- /dev/null +++ b/src/mainboard/lenovo/t430/acpi/superio.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/lenovo/t430/acpi_tables.c b/src/mainboard/lenovo/t430/acpi_tables.c new file mode 100644 index 0000000..c5559af --- /dev/null +++ b/src/mainboard/lenovo/t430/acpi_tables.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tmps = CTDP_SENSOR_ID; + + gnvs->f1of = CTDP_NOMINAL_THRESHOLD_OFF; + gnvs->f1on = CTDP_NOMINAL_THRESHOLD_ON; + + gnvs->f0of = CTDP_DOWN_THRESHOLD_OFF; + gnvs->f0on = CTDP_DOWN_THRESHOLD_ON; + + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; + gnvs->tmax = MAX_TEMPERATURE; + gnvs->flvl = 5; +} + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + acpi_update_thermal_table(gnvs); +} diff --git a/src/mainboard/lenovo/t430/board_info.txt b/src/mainboard/lenovo/t430/board_info.txt new file mode 100644 index 0000000..ac71c09 --- /dev/null +++ b/src/mainboard/lenovo/t430/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n +Release year: 2012 \ No newline at end of file diff --git a/src/mainboard/lenovo/t430/cmos.default b/src/mainboard/lenovo/t430/cmos.default new file mode 100644 index 0000000..ae19afb --- /dev/null +++ b/src/mainboard/lenovo/t430/cmos.default @@ -0,0 +1,17 @@ +boot_option=Fallback +debug_level=Spew +power_on_after_fail=Disable +nmi=Enable +volume=0x3 +first_battery=Primary +bluetooth=Enable +wwan=Enable +wlan=Enable +touchpad=Enable +sata_mode=AHCI +fn_ctrl_swap=Disable +sticky_fn=Disable +trackpoint=Enable +backlight=Both +usb_always_on=Enable +hybrid_graphics_mode=Integrated Only diff --git a/src/mainboard/lenovo/t430/cmos.layout b/src/mainboard/lenovo/t430/cmos.layout new file mode 100644 index 0000000..99f815e --- /dev/null +++ b/src/mainboard/lenovo/t430/cmos.layout @@ -0,0 +1,144 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +#400 8 r 0 reserved for century byte + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: EC +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +419 1 e 1 usb_always_on +#420 1 r 0 unused +421 1 e 9 sata_mode +422 2 e 10 backlight + +# coreboot config options: cpu +#424 8 r 0 unused + +# coreboot config options: northbridge +432 3 e 11 gfx_uma_size +435 2 e 12 hybrid_graphics_mode +#437 3 r 0 unused +440 8 h 0 volume + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 Both +10 1 Keyboard only +10 2 Thinklight only +10 3 None +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M +12 0 Integrated Only +12 1 Discrete Only + +# ----------------------------------------------------------------- +checksums + +checksum 392 447 984 diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb new file mode 100644 index 0000000..86c8756 --- /dev/null +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -0,0 +1,194 @@ +chip northbridge/intel/sandybridge + register "gfx.ndid" = "3" + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + + # Enable DisplayPort Hotplug with 6ms pulse + register "gpu_dp_d_hotplug" = "0x06" + + # Enable Panel as LVDS and configure power delays + register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms + register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms + register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms + register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms + register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms + register "gfx.use_spread_spectrum_clock" = "1" + register "gfx.link_frequency_270_mhz" = "1" + register "gpu_cpu_backlight" = "0x1155" + register "gpu_pch_backlight" = "0x11551155" + + device cpu_cluster 0x0 on + chip cpu/intel/socket_rPGA989 + device lapic 0x0 on + end + end + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0xacac off + end + end + end + + # Override fuse bits that hard-code the value to 666 Mhz + register "max_mem_clock_mhz" = "933" + + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "1" + register "gen1_dec" = "0x000c15e1" + register "gen2_dec" = "0x007c1601" + register "gen3_dec" = "0x000c06a1" + register "gpi13_routing" = "2" + register "gpi1_routing" = "2" + register "p_cnt_throttling_supported" = "1" + register "pcie_hotplug_map" = "{ 1, 0, 1, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x17" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x04000201" + register "xhci_switchable_ports" = "0x0000000f" + + # device specific SPI configuration + register "spi_uvscc" = "0x2005" + register "spi_lvscc" = "0x2005" + + device pci 14.0 on # USB 3.0 Controller + subsystemid 0x17aa 0x21f3 + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x17aa 0x21f3 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x17aa 0x21f3 + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x17aa 0x21f3 + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x17aa 0x21f3 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x17aa 0x21f3 + chip drivers/ricoh/rce822 # Ricoh cardreader + register "disable_mask" = "0x87" + register "sdwppol" = "1" + device pci 00.0 on # Ricoh SD card reader + subsystemid 0x17aa 0x21f3 + end + end + end + device pci 1c.1 on # PCIe Port #2 + subsystemid 0x17aa 0x21f3 + end + device pci 1c.2 on # PCIe Port #3 + subsystemid 0x17aa 0x21f3 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x17aa 0x21f3 + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x17aa 0x21f3 + chip ec/lenovo/pmh7 + register "backlight_enable" = "0x01" + register "dock_event_enable" = "0x01" + device pnp ff.1 on # dummy + end + end + chip ec/lenovo/h8 + device pnp ff.2 on # dummy + io 0x60 = 0x62 + io 0x62 = 0x66 + io 0x64 = 0x1600 + io 0x66 = 0x1604 + end + register "config0" = "0xa7" + register "config1" = "0x01" + register "config2" = "0xa0" + register "config3" = "0xe2" + + register "has_keyboard_backlight" = "0" + + register "beepmask0" = "0x02" + register "beepmask1" = "0x86" + register "has_power_management_beeps" = "1" + register "event2_enable" = "0xff" + register "event3_enable" = "0xff" + register "event4_enable" = "0xf0" + register "event5_enable" = "0x3c" + register "event6_enable" = "0x00" + register "event7_enable" = "0xa1" + register "event8_enable" = "0x7b" + register "event9_enable" = "0xff" + register "eventa_enable" = "0x00" + register "eventb_enable" = "0x00" + register "eventc_enable" = "0xff" + register "eventd_enable" = "0xff" + register "evente_enable" = "0x0d" + end + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x17aa 0x21f3 + end + device pci 1f.3 on # SMBus + subsystemid 0x17aa 0x21f3 + chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip + device i2c 54 on + end + device i2c 55 on + end + device i2c 56 on + end + device i2c 57 on + end + device i2c 5c on + end + device i2c 5d on + end + device i2c 5e on + end + device i2c 5f on + end + end + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x17aa 0x21f3 + end + device pci 01.0 on # PCIe Bridge for discrete graphics + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x17aa 0x21f3 + end + device pci 04.0 off # Signal processing controller + end + end +end diff --git a/src/mainboard/lenovo/t430/dsdt.asl b/src/mainboard/lenovo/t430/dsdt.asl new file mode 100644 index 0000000..638592d --- /dev/null +++ b/src/mainboard/lenovo/t430/dsdt.asl @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, // DSDT revision: ACPI v3.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20141018 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + #include <cpu/intel/model_206ax/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> + } + } +} diff --git a/src/mainboard/lenovo/t430/gpio.c b/src/mainboard/lenovo/t430/gpio.c new file mode 100644 index 0000000..2e4897a --- /dev/null +++ b/src/mainboard/lenovo/t430/gpio.c @@ -0,0 +1,169 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio10 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_HIGH, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, +}; + +const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/lenovo/t430/hda_verb.c b/src/mainboard/lenovo/t430/hda_verb.c new file mode 100644 index 0000000..02f433f --- /dev/null +++ b/src/mainboard/lenovo/t430/hda_verb.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0269, /* Codec Vendor / Device ID: Realtek */ + 0x17aa21f3, /* Subsystem ID */ + + 11, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x17aa21f3), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x0, 0x12, 0x90a60140), + + /* NID 0x14. */ + AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x0, 0x15, 0x03211020), + + /* NID 0x17. */ + AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), + + /* NID 0x18. */ + AZALIA_PIN_CFG(0x0, 0x18, 0x03a11830), + + /* NID 0x19. */ + AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0), + + /* NID 0x1a. */ + AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), + + /* NID 0x1b. */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), + + /* NID 0x1d. */ + AZALIA_PIN_CFG(0x0, 0x1d, 0x40138205), + + /* NID 0x1e. */ + AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), + + /* NID 0x07. */ + AZALIA_PIN_CFG(0x3, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/t430/mainboard.c b/src/mainboard/lenovo/t430/mainboard.c new file mode 100644 index 0000000..d18678b --- /dev/null +++ b/src/mainboard/lenovo/t430/mainboard.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <ec/lenovo/h8/h8.h> + +void h8_mainboard_init_dock (void) +{ +} + +static void mainboard_enable(device_t dev) +{ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/lenovo/t430/romstage.c b/src/mainboard/lenovo/t430/romstage.c new file mode 100644 index 0000000..eb2d29e --- /dev/null +++ b/src/mainboard/lenovo/t430/romstage.c @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <device/pci_def.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <ec/lenovo/pmh7/pmh7.h> + +void pch_enable_lpc(void) +{ + /* EC Decode Range Port60/64, Port62/66 */ + /* Enable TPM, EC, PS/2 Keyboard/Mouse */ + pci_write_config16(PCH_LPC_DEV, LPC_EN, + CNF2_LPC_EN | MC_LPC_EN | KBC_LPC_EN); + + pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, + (0x0c << 16) | EC_LENOVO_PMH7_BASE | 1); +} + +void rcba_config(void) +{ + /* Disable unused devices (board specific, reserved only). + * FIXME: Test if reserved bits are read only. */ + RCBA32(FD) = PCH_DISABLE_ALWAYS | 0x10001fe0; +} + +/* FIXME: used T530 values here */ +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 1, 0 }, + { 1, 1, 1 }, + { 1, 2, 3 }, + { 1, 1, -1 }, + { 1, 1, 2 }, + { 1, 0, -1 }, + { 0, 0, -1 }, + { 1, 2, -1 }, + { 1, 0, -1 }, + { 1, 1, 5 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 3, -1 }, + { 1, 1, -1 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x51, id_only); +} diff --git a/src/mainboard/lenovo/t430/smihandler.c b/src/mainboard/lenovo/t430/smihandler.c new file mode 100644 index 0000000..e86c3c0 --- /dev/null +++ b/src/mainboard/lenovo/t430/smihandler.c @@ -0,0 +1,102 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <ec/acpi/ec.h> +#include <ec/lenovo/h8/h8.h> +#include <delay.h> +#include <southbridge/intel/bd82x6x/pch.h> + +#define GPE_EC_SCI 1 +#define GPE_EC_WAKE 13 + +static void mainboard_smm_init(void) +{ + printk(BIOS_DEBUG, "initializing SMI\n"); +} + +int mainboard_io_trap_handler(int smif) +{ + static int smm_initialized; + + if (!smm_initialized) { + mainboard_smm_init(); + smm_initialized = 1; + } + + return 0; +} + +static void mainboard_smi_handle_ec_sci(void) +{ + u8 status = inb(EC_SC); + u8 event; + + if (!(status & EC_SCI_EVT)) + return; + + event = ec_query(); + printk(BIOS_DEBUG, "EC event %02x\n", event); +} + +void mainboard_smi_gpi(u32 gpi_sts) +{ + if (gpi_sts & (1 << GPE_EC_SCI)) + mainboard_smi_handle_ec_sci(); +} + +int mainboard_smi_apmc(u8 data) +{ + switch (data) { + case APM_CNT_ACPI_ENABLE: + /* use 0x1600/0x1604 to prevent races with userspace */ + ec_set_ports(0x1604, 0x1600); + /* route EC_SCI to SCI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + case APM_CNT_ACPI_DISABLE: + /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't + provide a EC query function */ + ec_set_ports(0x66, 0x62); + /* route EC_SCI to SMI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + default: + break; + } + return 0; +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (slp_typ == 3) { + h8_usb_always_on(); + + u8 ec_wake = ec_read(0x32); + /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ + if (ec_wake & 0x14) { + /* Redirect EC WAKE GPE to SCI. */ + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); + } + } +} diff --git a/src/mainboard/lenovo/t430/thermal.h b/src/mainboard/lenovo/t430/thermal.h new file mode 100644 index 0000000..e3e49f5 --- /dev/null +++ b/src/mainboard/lenovo/t430/thermal.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _LENOVO_T430_THERMAL_H +#define _LENOVO_T430_THERMAL_H + +/* Config TDP Sensor ID */ +#define CTDP_SENSOR_ID 0 /* PECI */ + +/* Config TDP Nominal */ +#define CTDP_NOMINAL_THRESHOLD_OFF 0 +#define CTDP_NOMINAL_THRESHOLD_ON 0 + +/* Config TDP Down */ +#define CTDP_DOWN_THRESHOLD_OFF 80 +#define CTDP_DOWN_THRESHOLD_ON 90 + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 90 + +/* Tj_max value for calculating PECI CPU temperature */ +#define MAX_TEMPERATURE 105 + +#endif -- To view, visit https://review.coreboot.org/18011 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I5403cfb80a57753e873c570d95ca535cf5f45630 Gerrit-PatchSet: 15 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/lenovo/t400: Generate undock event with dock button
by Patrick Rudolph (Code Review) 19 May '17

19 May '17

Patrick Rudolph has submitted this change and it was merged. ( https://review.coreboot.org/19551 ) Change subject: mb/lenovo/t400: Generate undock event with dock button ...................................................................... mb/lenovo/t400: Generate undock event with dock button Change-Id: I1161ed5f5c30201d2ad156d8fce4e8a90e65bff6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/19551 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- M src/mainboard/lenovo/t400/acpi/dock.asl 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: Patrick Rudolph: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/mainboard/lenovo/t400/acpi/dock.asl b/src/mainboard/lenovo/t400/acpi/dock.asl index e2aa53e..4a0ccf3 100644 --- a/src/mainboard/lenovo/t400/acpi/dock.asl +++ b/src/mainboard/lenovo/t400/acpi/dock.asl @@ -56,6 +56,11 @@ Notify(\_SB.DOCK, 3) } + Method(_Q50, 0, NotSerialized) + { + Notify(\_SB.DOCK, 3) + } + Method(_Q58, 0, NotSerialized) { Notify(\_SB.DOCK, 0) -- To view, visit https://review.coreboot.org/19551 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I1161ed5f5c30201d2ad156d8fce4e8a90e65bff6 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: nb/intel/sandybridge: Hide additional nb devices
by Patrick Rudolph (Code Review) 19 May '17

19 May '17

Patrick Rudolph has submitted this change and it was merged. ( https://review.coreboot.org/19689 ) Change subject: nb/intel/sandybridge: Hide additional nb devices ...................................................................... nb/intel/sandybridge: Hide additional nb devices Hide device 4 and device 7 if disabled. Allows devicetree settings to take effect. Tested on Lenovo T430. Change-Id: I64a19e2bbdb1640e1d732f6e4486f73cbb0bda81 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/19689 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/sandybridge/sandybridge.h 2 files changed, 12 insertions(+), 0 deletions(-) Approvals: Arthur Heymans: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 562e7f2..5c5f41a 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -357,11 +357,21 @@ printk(BIOS_DEBUG, "Disabling IGD.\n"); reg &= ~DEVEN_IGD; } + dev = dev_find_slot(0, PCI_DEVFN(4, 0)); + if (!dev || !dev->enabled) { + printk(BIOS_DEBUG, "Disabling Device 4.\n"); + reg &= ~DEVEN_D4EN; + } dev = dev_find_slot(0, PCI_DEVFN(6, 0)); if (!dev || !dev->enabled) { printk(BIOS_DEBUG, "Disabling PEG60.\n"); reg &= ~DEVEN_PEG60; } + dev = dev_find_slot(0, PCI_DEVFN(7, 0)); + if (!dev || !dev->enabled) { + printk(BIOS_DEBUG, "Disabling Device 7.\n"); + reg &= ~DEVEN_D7EN; + } dev = dev_find_slot(0, PCI_DEVFN(0, 0)); pci_write_config32(dev, DEVEN, reg); diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 8d2ae85..bc659be 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -75,7 +75,9 @@ #define GGC 0x50 /* GMCH Graphics Control */ #define DEVEN 0x54 /* Device Enable */ +#define DEVEN_D7EN (1 << 14) #define DEVEN_PEG60 (1 << 13) +#define DEVEN_D4EN (1 << 7) #define DEVEN_IGD (1 << 4) #define DEVEN_PEG10 (1 << 3) #define DEVEN_PEG11 (1 << 2) -- To view, visit https://review.coreboot.org/19689 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I64a19e2bbdb1640e1d732f6e4486f73cbb0bda81 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: [WIP]mainboard/intel/glkrvp: Add GPE routing settings for GL...
by build bot (Jenkins) (Code Review) 19 May '17

19 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19739 ) Change subject: [WIP]mainboard/intel/glkrvp: Add GPE routing settings for GLKRVP. ...................................................................... Patch Set 6: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/54010/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/9747/ : SUCCESS -- To view, visit https://review.coreboot.org/19739 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I56a99bbb70ac9edda8448fabf05e3ea90d18d93c Gerrit-PatchSet: 6 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: [WIP]mainboard/intel/glkrvp: Add GPE routing settings for GL...
by Hannah Williams (Code Review) 19 May '17

19 May '17

Hello Shaunak Saha, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19739 to look at the new patch set (#6). Change subject: [WIP]mainboard/intel/glkrvp: Add GPE routing settings for GLKRVP. ...................................................................... [WIP]mainboard/intel/glkrvp: Add GPE routing settings for GLKRVP. This patch sets the devicetree for gpe0_dw configuration and also configures the GPIO lines for SCI. The macros for LID switch is also set. Change-Id: I56a99bbb70ac9edda8448fabf05e3ea90d18d93c Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- M src/mainboard/intel/glkrvp/dsdt.asl M src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/ec.h M src/mainboard/intel/glkrvp/variants/baseboard/include/baseboard/gpio.h 4 files changed, 33 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/19739/6 -- To view, visit https://review.coreboot.org/19739 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I56a99bbb70ac9edda8448fabf05e3ea90d18d93c Gerrit-PatchSet: 6 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: [WIP]mainboard/intel/glkrvp: Add GPE routing settings for GL...
by build bot (Jenkins) (Code Review) 19 May '17

19 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19739 ) Change subject: [WIP]mainboard/intel/glkrvp: Add GPE routing settings for GLKRVP. ...................................................................... Patch Set 5: Build Failed https://qa.coreboot.org/job/coreboot-gerrit/54009/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/9746/ : SUCCESS -- To view, visit https://review.coreboot.org/19739 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I56a99bbb70ac9edda8448fabf05e3ea90d18d93c Gerrit-PatchSet: 5 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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coreboot-gerrit May 2017