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Change in coreboot[master]: soc/intel/apollolake: Use common systemagent code
by Subrata Banik (Code Review) 19 May '17

19 May '17

Subrata Banik has uploaded a new change for review. ( https://review.coreboot.org/19795 ) Change subject: soc/intel/apollolake: Use common systemagent code ...................................................................... soc/intel/apollolake: Use common systemagent code This patch perform resource mapping for PCI, fixed MMIO, DRAM and IMR's based on inputs given by SoC. TEST=Ensure PCI root bridge 0:0:0 memory resource allocation remains same between previous implementation and current implementation. Change-Id: I15a3b2fc46ec9063b54379d41996b9a1d612cfd2 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/include/soc/systemagent.h M src/soc/intel/apollolake/northbridge.c M src/soc/intel/apollolake/romstage.c 5 files changed, 76 insertions(+), 167 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/19795/1 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 56f0d20..7c95e1c 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -50,6 +50,7 @@ select RELOCATABLE_RAMSTAGE # Build fails if this is not selected select RTC select SMM_TSEG + select SA_ENABLE_IMR select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index da60827..90a1ba9 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -219,7 +219,6 @@ uint32_t power_unit; uint32_t tdp, min_power, max_power; uint32_t pl2_val; - uint32_t *rapl_mmio_reg; if (!dev || !dev->chip_info) { printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); @@ -272,15 +271,12 @@ printk(BIOS_INFO, "RAPL PL2 %d.%dW\n", pl2_val / power_unit, 100 * (pl2_val % power_unit) / power_unit); - /* Get the MMIO address */ - rapl_mmio_reg = (void *)(uintptr_t) (MCH_BASE_ADDRESS + - MCHBAR_RAPL_PPL); /* Setting RAPL MMIO register for Power limits. * RAPL driver is using MSR instead of MMIO. * So, disabled LIMIT_EN bit for MMIO. */ - write32(rapl_mmio_reg, limit.lo & ~(PKG_POWER_LIMIT_EN)); - write32(rapl_mmio_reg + 1, limit.hi & ~(PKG_POWER_LIMIT_EN)); + MCHBAR32(MCHBAR_RAPL_PPL) = limit.lo & ~(PKG_POWER_LIMIT_EN); + MCHBAR32(MCHBAR_RAPL_PPL + 4) = limit.hi & ~(PKG_POWER_LIMIT_EN); } static void soc_init(void *data) diff --git a/src/soc/intel/apollolake/include/soc/systemagent.h b/src/soc/intel/apollolake/include/soc/systemagent.h index 1ed0a1f..d6c7390 100644 --- a/src/soc/intel/apollolake/include/soc/systemagent.h +++ b/src/soc/intel/apollolake/include/soc/systemagent.h @@ -20,12 +20,6 @@ #include <intelblocks/systemagent.h> -/* IMR registers are found under MCHBAR. */ -#define MCHBAR_IMR0BASE 0x6870 -#define MCHBAR_IMR0MASK 0x6874 -#define MCH_IMR_PITCH 0x20 -#define MCH_NUM_IMRS 20 - /* RAPL Package Power Limit register under MCHBAR. */ #define PUNIT_THERMAL_DEVICE_IRQ 0x700C #define PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER 0x18 @@ -44,5 +38,28 @@ /* Must be last. */ MAX_MAP_ENTRIES }; + +/* IMR registers are found under MCHBAR. */ +#define IMR0_BASE 0x6870 +#define IMR1_BASE 0x6890 +#define IMR2_BASE 0x68B0 +#define IMR3_BASE 0x68D0 +#define IMR4_BASE 0x68F0 +#define IMR5_BASE 0x6910 +#define IMR6_BASE 0x6930 +#define IMR7_BASE 0x6950 +#define IMR8_BASE 0x6970 +#define IMR9_BASE 0x6990 +#define IMR10_BASE 0x69B0 +#define IMR11_BASE 0x69D0 +#define IMR12_BASE 0x69F0 +#define IMR13_BASE 0x6A10 +#define IMR14_BASE 0x6A30 +#define IMR15_BASE 0x6A50 +#define IMR16_BASE 0x6A70 +#define IMR17_BASE 0x6A90 +#define IMR18_BASE 0x6AB0 +#define IMR19_BASE 0x6AD0 + #define SOC_SA_IMR_RESOURCES 20 #endif /* SOC_APOLLOLAKE_SYSTEMAGENT_H */ diff --git a/src/soc/intel/apollolake/northbridge.c b/src/soc/intel/apollolake/northbridge.c index 9519603..70893e6 100644 --- a/src/soc/intel/apollolake/northbridge.c +++ b/src/soc/intel/apollolake/northbridge.c @@ -20,150 +20,42 @@ #include <soc/iomap.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <intelblocks/systemagent.h> #include <soc/systemagent.h> #include <soc/pci_ids.h> -static uint32_t get_bar(device_t dev, unsigned int index) -{ - uint32_t bar; - - bar = pci_read_config32(dev, index); - - /* If not enabled return 0 else strip enabled bit */ - return (bar & 1) ? (bar & ~1) : 0; -} - -static int mc_add_fixed_mmio_resources(device_t dev, int index) -{ - unsigned long addr; - - /* PCI extended config region */ - addr = ALIGN_DOWN(get_bar(dev, PCIEXBAR), 256*MiB) / KiB; - mmio_resource(dev, index++, addr, CONFIG_SA_PCIEX_LENGTH / KiB); - - /* Memory Controller Hub */ - addr = ALIGN_DOWN(get_bar(dev, MCHBAR), 32*KiB) / KiB; - mmio_resource(dev, index++, addr, MCH_BASE_SIZE / KiB); - - return index; -} - -static bool is_imr_enabled(uint32_t imr_base_reg) -{ - return !!(imr_base_reg & (1 << 31)); -} - -static void imr_resource(device_t dev, int idx, uint32_t base, uint32_t mask) -{ - uint32_t base_k, size_k; - /* Bits 28:0 encode the base address bits 38:10, hence the KiB unit. */ - base_k = (base & 0x0fffffff); - /* Bits 28:0 encode the AND mask used for comparison, in KiB. */ - size_k = ((~mask & 0x0fffffff) + 1); - /* - * IMRs sit in lower DRAM. Mark them cacheable, otherwise we run - * out of MTRRs. Memory reserved by IMRs is not usable for host - * so mark it reserved. - */ - reserved_ram_resource(dev, idx, base_k, size_k); -} - -static int mc_add_imr_resources(device_t dev, int index) -{ - uint8_t *mchbar; - size_t i, imr_offset; - uint32_t base, mask; - - mchbar = (void *)(ALIGN_DOWN(get_bar(dev, MCHBAR), 32*KiB)); - - for (i = 0; i < MCH_NUM_IMRS; i++) { - imr_offset = i * MCH_IMR_PITCH; - base = read32(mchbar + imr_offset + MCHBAR_IMR0BASE); - mask = read32(mchbar + imr_offset + MCHBAR_IMR0MASK); - - if (is_imr_enabled(base)) - imr_resource(dev, index++, base, mask); - } - - return index; -} - - -static int mc_add_dram_resources(device_t dev, int index) -{ - unsigned long base_k, size_k; - uint32_t bgsm, bdsm, tolud, tseg; - uint64_t touud; - - bgsm = ALIGN_DOWN(pci_read_config32(dev, BGSM), MiB); - bdsm = ALIGN_DOWN(pci_read_config32(dev, BDSM), MiB); - tolud = ALIGN_DOWN(pci_read_config32(dev, TOLUD), MiB); - tseg = ALIGN_DOWN(pci_read_config32(dev, TSEG), MiB); - - /* TOUUD is naturally a 64 bit integer */ - touud = pci_read_config32(dev, TOUUD + sizeof(uint32_t)); - touud <<= 32; - touud |= ALIGN_DOWN(pci_read_config32(dev, TOUUD), MiB); - - /* 0 -> 0xa0000: 640kb of DOS memory. Not enough for anybody nowadays */ - ram_resource(dev, index++, 0, 640); - - /* 0xa0000 - 0xbffff: legacy VGA */ - mmio_resource(dev, index++, 640, 128); - - /* 0xc0000 -> 0xfffff: leave without e820 entry, as it has special uses - * 0x100000 -> top_of_ram - */ - base_k = 1024; - size_k = (tseg / KiB) - base_k; - ram_resource(dev, index++, base_k, size_k); - - /* TSEG -> BGSM */ - reserved_ram_resource(dev, index++, tseg / KiB, (bgsm - tseg) / KiB); - - /* BGSM -> BDSM */ - mmio_resource(dev, index++, bgsm / KiB, (bdsm - bgsm) / KiB); - - /* BDSM -> TOLUD */ - mmio_resource(dev, index++, bdsm / KiB, (tolud - bdsm) / KiB); - - /* 4G -> TOUUD */ - base_k = 4ULL*GiB / KiB; - size_k = (touud / KiB) - base_k; - ram_resource(dev, index++, base_k, size_k); - - - return index; -} - -static void northbridge_read_resources(device_t dev) -{ - - int index = 0; - /* Read standard PCI resources. */ - pci_dev_read_resources(dev); - - /* Add all fixed MMIO resources. */ - index = mc_add_fixed_mmio_resources(dev, index); - - /* Calculate and add DRAM resources. */ - index = mc_add_dram_resources(dev, index); - - /* Add the isolated memory ranges (IMRs). */ - mc_add_imr_resources(dev, index); - -} - -static struct device_operations northbridge_ops = { - .read_resources = northbridge_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = DEVICE_NOOP, - .enable = DEVICE_NOOP +struct sa_mmio_descriptor sa_fixed_resources[SOC_SA_FIXED_RESOURCES] = { + { PCIEXBAR, 0, get_pcie_base_addr, "PCIEXBAR" }, + { MCHBAR, MCH_BASE_SIZE, get_base_addr, "MCHBAR" }, }; -static const struct pci_driver northbridge_driver __pci_driver = { - .ops = &northbridge_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_APOLLOLAKE_NB +struct sa_map_entry sa_memory_map[MAX_MAP_ENTRIES] = { + [SA_TOUUD_REG] = SA_MAP_ENTRY_BASE_64(TOUUD, "TOUUD"), + [SA_TOLUD_REG] = SA_MAP_ENTRY_BASE_32(TOLUD, "TOLUD"), + [SA_BDSM_REG] = SA_MAP_ENTRY_BASE_32(BDSM, "BDSM"), + [SA_BGSM_REG] = SA_MAP_ENTRY_BASE_32(BGSM, "BGSM"), + [SA_TSEG_REG] = SA_MAP_ENTRY_BASE_32(TSEG, "TESGMB"), +}; + +struct sa_mmio_descriptor sa_imr_resources[SOC_SA_IMR_RESOURCES] = { + { IMR0_BASE, 0, get_base_addr_from_mchbar, "IMR0 BASE" }, + { IMR1_BASE, 0, get_base_addr_from_mchbar, "IMR1 BASE" }, + { IMR2_BASE, 0, get_base_addr_from_mchbar, "IMR2 BASE" }, + { IMR3_BASE, 0, get_base_addr_from_mchbar, "IMR3 BASE" }, + { IMR4_BASE, 0, get_base_addr_from_mchbar, "IMR4 BASE" }, + { IMR5_BASE, 0, get_base_addr_from_mchbar, "IMR5 BASE" }, + { IMR6_BASE, 0, get_base_addr_from_mchbar, "IMR6 BASE" }, + { IMR7_BASE, 0, get_base_addr_from_mchbar, "IMR7 BASE" }, + { IMR8_BASE, 0, get_base_addr_from_mchbar, "IMR8 BASE" }, + { IMR9_BASE, 0, get_base_addr_from_mchbar, "IMR9 BASE" }, + { IMR10_BASE, 0, get_base_addr_from_mchbar, "IMR10 BASE" }, + { IMR11_BASE, 0, get_base_addr_from_mchbar, "IMR11 BASE" }, + { IMR12_BASE, 0, get_base_addr_from_mchbar, "IMR12 BASE" }, + { IMR13_BASE, 0, get_base_addr_from_mchbar, "IMR13 BASE" }, + { IMR14_BASE, 0, get_base_addr_from_mchbar, "IMR14 BASE" }, + { IMR15_BASE, 0, get_base_addr_from_mchbar, "IMR15 BASE" }, + { IMR16_BASE, 0, get_base_addr_from_mchbar, "IMR16 BASE" }, + { IMR17_BASE, 0, get_base_addr_from_mchbar, "IMR17 BASE" }, + { IMR18_BASE, 0, get_base_addr_from_mchbar, "IMR18 BASE" }, + { IMR19_BASE, 0, get_base_addr_from_mchbar, "IMR19 BASE" }, }; diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index aebed9a..82a9ad6 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -31,6 +31,7 @@ #include <fsp/api.h> #include <fsp/memmap.h> #include <fsp/util.h> +#include <intelblocks/systemagent.h> #include <reset.h> #include <soc/cpu.h> #include <soc/intel/common/mrc_cache.h> @@ -80,8 +81,13 @@ */ static void soc_early_romstage_init(void) { - /* Set MCH base address and enable bit */ - pci_write_config32(SA_DEV_ROOT, MCHBAR, MCH_BASE_ADDRESS | 1); + struct sa_set_mmio_descriptor soc_fixed_set_resources[] = { + { MCHBAR, MCH_BASE_ADDRESS, set_base_addr, \ + "MCHBAR"}, + }; + + romstage_systemagent_early_init(soc_fixed_set_resources, + ARRAY_SIZE(soc_fixed_set_resources)); /* Enable decoding for HPET. Needed for FSP global pointer storage */ pci_write_config8(PCH_DEV_P2SB, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 | @@ -140,13 +146,10 @@ * Software Core Disable Mask (P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR). * Enable all cores here. */ - write32((void *)(MCH_BASE_ADDRESS + CORE_DISABLE_MASK), - 0x0); + MCHBAR32(CORE_DISABLE_MASK) = 0x0; - void *bios_rest_cpl = (void *)(MCH_BASE_ADDRESS + - BIOS_RESET_CPL); /* P-Unit bring up */ - reg = read32(bios_rest_cpl); + reg = MCHBAR32(BIOS_RESET_CPL); if (reg == 0xffffffff) { /* P-unit not found */ printk(BIOS_DEBUG, "Punit MMIO not available\n"); @@ -156,24 +159,24 @@ pci_write_config8(SA_DEV_PUNIT, PCI_INTERRUPT_PIN, 0x2); /* Set PUINT IRQ to 24 and INTPIN LOCK */ - write32((void *)(MCH_BASE_ADDRESS + PUNIT_THERMAL_DEVICE_IRQ), - PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER | - PUINT_THERMAL_DEVICE_IRQ_LOCK); + MCHBAR32(PUNIT_THERMAL_DEVICE_IRQ) = + PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER | + PUINT_THERMAL_DEVICE_IRQ_LOCK; - data = read32((void *)(MCH_BASE_ADDRESS + 0x7818)); + data = MCHBAR32(0x7818); data &= 0xFFFFE01F; data |= 0x20 | 0x200; - write32((void *)(MCH_BASE_ADDRESS + 0x7818), data); + MCHBAR32(0x7818) = data; /* Stage0 BIOS Reset Complete (RST_CPL) */ - write32(bios_rest_cpl, 0x1); + enable_bios_reset_cpl(); /* * Poll for bit 8 in same reg (RST_CPL). * We wait here till 1 ms for the bit to get set. */ stopwatch_init_msecs_expire(&sw, 1); - while (!(read32(bios_rest_cpl) & 0x100)) { + while (!(MCHBAR32(BIOS_RESET_CPL) & 0x100)) { if (stopwatch_expired(&sw)) { printk(BIOS_DEBUG, "Failed to set RST_CPL bit\n"); -- To view, visit https://review.coreboot.org/19795 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I15a3b2fc46ec9063b54379d41996b9a1d612cfd2 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/skylake: Use common systemagent code
by Subrata Banik (Code Review) 19 May '17

19 May '17

Subrata Banik has uploaded a new change for review. ( https://review.coreboot.org/19796 ) Change subject: soc/intel/skylake: Use common systemagent code ...................................................................... soc/intel/skylake: Use common systemagent code This patch perform resource mapping for PCI, fixed MMIO, DRAM and IMR's based on inputs given by SoC. TEST=Ensure PCI root bridge 0:0:0 memory resource allocation remains same between previous implementation and current implementation. Change-Id: I93567a79b2d12dd5d6363957e55ce2cb86ff83a7 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/include/soc/systemagent.h M src/soc/intel/skylake/romstage/systemagent.c M src/soc/intel/skylake/systemagent.c 4 files changed, 45 insertions(+), 418 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/19796/1 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 2bfa61c..8cf1cb1 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -48,6 +48,7 @@ select RELOCATABLE_MODULES select RELOCATABLE_RAMSTAGE select RTC + select SA_ENABLE_DPR select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK diff --git a/src/soc/intel/skylake/include/soc/systemagent.h b/src/soc/intel/skylake/include/soc/systemagent.h index 0a82182..0142135 100644 --- a/src/soc/intel/skylake/include/soc/systemagent.h +++ b/src/soc/intel/skylake/include/soc/systemagent.h @@ -95,7 +95,6 @@ #define MCHBAR_PEI_VERSION 0x5034 #define BIOS_RESET_CPL 0x5da8 #define EDRAMBAR 0x5408 -#define MCH_PAIR 0x5418 #define GDXCBAR 0x5420 #define MCH_PKG_POWER_LIMIT_LO 0x59a0 @@ -118,8 +117,6 @@ /* Data is passed through bits 31:0 of the data register. */ #define BIOS_MAILBOX_DATA 0x5da0 -/* System Agent identification */ -u8 systemagent_revision(void); #define SOC_SA_FIXED_RESOURCES 6 enum { diff --git a/src/soc/intel/skylake/romstage/systemagent.c b/src/soc/intel/skylake/romstage/systemagent.c index 2f58db6..aeaeb33 100644 --- a/src/soc/intel/skylake/romstage/systemagent.c +++ b/src/soc/intel/skylake/romstage/systemagent.c @@ -15,38 +15,28 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <arch/io.h> -#include <device/pci_def.h> -#include <reg_script.h> +#include <intelblocks/systemagent.h> #include <soc/iomap.h> -#include <soc/pci_devs.h> #include <soc/romstage.h> #include <soc/systemagent.h> - -static const struct reg_script systemagent_early_init_script[] = { - REG_PCI_WRITE32(MCHBAR, MCH_BASE_ADDRESS | 1), - REG_PCI_WRITE32(DMIBAR, DMI_BASE_ADDRESS | 1), - REG_PCI_WRITE32(EPBAR, EP_BASE_ADDRESS | 1), - REG_MMIO_WRITE32(MCH_BASE_ADDRESS + EDRAMBAR, EDRAM_BASE_ADDRESS | 1), - REG_MMIO_WRITE32(MCH_BASE_ADDRESS + GDXCBAR, GDXC_BASE_ADDRESS | 1), - - /* Set C0000-FFFFF to access RAM on both reads and writes */ - REG_PCI_WRITE8(PAM0, 0x30), - REG_PCI_WRITE8(PAM1, 0x33), - REG_PCI_WRITE8(PAM2, 0x33), - REG_PCI_WRITE8(PAM3, 0x33), - REG_PCI_WRITE8(PAM4, 0x33), - REG_PCI_WRITE8(PAM5, 0x33), - REG_PCI_WRITE8(PAM6, 0x33), - - /* Device enable: IGD and Mini-HD */ - REG_PCI_WRITE32(DEVEN, DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN), - - REG_SCRIPT_END -}; +#include <stdlib.h> void systemagent_early_init(void) { - reg_script_run_on_dev(SA_DEV_ROOT, systemagent_early_init_script); + struct sa_set_mmio_descriptor soc_fixed_set_resources[] = { + { MCHBAR, MCH_BASE_ADDRESS, set_base_addr, \ + "MCHBAR"}, + { DMIBAR, DMI_BASE_ADDRESS, set_base_addr, \ + "DMIBAR"}, + { EPBAR, EP_BASE_ADDRESS, set_base_addr, \ + "EPBAR"}, + { GDXCBAR, GDXC_BASE_ADDRESS, set_base_addr_into_mchbar, \ + "GDXCBAR"}, + { EDRAMBAR, EDRAM_BASE_ADDRESS, set_base_addr_into_mchbar, \ + "EDRAMBAR"}, + }; + + romstage_systemagent_early_init(soc_fixed_set_resources, + ARRAY_SIZE(soc_fixed_set_resources)); } diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c index f15d26e..c4cb51b 100644 --- a/src/soc/intel/skylake/systemagent.c +++ b/src/soc/intel/skylake/systemagent.c @@ -3,7 +3,7 @@ * * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2015-2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,415 +16,54 @@ */ #include <console/console.h> -#include <arch/acpi.h> #include <arch/io.h> #include <stdint.h> #include <delay.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <intelblocks/systemagent.h> #include <stdlib.h> #include <string.h> -#include <cbmem.h> -#include <romstage_handoff.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <soc/cpu.h> #include <soc/iomap.h> #include <soc/pci_devs.h> -#include <soc/ramstage.h> #include <soc/systemagent.h> -u8 systemagent_revision(void) -{ - return pci_read_config8(SA_DEV_ROOT, PCI_REVISION_ID); -} - -static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) -{ - u32 pciexbar_reg; - - *base = 0; - *len = 0; - - pciexbar_reg = pci_read_config32(dev, index); - - if (!(pciexbar_reg & (1 << 0))) - return 0; - - switch ((pciexbar_reg >> 1) & 3) { - case 0: /* 256MB */ - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)| - (1 << 28)); - *len = 256 * 1024 * 1024; - return 1; - case 1: /* 128M */ - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)| - (1 << 28)|(1 << 27)); - *len = 128 * 1024 * 1024; - return 1; - case 2: /* 64M */ - *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)| - (1 << 28)|(1 << 27)|(1 << 26)); - *len = 64 * 1024 * 1024; - return 1; - } - - return 0; -} - -static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len) -{ - u32 bar; - - bar = pci_read_config32(dev, index); - - /* If not enabled don't report it. */ - if (!(bar & 0x1)) - return 0; - - /* Knock down the enable bit. */ - *base = bar & ~1; - - return 1; -} - -/* - * There are special BARs that actually are programmed in the MCHBAR. These - * Intel special features, but they do consume resources that need to be - * accounted for. - */ -static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base, - u32 *len) -{ - u32 bar; - - bar = MCHBAR32(index); - - /* If not enabled don't report it. */ - if (!(bar & 0x1)) - return 0; - - /* Knock down the enable bit. */ - *base = bar & ~1; - - return 1; -} - -struct fixed_mmio_descriptor { - unsigned int index; - u32 size; - int (*get_resource)(device_t dev, unsigned int index, - u32 *base, u32 *size); - const char *description; +struct sa_mmio_descriptor sa_fixed_resources[SOC_SA_FIXED_RESOURCES] = { + { PCIEXBAR, 0, get_pcie_base_addr, "PCIEXBAR" }, + { MCHBAR, MCH_BASE_SIZE, get_base_addr, "MCHBAR" }, + { DMIBAR, DMI_BASE_SIZE, get_base_addr, "DMIBAR" }, + { EPBAR, EP_BASE_SIZE, get_base_addr, "EPBAR" }, + { GDXCBAR, GDXC_BASE_SIZE, get_base_addr_from_mchbar, "GDXCBAR" }, + { EDRAMBAR, EDRAM_BASE_SIZE, get_base_addr_from_mchbar, "EDRAMBAR" }, }; -struct fixed_mmio_descriptor mc_fixed_resources[] = { - { PCIEXBAR, 0, get_pcie_bar, "PCIEXBAR" }, - { MCHBAR, MCH_BASE_SIZE, get_bar, "MCHBAR" }, - { DMIBAR, DMI_BASE_SIZE, get_bar, "DMIBAR" }, - { EPBAR, EP_BASE_SIZE, get_bar, "EPBAR" }, - { GDXCBAR, GDXC_BASE_SIZE, get_bar_in_mchbar, "GDXCBAR" }, - { EDRAMBAR, EDRAM_BASE_SIZE, get_bar_in_mchbar, "EDRAMBAR" }, +struct sa_map_entry sa_memory_map[MAX_MAP_ENTRIES] = { + [SA_TOM_REG] = SA_MAP_ENTRY_BASE_64(TOM, "TOM"), + [SA_TOUUD_REG] = SA_MAP_ENTRY_BASE_64(TOUUD, "TOUUD"), + [SA_MESEG_BASE_REG] = SA_MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"), + [SA_MESEG_LIMIT_REG] = SA_MAP_ENTRY_LIMIT_64(MESEG_LIMIT, \ + "MESEG_LIMIT"), + [SA_REMAP_BASE_REG] = SA_MAP_ENTRY_BASE_64(REMAPBASE, \ + "REMAP_BASE"), + [SA_REMAP_LIMIT_REG] = SA_MAP_ENTRY_LIMIT_64(REMAPLIMIT, \ + "REMAP_LIMIT"), + [SA_TOLUD_REG] = SA_MAP_ENTRY_BASE_32(TOLUD, "TOLUD"), + [SA_BDSM_REG] = SA_MAP_ENTRY_BASE_32(BDSM, "BDSM"), + [SA_BGSM_REG] = SA_MAP_ENTRY_BASE_32(BGSM, "BGSM"), + [SA_TSEG_REG] = SA_MAP_ENTRY_BASE_32(TSEG, "TESGMB"), }; -/* - * Add all known fixed MMIO ranges that hang off the host bridge/memory - * controller device. - */ -static void mc_add_fixed_mmio_resources(device_t dev) +void soc_systemagent_init(struct device *dev) { - int i; - - for (i = 0; i < ARRAY_SIZE(mc_fixed_resources); i++) { - u32 base; - u32 size; - struct resource *resource; - unsigned int index; - - size = mc_fixed_resources[i].size; - index = mc_fixed_resources[i].index; - if (!mc_fixed_resources[i].get_resource(dev, index, - &base, &size)) - continue; - - resource = new_resource(dev, mc_fixed_resources[i].index); - resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | - IORESOURCE_STORED | IORESOURCE_RESERVE | - IORESOURCE_ASSIGNED; - resource->base = base; - resource->size = size; - printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n", - __func__, mc_fixed_resources[i].description, index, - (unsigned long)base, (unsigned long)(base + size - 1)); - } -} - -struct map_entry { - int reg; - int is_64_bit; - int is_limit; - const char *description; -}; - -static void read_map_entry(device_t dev, struct map_entry *entry, - uint64_t *result) -{ - uint64_t value; - uint64_t mask; - - /* All registers are on a 1MiB granularity. */ - mask = ((1ULL<<20)-1); - mask = ~mask; - - value = 0; - - if (entry->is_64_bit) { - value = pci_read_config32(dev, entry->reg + 4); - value <<= 32; - } - - value |= (uint64_t) pci_read_config32(dev, entry->reg); - value &= mask; - - if (entry->is_limit) - value |= ~mask; - - *result = value; -} - -#define MAP_ENTRY(reg_, is_64_, is_limit_, desc_) \ - { \ - .reg = reg_, \ - .is_64_bit = is_64_, \ - .is_limit = is_limit_, \ - .description = desc_, \ - } - -#define MAP_ENTRY_BASE_64(reg_, desc_) \ - MAP_ENTRY(reg_, 1, 0, desc_) -#define MAP_ENTRY_LIMIT_64(reg_, desc_) \ - MAP_ENTRY(reg_, 1, 1, desc_) -#define MAP_ENTRY_BASE_32(reg_, desc_) \ - MAP_ENTRY(reg_, 0, 0, desc_) - -enum { - TOM_REG, - TOUUD_REG, - MESEG_BASE_REG, - MESEG_LIMIT_REG, - REMAP_BASE_REG, - REMAP_LIMIT_REG, - TOLUD_REG, - BGSM_REG, - BDSM_REG, - TSEG_REG, - /* Must be last. */ - NUM_MAP_ENTRIES -}; - -static struct map_entry memory_map[NUM_MAP_ENTRIES] = { - [TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"), - [TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"), - [MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"), - [MESEG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(MESEG_LIMIT, "MESEG_LIMIT"), - [REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"), - [REMAP_LIMIT_REG] = MAP_ENTRY_LIMIT_64(REMAPLIMIT, "REMAP_LIMIT"), - [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"), - [BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"), - [BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"), - [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"), -}; - -static void mc_read_map_entries(device_t dev, uint64_t *values) -{ - int i; - for (i = 0; i < NUM_MAP_ENTRIES; i++) - read_map_entry(dev, &memory_map[i], &values[i]); -} - -static void mc_report_map_entries(device_t dev, uint64_t *values) -{ - int i; - for (i = 0; i < NUM_MAP_ENTRIES; i++) { - printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n", - memory_map[i].description, values[i]); - } - /* One can validate the BDSM and BGSM against the GGC. */ - printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); -} - -static void mc_add_dram_resources(device_t dev) -{ - unsigned long base_k, size_k; - unsigned long touud_k; - unsigned long index; - struct resource *resource; - uint64_t mc_values[NUM_MAP_ENTRIES]; - unsigned long dpr_size = 0; - u32 dpr_reg; - - /* Read in the MAP registers and report their values. */ - mc_read_map_entries(dev, &mc_values[0]); - mc_report_map_entries(dev, &mc_values[0]); - - /* - * DMA Protected Range can be reserved below TSEG for PCODE patch - * or TXT/BootGuard related data. Rather than report a base address - * the DPR register reports the TOP of the region, which is the same - * as TSEG base. The region size is reported in MiB in bits 11:4. - */ - dpr_reg = pci_read_config32(SA_DEV_ROOT, DPR); - if (dpr_reg & DPR_EPM) { - dpr_size = (dpr_reg & DPR_SIZE_MASK) << 16; - printk(BIOS_INFO, "DPR SIZE: 0x%lx\n", dpr_size); - } - - /* - * These are the host memory ranges that should be added: - * - 0 -> 0xa0000: cacheable - * - 0xc0000 -> top_of_ram : cacheable - * - top_of_ram -> TSEG - DPR: uncacheable - * - TESG - DPR -> BGSM: cacheable with standard MTRRs and reserved - * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved - * - 4GiB -> TOUUD: cacheable - * - * The default SMRAM space is reserved so that the range doesn't - * have to be saved during S3 Resume. Once marked reserved the OS - * cannot use the memory. This is a bit of an odd place to reserve - * the region, but the CPU devices don't have dev_ops->read_resources() - * called on them. - * - * The range 0xa0000 -> 0xc0000 does not have any resources - * associated with it to handle legacy VGA memory. If this range - * is not omitted the mtrr code will setup the area as cacheable - * causing VGA access to not work. - * - * The TSEG region is mapped as cacheable so that one can perform - * SMRAM relocation faster. Once the SMRR is enabled the SMRR takes - * precedence over the existing MTRRs covering this region. - * - * It should be noted that cacheable entry types need to be added in - * order. The reason is that the current MTRR code assumes this and - * falls over itself if it isn't. - * - * The resource index starts low and should not meet or exceed - * PCI_BASE_ADDRESS_0. - */ - index = 0; - - /* 0 - > 0xa0000 */ - base_k = 0; - size_k = (0xa0000 >> 10) - base_k; - ram_resource(dev, index++, base_k, size_k); - - /* 0xc0000 -> top_of_ram */ - base_k = 0xc0000 >> 10; - size_k = (top_of_32bit_ram() >> 10) - base_k; - ram_resource(dev, index++, base_k, size_k); - - /* top_of_ram -> TSEG - DPR */ - resource = new_resource(dev, index++); - resource->base = top_of_32bit_ram(); - resource->size = mc_values[TSEG_REG] - dpr_size - resource->base; - resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | - IORESOURCE_STORED | IORESOURCE_RESERVE | - IORESOURCE_ASSIGNED; - - /* TSEG - DPR -> BGSM */ - resource = new_resource(dev, index++); - resource->base = mc_values[TSEG_REG] - dpr_size; - resource->size = mc_values[BGSM_REG] - resource->base; - resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | - IORESOURCE_STORED | IORESOURCE_RESERVE | - IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE; - - /* BGSM -> TOLUD */ - resource = new_resource(dev, index++); - resource->base = mc_values[BGSM_REG]; - resource->size = mc_values[TOLUD_REG] - resource->base; - resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | - IORESOURCE_STORED | IORESOURCE_RESERVE | - IORESOURCE_ASSIGNED; - - /* 4GiB -> TOUUD */ - base_k = 4096 * 1024; /* 4GiB */ - touud_k = mc_values[TOUUD_REG] >> 10; - size_k = touud_k - base_k; - if (touud_k > base_k) - ram_resource(dev, index++, base_k, size_k); - - /* - * Reserve everything between A segment and 1MB: - * - * 0xa0000 - 0xbffff: legacy VGA - * 0xc0000 - 0xfffff: RAM - */ - mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); - reserved_ram_resource(dev, index++, (0xc0000 >> 10), - (0x100000 - 0xc0000) >> 10); - - chromeos_reserve_ram_oops(dev, index++); -} - -static void systemagent_read_resources(device_t dev) -{ - /* Read standard PCI resources. */ - pci_dev_read_resources(dev); - - /* Add all fixed MMIO resources. */ - mc_add_fixed_mmio_resources(dev); - - /* Calculate and add DRAM resources. */ - mc_add_dram_resources(dev); -} - -static void systemagent_init(struct device *dev) -{ - u8 bios_reset_cpl, pair; - /* Enable Power Aware Interrupt Routing */ - pair = MCHBAR8(MCH_PAIR); - pair &= ~0x7; /* Clear 2:0 */ - pair |= 0x4; /* Fixed Priority */ - MCHBAR8(MCH_PAIR) = pair; + enable_power_aware_intr(); - /* - * Set bits 0+1 of BIOS_RESET_CPL to indicate to the CPU - * that BIOS has initialized memory and power management - */ - bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL); - bios_reset_cpl |= 3; - MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl; - printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); + /* Enable BIOS Reset CPL */ + enable_bios_reset_cpl(); /* Configure turbo power limits 1ms after reset complete bit */ mdelay(1); set_power_limits(28); } - -static struct device_operations systemagent_ops = { - .read_resources = &systemagent_read_resources, - .set_resources = &pci_dev_set_resources, - .enable_resources = &pci_dev_enable_resources, - .init = &systemagent_init, - .ops_pci = &soc_pci_ops, -}; - -static const unsigned short systemagent_ids[] = { - MCH_SKYLAKE_ID_U, - MCH_SKYLAKE_ID_Y, - MCH_SKYLAKE_ID_ULX, - MCH_SKYLAKE_ID_H, - MCH_SKYLAKE_ID_H_EM, - MCH_KABYLAKE_ID_U, - MCH_KABYLAKE_ID_U_R, - MCH_KABYLAKE_ID_Y, - MCH_KABYLAKE_ID_H, - 0 -}; - -static const struct pci_driver systemagent_driver __pci_driver = { - .ops = &systemagent_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = systemagent_ids -}; -- To view, visit https://review.coreboot.org/19796 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I93567a79b2d12dd5d6363957e55ce2cb86ff83a7 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: src/include/device: Add System Agent (SA) device ids
by Subrata Banik (Code Review) 19 May '17

19 May '17

Subrata Banik has uploaded a new change for review. ( https://review.coreboot.org/19794 ) Change subject: src/include/device: Add System Agent (SA) device ids ...................................................................... src/include/device: Add System Agent (SA) device ids Change-Id: Iddc9f8187d1ff4a51bf3bf42a266b79007c42f3b Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/include/device/pci_ids.h 1 file changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/19794/1 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 5a2e1b2..c4123d0 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2796,7 +2796,17 @@ #define PCI_DEVICE_ID_INTEL_APL_IGD_HD_500 0x5a85 /* Intel Northbridge Ids */ -#define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0 +#define PCI_DEVICE_ID_INTEL_GLK_NB 0x31f0 +#define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0 +#define PCI_DEVICE_ID_INTE_SKL_ID_U 0x1904 +#define PCI_DEVICE_ID_INTE_SKL_ID_Y 0x190c +#define PCI_DEVICE_ID_INTE_SKL_ID_ULX 0x1924 +#define PCI_DEVICE_ID_INTE_SKL_ID_H 0x1910 +#define PCI_DEVICE_ID_INTE_SKL_ID_H_EM 0x1918 +#define PCI_DEVICE_ID_INTE_KBL_ID_U 0x5904 +#define PCI_DEVICE_ID_INTE_KBL_ID_Y 0x590c +#define PCI_DEVICE_ID_INTE_KBL_ID_H 0x5910 +#define PCI_DEVICE_ID_INTE_KBL_U_R 0x5914 /* Intel SMBUS device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23 -- To view, visit https://review.coreboot.org/19794 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Iddc9f8187d1ff4a51bf3bf42a266b79007c42f3b Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/apollolake: Use MCH_BASE_ADDRESS macro for APL
by Subrata Banik (Code Review) 19 May '17

19 May '17

Subrata Banik has uploaded a new change for review. ( https://review.coreboot.org/19793 ) Change subject: soc/intel/apollolake: Use MCH_BASE_ADDRESS macro for APL ...................................................................... soc/intel/apollolake: Use MCH_BASE_ADDRESS macro for APL Systemagent common code will use MCH_BASE_ADDRESS macro, hence cleaning current APL code to adhere such changes. Change-Id: Iace1cf786b08221c3955101186509ac5161c3841 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/apollolake/acpi/pmc_ipc.asl M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/include/soc/iomap.h M src/soc/intel/apollolake/include/soc/systemagent.h M src/soc/intel/apollolake/romstage.c 5 files changed, 17 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/19793/1 diff --git a/src/soc/intel/apollolake/acpi/pmc_ipc.asl b/src/soc/intel/apollolake/acpi/pmc_ipc.asl index c958c16..cb151bd 100644 --- a/src/soc/intel/apollolake/acpi/pmc_ipc.asl +++ b/src/soc/intel/apollolake/acpi/pmc_ipc.asl @@ -47,9 +47,9 @@ Store (PMC_BAR0, IBAS) CreateDwordField (^RBUF, ^MDAT._BAS, MDBA) - Store (MCH_BASE_ADDR + MAILBOX_DATA, MDBA) + Store (MCH_BASE_ADDRESS + MAILBOX_DATA, MDBA) CreateDwordField (^RBUF, ^MINF._BAS, MIBA) - Store (MCH_BASE_ADDR + MAILBOX_INTF, MIBA) + Store (MCH_BASE_ADDRESS + MAILBOX_INTF, MIBA) CreateDwordField (^RBUF, ^SBAR._BAS, SBAS) Store (PMC_SRAM_BASE_0, SBAS) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 5211f84..da60827 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -273,7 +273,8 @@ 100 * (pl2_val % power_unit) / power_unit); /* Get the MMIO address */ - rapl_mmio_reg = (void *)(uintptr_t) (MCH_BASE_ADDR + MCHBAR_RAPL_PPL); + rapl_mmio_reg = (void *)(uintptr_t) (MCH_BASE_ADDRESS + + MCHBAR_RAPL_PPL); /* Setting RAPL MMIO register for Power limits. * RAPL driver is using MSR instead of MMIO. diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index eab1273..0b52095 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -22,14 +22,8 @@ #define P2SB_BAR CONFIG_PCR_BASE_ADDRESS #define P2SB_SIZE (16 * MiB) -#define MCH_BASE_ADDR 0xfed10000 +#define MCH_BASE_ADDRESS 0xfed10000 #define MCH_BASE_SIZE (32 * KiB) - -#define P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR 0x7168 -#define P_CR_BIOS_RESET_CPL_0_0_0_MCHBAR 0x7078 -#define PUNIT_THERMAL_DEVICE_IRQ 0x700C -#define PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER 0x18 -#define PUINT_THERMAL_DEVICE_IRQ_LOCK 0x80000000 #define ACPI_PMIO_BASE 0x400 #define ACPI_PMIO_SIZE 0x100 diff --git a/src/soc/intel/apollolake/include/soc/systemagent.h b/src/soc/intel/apollolake/include/soc/systemagent.h index 9944c15..6b423db 100644 --- a/src/soc/intel/apollolake/include/soc/systemagent.h +++ b/src/soc/intel/apollolake/include/soc/systemagent.h @@ -27,6 +27,11 @@ #define MCH_NUM_IMRS 20 /* RAPL Package Power Limit register under MCHBAR. */ +#define PUNIT_THERMAL_DEVICE_IRQ 0x700C +#define PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER 0x18 +#define PUINT_THERMAL_DEVICE_IRQ_LOCK 0x80000000 +#define BIOS_RESET_CPL 0x7078 #define MCHBAR_RAPL_PPL 0x70A8 +#define CORE_DISABLE_MASK 0x7168 #endif /* SOC_APOLLOLAKE_SYSTEMAGENT_H */ diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 39d3989..aebed9a 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -81,7 +81,7 @@ static void soc_early_romstage_init(void) { /* Set MCH base address and enable bit */ - pci_write_config32(SA_DEV_ROOT, MCHBAR, MCH_BASE_ADDR | 1); + pci_write_config32(SA_DEV_ROOT, MCHBAR, MCH_BASE_ADDRESS | 1); /* Enable decoding for HPET. Needed for FSP global pointer storage */ pci_write_config8(PCH_DEV_P2SB, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 | @@ -140,11 +140,11 @@ * Software Core Disable Mask (P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR). * Enable all cores here. */ - write32((void *)(MCH_BASE_ADDR + P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR), + write32((void *)(MCH_BASE_ADDRESS + CORE_DISABLE_MASK), 0x0); - void *bios_rest_cpl = (void *)(MCH_BASE_ADDR + - P_CR_BIOS_RESET_CPL_0_0_0_MCHBAR); + void *bios_rest_cpl = (void *)(MCH_BASE_ADDRESS + + BIOS_RESET_CPL); /* P-Unit bring up */ reg = read32(bios_rest_cpl); if (reg == 0xffffffff) { @@ -156,14 +156,14 @@ pci_write_config8(SA_DEV_PUNIT, PCI_INTERRUPT_PIN, 0x2); /* Set PUINT IRQ to 24 and INTPIN LOCK */ - write32((void *)(MCH_BASE_ADDR + PUNIT_THERMAL_DEVICE_IRQ), + write32((void *)(MCH_BASE_ADDRESS + PUNIT_THERMAL_DEVICE_IRQ), PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER | PUINT_THERMAL_DEVICE_IRQ_LOCK); - data = read32((void *)(MCH_BASE_ADDR + 0x7818)); + data = read32((void *)(MCH_BASE_ADDRESS + 0x7818)); data &= 0xFFFFE01F; data |= 0x20 | 0x200; - write32((void *)(MCH_BASE_ADDR + 0x7818), data); + write32((void *)(MCH_BASE_ADDRESS + 0x7818), data); /* Stage0 BIOS Reset Complete (RST_CPL) */ write32(bios_rest_cpl, 0x1); -- To view, visit https://review.coreboot.org/19793 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Iace1cf786b08221c3955101186509ac5161c3841 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/common/block: Add Intel common systemagent support
by Subrata Banik (Code Review) 19 May '17

19 May '17

Hello V Sowmya, I'd like you to reexamine a change. Please visit https://review.coreboot.org/19668 to look at the new patch set (#2). Change subject: soc/intel/common/block: Add Intel common systemagent support ...................................................................... soc/intel/common/block: Add Intel common systemagent support Add Intel common systemagent support for romstage and ramstage. Include soc specific macros need to compile stemagent common code. Change-Id: I969ff187e3d4199864cb2e9c9a13f4d04158e27c Signed-off-by: V Sowmya <v.sowmya(a)intel.com> Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/apollolake/include/soc/systemagent.h M src/soc/intel/common/block/include/intelblocks/systemagent.h M src/soc/intel/common/block/systemagent/Kconfig M src/soc/intel/common/block/systemagent/Makefile.inc M src/soc/intel/common/block/systemagent/systemagent.c A src/soc/intel/common/block/systemagent/systemagent_early.c M src/soc/intel/skylake/include/soc/systemagent.h 7 files changed, 688 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/19668/2 -- To view, visit https://review.coreboot.org/19668 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I969ff187e3d4199864cb2e9c9a13f4d04158e27c Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/common/block: Add GLK I2C PCI IDs
by build bot (Jenkins) (Code Review) 19 May '17

19 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19782 ) Change subject: soc/intel/common/block: Add GLK I2C PCI IDs ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9752/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54015/ : SUCCESS -- To view, visit https://review.coreboot.org/19782 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I2144199345e6382984c367f6a77f0cbb0a93daea Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: Kconfig: Rework MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG
by build bot (Jenkins) (Code Review) 19 May '17

19 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19791 ) Change subject: Kconfig: Rework MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9751/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54014/ : SUCCESS -- To view, visit https://review.coreboot.org/19791 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I2d9d09be9aa6d019e77460e69a245ad2d8cda4ea Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: Kconfig: Rework MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG
by build bot (Jenkins) (Code Review) 19 May '17

19 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19791 ) Change subject: Kconfig: Rework MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9750/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54013/ : SUCCESS -- To view, visit https://review.coreboot.org/19791 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I2d9d09be9aa6d019e77460e69a245ad2d8cda4ea Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/x4x/raminit: Rework receive enable calibration
by Arthur Heymans (Code Review) 19 May '17

19 May '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/18692 ) Change subject: nb/intel/x4x/raminit: Rework receive enable calibration ...................................................................... Patch Set 20: (4 comments) https://review.coreboot.org/#/c/18692/20/src/northbridge/intel/x4x/rcven.c File src/northbridge/intel/x4x/rcven.c: PS20, Line 49: MCHBAR8(0x9d8) = MCHBAR8(0x9d8) & ~0x2; : udelay(2); : MCHBAR8(0x9d8) = MCHBAR8(0x9d8) | 0x2; : udelay(2); > Looks like `0x400 * channel + 0x5d8`, shouldn't matter, though it I'll try without. it could provide a speed up. Line 54: strobe = read32((u32 *)addr); > i945 repeats the memory access but not the whole sequence, maybe I'll try. PS20, Line 56: MCHBAR32(sample_offset) > Unaligned access, not sure if it can cause any trouble. it could just I use MCHBAR8 I suppose. PS20, Line 319: timing[lane].coarse = (s->selected_timings.CAS - 1) pineview which is a quite similar memory controller starts at CAS + 1, and so does gm45. Maybe this helps with those false results? -- To view, visit https://review.coreboot.org/18692 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I0c970455e609d3ce96a262cbf110336a2079da4d Gerrit-PatchSet: 20 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-HasComments: Yes

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Change in coreboot[master]: nb/intel/x4x/raminit: Rework receive enable calibration
by build bot (Jenkins) (Code Review) 19 May '17

19 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18692 ) Change subject: nb/intel/x4x/raminit: Rework receive enable calibration ...................................................................... Patch Set 20: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/9749/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54012/ : SUCCESS -- To view, visit https://review.coreboot.org/18692 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I0c970455e609d3ce96a262cbf110336a2079da4d Gerrit-PatchSet: 20 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-HasComments: No

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