coreboot-gerrit May 2017

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Change in coreboot[master]: mainboard/google/poppy: Add PowerResource for touchscreen de...
by Duncan Laurie (Code Review) 23 May '17

23 May '17

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/19829 ) Change subject: mainboard/google/poppy: Add PowerResource for touchscreen device ...................................................................... Patch Set 1: Code-Review+2 Did we ever figure out how to handle the wacom firmware updater? -- To view, visit https://review.coreboot.org/19829 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ia0bebc7259b10cc60a9fa5b53542dfdd9685663e Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Implement GPIO ACPI AML generating functions
by Duncan Laurie (Code Review) 23 May '17

23 May '17

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/19828 ) Change subject: soc/intel/skylake: Implement GPIO ACPI AML generating functions ...................................................................... Patch Set 1: Code-Review+2 (1 comment) https://review.coreboot.org/#/c/19828/1/src/soc/intel/skylake/acpi.c File src/soc/intel/skylake/acpi.c: Line 713: maybe delete this blank line, or add one to the above function, just so they are consistent -- To view, visit https://review.coreboot.org/19828 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I77e5d0decd8929a922d06b02312378f092551667 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-HasComments: Yes

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Change in coreboot[master]: sb/intel/bd82x6x: Disable unused bridges
by Arthur Heymans (Code Review) 23 May '17

23 May '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/19818 ) Change subject: sb/intel/bd82x6x: Disable unused bridges ...................................................................... Patch Set 3: Code-Review+2 > > On my x200/ICH9 all SB PCIe functions seem to support hotplug. > > How is the situation on bd82x6x? > > All ports support hotplug. But you won't use all of them. For that > reason you can select which of them are used (for Express card) by > using a devicetree array. On my board with current devixetree, no > ports would be disabled as two are in use and one is marked hotplug > let. It's only useful if you remove on the PCIe devices (like WiFi > card). wups, I missed that. This is good default behavior, people wanting to change it can modify devicetree. -- To view, visit https://review.coreboot.org/19818 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I6ee5e5f33824acdbca0f6ed28e90beab7fe10002 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: [WIP]Use CPU common code
by Subrata Banik (Code Review) 23 May '17

23 May '17

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/19827 ) Change subject: soc/intel/apollolake: [WIP]Use CPU common code ...................................................................... Patch Set 2: (3 comments) https://review.coreboot.org/#/c/19827/2/src/soc/intel/apollolake/Makefile.i… File src/soc/intel/apollolake/Makefile.inc: PS2, Line 97: CPPFLAGS_common += -I$(src)/soc/intel/apollolake why we need this https://review.coreboot.org/#/c/19827/2/src/soc/intel/apollolake/include/so… File src/soc/intel/apollolake/include/soc/cpu.h: PS2, Line 33: define BASE_CLOCK_MHZ 100 bclk is there at common code PS2, Line 39: #define APL_BURST_MODE_DISABLE 0x40 already there -- To view, visit https://review.coreboot.org/19827 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I529c67cf20253cf819d1c13849300788104b083c Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: Yes

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Change in coreboot[master]: mainboard/google/poppy: Add PowerResource for touchscreen de...
by Furquan Shaikh (Code Review) 23 May '17

23 May '17

Furquan Shaikh has uploaded a new change for review. ( https://review.coreboot.org/19829 ) Change subject: mainboard/google/poppy: Add PowerResource for touchscreen device ...................................................................... mainboard/google/poppy: Add PowerResource for touchscreen device 1. Do not enable touchscreen device by default in gpio configuration. 2. Select use of PowerResource for touchscreen device in devicetree so that the ACPI subsystem can take care of powering on/off the device. BUG=b:62028489 TEST=Verified 100 cycles of suspend-resume. Touchscreen still works on poppy. Change-Id: Ia0bebc7259b10cc60a9fa5b53542dfdd9685663e Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/gpio.c M src/mainboard/google/poppy/variants/soraka/devicetree.cb 3 files changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/19829/1 diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index 4e3ffaf..51dadda 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -210,6 +210,10 @@ register "desc" = ""Atmel Touchscreen"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "probed" = "1" + register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)" + register "enable_delay_ms" = "250" device i2c 4b on end end end # I2C #0 diff --git a/src/mainboard/google/poppy/variants/baseboard/gpio.c b/src/mainboard/google/poppy/variants/baseboard/gpio.c index 2be9d0f..a865193 100644 --- a/src/mainboard/google/poppy/variants/baseboard/gpio.c +++ b/src/mainboard/google/poppy/variants/baseboard/gpio.c @@ -174,7 +174,7 @@ /* C21 : UART2_TXD ==> PCHTX_SERVORX_UART */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* C22 : UART2_RTS# ==> EN_PP3300_DX_TOUCHSCREEN */ - PAD_CFG_GPO(GPP_C22, 1, DEEP), + PAD_CFG_GPO(GPP_C22, 0, DEEP), /* C23 : UART2_CTS# ==> PCH_WP */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 39739e8..4197437 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -210,6 +210,10 @@ register "desc" = ""Atmel Touchscreen"" register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" register "probed" = "1" + register "has_power_resource" = "1" + register "disable_gpio_export_in_crs" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C22)" + register "enable_delay_ms" = "250" device i2c 4b on end end end # I2C #0 -- To view, visit https://review.coreboot.org/19829 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Ia0bebc7259b10cc60a9fa5b53542dfdd9685663e Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: soc/intel/skylake: Implement GPIO ACPI AML generating functions
by Furquan Shaikh (Code Review) 23 May '17

23 May '17

Furquan Shaikh has uploaded a new change for review. ( https://review.coreboot.org/19828 ) Change subject: soc/intel/skylake: Implement GPIO ACPI AML generating functions ...................................................................... soc/intel/skylake: Implement GPIO ACPI AML generating functions Implement GPIO ACPI AML generating functions that can be called by coreboot drivers to generate GPIO manipulation code in AML. Following API functions are implemented: 1. acpigen_soc_read_rx_gpio 2. acpigen_soc_get_tx_gpio 3. acpigen_soc_set_tx_gpio 4. acpigen_soc_clear_tx_gpio In addition to the API functions above, helper functions are added to gpio.asl to set/clear/get Tx value of GPIO. BUG=b:62028489 Change-Id: I77e5d0decd8929a922d06b02312378f092551667 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/acpi/gpio.asl 2 files changed, 83 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/19828/1 diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 64438bd..f83bf75 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -695,3 +695,41 @@ return NULL; } + +static int acpigen_soc_gpio_op(const char *op, unsigned int gpio_num) +{ + /* op (gpio_num) */ + acpigen_emit_namestring(op); + acpigen_write_integer(gpio_num); + return 0; +} + +static int acpigen_soc_get_gpio_state(const char *op, unsigned int gpio_num) +{ + /* Store (op (gpio_num), Local0) */ + acpigen_write_store(); + acpigen_soc_gpio_op(op, gpio_num); + acpigen_emit_byte(LOCAL0_OP); + + return 0; +} + +int acpigen_soc_read_rx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_get_gpio_state("\\_SB.PCI0.GRXS", gpio_num); +} + +int acpigen_soc_get_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_get_gpio_state("\\_SB.PCI0.GTXS", gpio_num); +} + +int acpigen_soc_set_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_gpio_op("\\_SB.PCI0.STXS", gpio_num); +} + +int acpigen_soc_clear_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_gpio_op("\\_SB.PCI0.CTXS", gpio_num); +} diff --git a/src/soc/intel/skylake/acpi/gpio.asl b/src/soc/intel/skylake/acpi/gpio.asl index 0c5a793..fb22095 100644 --- a/src/soc/intel/skylake/acpi/gpio.asl +++ b/src/soc/intel/skylake/acpi/gpio.asl @@ -120,7 +120,7 @@ } /* - * Get GPIO Value + * Get GPIO Rx Value * Arg0 - GPIO Number */ Method (GRXS, 1, Serialized) @@ -134,3 +134,47 @@ Return (Local0) } + +/* + * Get GPIO Tx Value + * Arg0 - GPIO Number + */ +Method (GTXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + And (GPIOTXSTATE_MASK, ShiftRight (VAL0, GPIOTXSTATE_SHIFT), Local0) + + Return (Local0) +} + +/* + * Set GPIO Tx Value + * Arg0 - GPIO Number + */ +Method (STXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + Or (GPIOTXSTATE_MASK, VAL0, VAL0) +} + +/* + * Clear GPIO Tx Value + * Arg0 - GPIO Number + */ +Method (CTXS, 1, Serialized) +{ + OperationRegion (PREG, SystemMemory, GADD (Arg0), 4) + Field (PREG, AnyAcc, NoLock, Preserve) + { + VAL0, 32 + } + And (Not (GPIOTXSTATE_MASK), VAL0, VAL0) +} -- To view, visit https://review.coreboot.org/19828 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I77e5d0decd8929a922d06b02312378f092551667 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: soc/intel/skylake: [WIP]Use CPU common code
by Subrata Banik (Code Review) 23 May '17

23 May '17

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/19566 ) Change subject: soc/intel/skylake: [WIP]Use CPU common code ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/#/c/19566/6/src/soc/intel/skylake/bootblock/rep… File src/soc/intel/skylake/bootblock/report_platform.c: PS6, Line 23: #include <intelblocks/cpu.h> order -- To view, visit https://review.coreboot.org/19566 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I6af56564c6f488f58173ba0beda6912763706f9f Gerrit-PatchSet: 6 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/common/block: [WIP]Add Intel common CPU code
by Subrata Banik (Code Review) 23 May '17

23 May '17

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/19540 ) Change subject: soc/intel/common/block: [WIP]Add Intel common CPU code ...................................................................... Patch Set 8: (20 comments) https://review.coreboot.org/#/c/19540/8/src/soc/intel/common/block/cpu/Kcon… File src/soc/intel/common/block/cpu/Kconfig: PS8, Line 4: Intel Common CPU Model Support. can you please add little bit more like below. https://review.coreboot.org/#/c/19540/8/src/soc/intel/common/block/cpu/cpu.c File src/soc/intel/common/block/cpu/cpu.c: PS8, Line 18: #include <assert.h> : #include <bootstate.h> : #include <console/console.h> : #include <cpu/cpu.h> : #include <cpu/x86/mtrr.h> : #include <cpu/x86/msr.h> : #include <cpu/x86/lapic.h> : #include <cpu/x86/mp.h> : #include <cpu/intel/microcode.h> : #include <cpu/intel/speedstep.h> : #include <cpu/intel/turbo.h> : #include <cpu/x86/cache.h> : #include <cpu/x86/name.h> : #include <cpu/x86/smm.h> : #include <delay.h> : #include <device/device.h> : #include <device/pci.h> : #include <intelblocks/cpu.h> : #include <intelblocks/msr.h> : #include <intelblocks/smm.h> : #include <pc80/mc146818rtc.h> : #include <soc/cpu.h> : #include <soc/pci_devs.h> : #include <soc/systemagent.h> : #include <string.h> let see if we can optimize this PS8, Line 48: : eax = cpuid_eax(CPUID_LEAF_PM); : : msr = rdmsr(MSR_IA32_MISC_ENABLES); : eax &= 0x2; : if ((!eax) && ((msr.hi & BURST_MODE_DISABLE) == 0)) { : /* Burst Mode has been factory configured as disabled : * and is not available in this physical processor : * package. : */ : printk(BIOS_DEBUG, "Burst Mode is factory disabled\n"); : return; : } : : /* Enable burst mode */ : msr.hi &= ~BURST_MODE_DISABLE; : wrmsr(MSR_IA32_MISC_ENABLES, msr); can this be put into a function and call as enable/disable turbo for romstage as i understood you don't want to use turbo.c file which gets included in ramstage PS8, Line 66: /* Enable speed step. */ : msr = rdmsr(MSR_IA32_MISC_ENABLES); : msr.lo |= 1 << 16; : wrmsr(MSR_IA32_MISC_ENABLES, msr); make as function so, mp init feature programming can use this. https://review.coreboot.org/#/c/19540/8/src/soc/intel/common/block/cpu/cpu_… File src/soc/intel/common/block/cpu/cpu_early.c: Line 53: } can we also have a int get_nominal_ratio() { flex_ratio = rdmsr(MSR_FLEX_RATIO); nominal_ratio = ((flex_ratio.lo >> 8) & 0xff) return nominal_ratio; } PS8, Line 94: #if !ENV_RAMSTAGE why guard? PS8, Line 150: void set_P_State_to_turbo_ratio(void) no camel case PS8, Line 170: set_P_State_to_nominal_TDP_ratio same PS8, Line 189: set_P_State_to_max_non_turbo_ratio -same https://review.coreboot.org/#/c/19540/8/src/soc/intel/common/block/cpu/smmr… File src/soc/intel/common/block/cpu/smmrelocate.c: PS8, Line 34: #include "chip.h" do we need? https://review.coreboot.org/#/c/19540/8/src/soc/intel/common/block/include/… File src/soc/intel/common/block/include/intelblocks/cpu.h: PS8, Line 19: #include <rules.h> remove this PS8, Line 25: one tab less? PS8, Line 39: #if !ENV_RAMSTAGE don't need? https://review.coreboot.org/#/c/19540/8/src/soc/intel/common/block/include/… File src/soc/intel/common/block/include/intelblocks/msr.h: PS8, Line 47: one tab less PS8, Line 53: 0x40 (1 << 6) PS8, Line 124: use tab? PS8, Line 124: #define SMRR_SUPPORTED (1<<11) : #define PRMRR_SUPPORTED (1<<12) lets analyze if you can move this into mtrr.h https://review.coreboot.org/#/c/19540/8/src/soc/intel/common/block/include/… File src/soc/intel/common/block/include/intelblocks/smm.h: PS8, Line 5: 2015 2017 PS8, Line 17: _ remove this PS8, Line 22: #include <fsp/memmap.h> : #include <soc/gpio.h> why we need this -- To view, visit https://review.coreboot.org/19540 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I2f80c42132d9ea738be4051d2395e9e51ac153f8 Gerrit-PatchSet: 8 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Cole Nelson <colex.nelson(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: Yes

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Change in coreboot[master]: sb/intel/bd82x6x: Disable unused bridges
by Patrick Rudolph (Code Review) 23 May '17

23 May '17

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/19818 ) Change subject: sb/intel/bd82x6x: Disable unused bridges ...................................................................... Patch Set 3: > On my x200/ICH9 all SB PCIe functions seem to support hotplug. > How is the situation on bd82x6x? All ports support hotplug. But you won't use all of them. For that reason you can select which of them are used (for Express card) by using a devicetree array. On my board with current devixetree, no ports would be disabled as two are in use and one is marked hotplug let. It's only useful if you remove on the PCIe devices (like WiFi card). -- To view, visit https://review.coreboot.org/19818 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I6ee5e5f33824acdbca0f6ed28e90beab7fe10002 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: sb/intel/bd82x6x: Disable unused bridges
by Arthur Heymans (Code Review) 23 May '17

23 May '17

1 0

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coreboot-gerrit May 2017