coreboot-gerrit May 2017

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Change in coreboot[master]: soc/intel/common/block/gpio: Port gpio code from Apollolake ...
by Hannah Williams (Code Review) 24 May '17

24 May '17

Hannah Williams has posted comments on this change. ( https://review.coreboot.org/19759 ) Change subject: soc/intel/common/block/gpio: Port gpio code from Apollolake into common gpio ...................................................................... Patch Set 8: (2 comments) https://review.coreboot.org/#/c/19759/8/src/soc/intel/common/block/include/… File src/soc/intel/common/block/include/intelblocks/gpio_defs.h: PS8, Line 162: PAD_CFG_NF_IOS > What's this about? I need to go to mainboard gpio table and replace all instances of PAD_CFG_NF_IOS with PAD_CFG_NF_IOSSTATE_IOSTERM - will do PS8, Line 178: PAD_CFG_NF_IOS_3 > Why is there IOS_1, IOS_2, and IOS_3? When instantiating those they don't h these are for a specific IOStandby State and Term combination. I can use the generic PAD_CFG_NF_IOSSTATE_IOSTERM and abandon these or else can name them as PAD_CFG_NF_IOSTATE_HIZCRX1_IOSTERM_DISPUPD instead of PAD_CFG_NF_IOS_1 - which one would be better ? -- To view, visit https://review.coreboot.org/19759 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ic48401e92103ff0ec278fb69a3d304148a2d79aa Gerrit-PatchSet: 8 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Divya Chellappa <divya.chella(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/common/block/gpio: Port gpio code from Apollolake ...
by Hannah Williams (Code Review) 24 May '17

24 May '17

Hannah Williams has posted comments on this change. ( https://review.coreboot.org/19759 ) Change subject: soc/intel/common/block/gpio: Port gpio code from Apollolake into common gpio ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/19759/2/src/soc/intel/common/block/gpio/gpi… File src/soc/intel/common/block/gpio/gpio.c: Line 1: /* > I don't follow? You mean the shift offset for checking a bit being set? gpi_status_get in soc/intel/apollolake/gpio.c, has, (1 << (gpi % GPIO_MAX_NUM_PER_GROUP))) shouldn't this be (1 << ((pad - comm->first_pad) % GPIO_MAX_NUM_PER_GROUP)) ? -- To view, visit https://review.coreboot.org/19759 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ic48401e92103ff0ec278fb69a3d304148a2d79aa Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Divya Chellappa <divya.chella(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/apollolake: enable MONITOR/MWAIT for GLK
by Hannah Williams (Code Review) 24 May '17

24 May '17

Hannah Williams has posted comments on this change. ( https://review.coreboot.org/19718 ) Change subject: soc/intel/apollolake: enable MONITOR/MWAIT for GLK ...................................................................... Patch Set 7: Code-Review-1 Enabling MonitorMwaitEnable is not working on GLK - needs to be further investigated -- To view, visit https://review.coreboot.org/19718 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: If648c25a9b26c04b278dce4af241d439790288ca Gerrit-PatchSet: 7 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Cole Nelson <colex.nelson(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Cole Nelson <colex.nelson(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: soc/marvell/bg4cd: remove cosmos mainboard and bg4cd soc
by Furquan Shaikh (Code Review) 24 May '17

24 May '17

Furquan Shaikh has submitted this change and it was merged. ( https://review.coreboot.org/19823 ) Change subject: soc/marvell/bg4cd: remove cosmos mainboard and bg4cd soc ...................................................................... soc/marvell/bg4cd: remove cosmos mainboard and bg4cd soc The SoC code was never completed. It's just a skeleton that gets in the way of refactoring other code. Likewise, the mainboard was never completed either. Just remove them both. Change-Id: I8faaa9bb1b90ad2936dcdbaf2882651ebba6630c Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/19823 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- D src/mainboard/google/cosmos/Kconfig D src/mainboard/google/cosmos/Kconfig.name D src/mainboard/google/cosmos/Makefile.inc D src/mainboard/google/cosmos/board_info.txt D src/mainboard/google/cosmos/boardid.c D src/mainboard/google/cosmos/bootblock.c D src/mainboard/google/cosmos/chromeos.c D src/mainboard/google/cosmos/chromeos.fmd D src/mainboard/google/cosmos/devicetree.cb D src/mainboard/google/cosmos/mainboard.c D src/mainboard/google/cosmos/memlayout.ld D src/mainboard/google/cosmos/reset.c D src/mainboard/google/cosmos/romstage.c D src/soc/marvell/bg4cd/Kconfig D src/soc/marvell/bg4cd/Makefile.inc D src/soc/marvell/bg4cd/bootblock.c D src/soc/marvell/bg4cd/bootblock_asm.S D src/soc/marvell/bg4cd/cbmem.c D src/soc/marvell/bg4cd/i2c.c D src/soc/marvell/bg4cd/include/soc/gpio.h D src/soc/marvell/bg4cd/include/soc/i2c.h D src/soc/marvell/bg4cd/include/soc/memlayout.ld D src/soc/marvell/bg4cd/include/soc/sdram.h D src/soc/marvell/bg4cd/monotonic_timer.c D src/soc/marvell/bg4cd/romstage.S D src/soc/marvell/bg4cd/sdram.c D src/soc/marvell/bg4cd/spi.c 27 files changed, 0 insertions(+), 798 deletions(-) Approvals: Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/cosmos/Kconfig b/src/mainboard/google/cosmos/Kconfig deleted file mode 100644 index 3d8d649..0000000 --- a/src/mainboard/google/cosmos/Kconfig +++ /dev/null @@ -1,56 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright 2014 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -if BOARD_GOOGLE_COSMOS - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select BOARD_ID_AUTO - select BOARD_ROMSIZE_KB_2048 - select COMMON_CBFS_SPI_WRAPPER - select HAVE_HARD_RESET - select MAINBOARD_HAS_CHROMEOS - select SOC_MARVELL_BG4CD - select SPI_FLASH - select SPI_FLASH_SPANSION - -config VBOOT - select VBOOT_VBNV_FLASH - -config MAINBOARD_DIR - string - default google/cosmos - -config MAINBOARD_PART_NUMBER - string - default "Cosmos" - -config MAINBOARD_VENDOR - string - default "Google" - -config BOOT_DEVICE_SPI_FLASH_BUS - int - default 2 - -config DRAM_SIZE_MB - int - default 1024 - -config GBB_HWID - string - depends on CHROMEOS - default "Cosmos TEST 1" -endif # BOARD_GOOGLE_COSMOS diff --git a/src/mainboard/google/cosmos/Kconfig.name b/src/mainboard/google/cosmos/Kconfig.name deleted file mode 100644 index 6dade21..0000000 --- a/src/mainboard/google/cosmos/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_GOOGLE_COSMOS - bool "Cosmos" diff --git a/src/mainboard/google/cosmos/Makefile.inc b/src/mainboard/google/cosmos/Makefile.inc deleted file mode 100644 index 12f38bd..0000000 --- a/src/mainboard/google/cosmos/Makefile.inc +++ /dev/null @@ -1,37 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright 2014 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -bootblock-y += bootblock.c -bootblock-y += boardid.c -bootblock-y += chromeos.c -bootblock-y += reset.c - -verstage-y += boardid.c -verstage-y += chromeos.c -verstage-y += reset.c - -romstage-y += boardid.c -romstage-y += chromeos.c -romstage-y += romstage.c -romstage-y += reset.c - -ramstage-y += boardid.c -ramstage-y += chromeos.c -ramstage-y += mainboard.c -ramstage-y += reset.c - -bootblock-y += memlayout.ld -verstage-y += memlayout.ld -romstage-y += memlayout.ld -ramstage-y += memlayout.ld diff --git a/src/mainboard/google/cosmos/board_info.txt b/src/mainboard/google/cosmos/board_info.txt deleted file mode 100644 index 15e52fd..0000000 --- a/src/mainboard/google/cosmos/board_info.txt +++ /dev/null @@ -1,5 +0,0 @@ -Vendor name: Google -Board name: Cosmos Marvell BG4CD reference board -Category: eval -ROM protocol: SPI -ROM socketed: n diff --git a/src/mainboard/google/cosmos/boardid.c b/src/mainboard/google/cosmos/boardid.c deleted file mode 100644 index 407f9dc..0000000 --- a/src/mainboard/google/cosmos/boardid.c +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <boardid.h> - -uint8_t board_id(void) -{ - return -1; -} diff --git a/src/mainboard/google/cosmos/bootblock.c b/src/mainboard/google/cosmos/bootblock.c deleted file mode 100644 index 957e09c..0000000 --- a/src/mainboard/google/cosmos/bootblock.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <bootblock_common.h> - -void bootblock_mainboard_init(void) -{ -} diff --git a/src/mainboard/google/cosmos/chromeos.c b/src/mainboard/google/cosmos/chromeos.c deleted file mode 100644 index d43daa2..0000000 --- a/src/mainboard/google/cosmos/chromeos.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <boot/coreboot_tables.h> -#include <vendorcode/google/chromeos/chromeos.h> - -void fill_lb_gpios(struct lb_gpios *gpios) -{ -} - -int get_recovery_mode_switch(void) -{ - return 0; -} - -int get_write_protect_state(void) -{ - return 0; -} diff --git a/src/mainboard/google/cosmos/chromeos.fmd b/src/mainboard/google/cosmos/chromeos.fmd deleted file mode 100644 index 9817169..0000000 --- a/src/mainboard/google/cosmos/chromeos.fmd +++ /dev/null @@ -1,28 +0,0 @@ -FLASH@0x0 0x200000 { - WP_RO@0x0 0x100000 { - RO_SECTION@0x0 0xf0000 { - BOOTBLOCK@0 128K - COREBOOT(CBFS)@0x20000 0x60000 - FMAP@0x80000 0x1000 - GBB@0x81000 0x6ef00 - RO_FRID@0xeff00 0x100 - } - RO_VPD@0xf0000 0x10000 - } - RW_SECTION_A@0x100000 0x68000 { - VBLOCK_A@0x0 0x2000 - FW_MAIN_A(CBFS)@0x2000 0x65f00 - RW_FWID_A@0x67f00 0x100 - } - RW_SHARED@0x168000 0x4000 { - SHARED_DATA@0x0 0x4000 - } - RW_ELOG@0x16c000 0x4000 - RW_SECTION_B@0x180000 0x68000 { - VBLOCK_B@0x0 0x2000 - FW_MAIN_B(CBFS)@0x2000 0x65f00 - RW_FWID_B@0x67f00 0x100 - } - RW_VPD@0x1e8000 0x8000 - RW_NVRAM@0x1f0000 0x10000 -} diff --git a/src/mainboard/google/cosmos/devicetree.cb b/src/mainboard/google/cosmos/devicetree.cb deleted file mode 100644 index 054c113..0000000 --- a/src/mainboard/google/cosmos/devicetree.cb +++ /dev/null @@ -1,19 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright 2014 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# TODO fill with Versatile Express board data in QEMU. -chip soc/marvell/bg4cd - device cpu_cluster 0 on end -end diff --git a/src/mainboard/google/cosmos/mainboard.c b/src/mainboard/google/cosmos/mainboard.c deleted file mode 100644 index 85187d8..0000000 --- a/src/mainboard/google/cosmos/mainboard.c +++ /dev/null @@ -1,34 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <boot/coreboot_tables.h> - -static void mainboard_init(device_t dev) -{ -} - -static void mainboard_enable(device_t dev) -{ - dev->ops->init = &mainboard_init; -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; - -void lb_board(struct lb_header *header) -{ -} diff --git a/src/mainboard/google/cosmos/memlayout.ld b/src/mainboard/google/cosmos/memlayout.ld deleted file mode 100644 index 2c33306..0000000 --- a/src/mainboard/google/cosmos/memlayout.ld +++ /dev/null @@ -1,14 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/memlayout.ld> diff --git a/src/mainboard/google/cosmos/reset.c b/src/mainboard/google/cosmos/reset.c deleted file mode 100644 index e01c741..0000000 --- a/src/mainboard/google/cosmos/reset.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <reset.h> - -void hard_reset(void) -{ - while (1) - ; -} diff --git a/src/mainboard/google/cosmos/romstage.c b/src/mainboard/google/cosmos/romstage.c deleted file mode 100644 index 36ee0f9..0000000 --- a/src/mainboard/google/cosmos/romstage.c +++ /dev/null @@ -1,53 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/cache.h> -#include <arch/exception.h> -#include <arch/stages.h> -#include <armv7.h> -#include <cbfs.h> -#include <cbmem.h> -#include <console/console.h> -#include <delay.h> -#include <program_loading.h> -#include <soc/sdram.h> -#include <stdlib.h> -#include <symbols.h> -#include <timestamp.h> -#include <types.h> -#include <vendorcode/google/chromeos/chromeos.h> - -#include "timer.h" - -void main(void) -{ - timestamp_add_now(TS_START_ROMSTAGE); - - console_init(); - - timestamp_add_now(TS_BEFORE_INITRAM); - - sdram_init(); - - timestamp_add_now(TS_AFTER_INITRAM); - - mmu_init(); - mmu_config_range(0, 4096, DCACHE_OFF); - dcache_mmu_enable(); - - cbmem_initialize_empty(); - - run_ramstage(); -} diff --git a/src/soc/marvell/bg4cd/Kconfig b/src/soc/marvell/bg4cd/Kconfig deleted file mode 100644 index 6f9b6aa..0000000 --- a/src/soc/marvell/bg4cd/Kconfig +++ /dev/null @@ -1,34 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright 2014 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -config SOC_MARVELL_BG4CD - bool - default n - select ARCH_BOOTBLOCK_ARMV7_M - select BOOTBLOCK_CUSTOM if VBOOT - select ARCH_RAMSTAGE_ARMV7 - select ARCH_ROMSTAGE_ARMV7 - select ARCH_VERSTAGE_ARMV7_M - select BOOTBLOCK_CONSOLE - select GENERIC_UDELAY - select HAVE_MONOTONIC_TIMER - select GENERIC_GPIO_LIB - -if SOC_MARVELL_BG4CD - -config VBOOT - select VBOOT_STARTS_IN_BOOTBLOCK - -endif diff --git a/src/soc/marvell/bg4cd/Makefile.inc b/src/soc/marvell/bg4cd/Makefile.inc deleted file mode 100644 index 86aa764..0000000 --- a/src/soc/marvell/bg4cd/Makefile.inc +++ /dev/null @@ -1,49 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright 2014 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -ifeq ($(CONFIG_SOC_MARVELL_BG4CD),y) - -bootblock-$(CONFIG_VBOOT) += bootblock_asm.S -bootblock-$(CONFIG_VBOOT) += bootblock.c - -bootblock-y += cbmem.c -bootblock-y += i2c.c -bootblock-y += monotonic_timer.c -bootblock-$(CONFIG_SPI_FLASH) += spi.c - -verstage-y += i2c.c -verstage-y += monotonic_timer.c -verstage-$(CONFIG_SPI_FLASH) += spi.c - -romstage-y += romstage.S -romstage-y += cbmem.c -romstage-y += i2c.c -romstage-y += monotonic_timer.c -romstage-y += sdram.c -romstage-$(CONFIG_SPI_FLASH) += spi.c - -ramstage-y += cbmem.c -ramstage-y += i2c.c -ramstage-y += monotonic_timer.c -ramstage-$(CONFIG_SPI_FLASH) += spi.c - -CPPFLAGS_common += -Isrc/soc/marvell/bg4cd/include/ - -$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin - @printf "Generating: $(subst $(obj)/,,$(@))\n" - @mkdir -p $(dir $@) - @mv $< $@ - -endif diff --git a/src/soc/marvell/bg4cd/bootblock.c b/src/soc/marvell/bg4cd/bootblock.c deleted file mode 100644 index fb3dcd2..0000000 --- a/src/soc/marvell/bg4cd/bootblock.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <program_loading.h> -#include <timestamp.h> -#include <vendorcode/google/chromeos/chromeos.h> - -void main(void) -{ - console_init(); - timestamp_init(timestamp_get()); - run_romstage(); -} diff --git a/src/soc/marvell/bg4cd/bootblock_asm.S b/src/soc/marvell/bg4cd/bootblock_asm.S deleted file mode 100644 index 73ca46b..0000000 --- a/src/soc/marvell/bg4cd/bootblock_asm.S +++ /dev/null @@ -1,54 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -#include <arch/asm.h> - -ENTRY(_start) - /* - * Initialize the stack to a known value. This is used to check for - * stack overflow later in the boot process. - */ - ldr r0, =_stack - ldr r1, =_estack - ldr r2, =0xdeadbeef -init_stack_loop: - str r2, [r0] - add r0, #4 - cmp r0, r1 - bne init_stack_loop - -call_verstage: - ldr sp, =_estack /* Set up stack pointer */ - /* - * we don't bl here to preserve lr so that we can return to the caller - * of the bootblock - */ - b main -ENDPROC(_start) diff --git a/src/soc/marvell/bg4cd/cbmem.c b/src/soc/marvell/bg4cd/cbmem.c deleted file mode 100644 index ee8cd16..0000000 --- a/src/soc/marvell/bg4cd/cbmem.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbmem.h> -#include <stddef.h> - -void *cbmem_top(void) -{ - return NULL; -} diff --git a/src/soc/marvell/bg4cd/i2c.c b/src/soc/marvell/bg4cd/i2c.c deleted file mode 100644 index 6d06ee3..0000000 --- a/src/soc/marvell/bg4cd/i2c.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/i2c.h> -#include <soc/i2c.h> - -int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int seg_count) -{ - return 0; -} - -void i2c_init(unsigned int bus, unsigned int hz) -{ -} diff --git a/src/soc/marvell/bg4cd/include/soc/gpio.h b/src/soc/marvell/bg4cd/include/soc/gpio.h deleted file mode 100644 index de1224f..0000000 --- a/src/soc/marvell/bg4cd/include/soc/gpio.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __SOC_MARVELL_BG4CD_GPIO_H__ -#define __SOC_MARVELL_BG4CD_GPIO_H__ - -#include <types.h> - -typedef u32 gpio_t; - -#endif /* __SOC_MARVELL_BG4CD_GPIO_H__ */ diff --git a/src/soc/marvell/bg4cd/include/soc/i2c.h b/src/soc/marvell/bg4cd/include/soc/i2c.h deleted file mode 100644 index e6244ea..0000000 --- a/src/soc/marvell/bg4cd/include/soc/i2c.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __SOC_MARVELL_BG4CD_I2C_H__ -#define __SOC_MARVELL_BG4CD_I2C_H__ - -void i2c_init(unsigned int bus, unsigned int hz); - -#endif diff --git a/src/soc/marvell/bg4cd/include/soc/memlayout.ld b/src/soc/marvell/bg4cd/include/soc/memlayout.ld deleted file mode 100644 index 83d9bf0..0000000 --- a/src/soc/marvell/bg4cd/include/soc/memlayout.ld +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <memlayout.h> - -#include <arch/header.ld> - -SECTIONS -{ - SRAM_START(0x20000) - - BOOTBLOCK(0x20000, 40K) - /* there is no VERSTAGE because it's built into bootblock */ - - PRERAM_CBFS_CACHE(0x2A000, 8K) - STACK(0x2C000, 8K) - VBOOT2_WORK(0x2E000, 16K) - - SRAM_END(0x40000) - - DRAM_START(0x40000) - - RAMSTAGE(0x40000, 128K) - POSTRAM_CBFS_CACHE(0x60000, 1M) - - ROMSTAGE(0xF7A40000, 32K) - TTB(0xF7A48000, 16K) -} diff --git a/src/soc/marvell/bg4cd/include/soc/sdram.h b/src/soc/marvell/bg4cd/include/soc/sdram.h deleted file mode 100644 index 0980560..0000000 --- a/src/soc/marvell/bg4cd/include/soc/sdram.h +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __SOC_MARVELL_BG4CD_SDRAM_H__ -#define __SOC_MARVELL_BG4CD_SDRAM_H__ - -void sdram_init(void); -#endif diff --git a/src/soc/marvell/bg4cd/monotonic_timer.c b/src/soc/marvell/bg4cd/monotonic_timer.c deleted file mode 100644 index e8e5939..0000000 --- a/src/soc/marvell/bg4cd/monotonic_timer.c +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <delay.h> -#include <timer.h> - -void timer_monotonic_get(struct mono_time *mt) -{ -} diff --git a/src/soc/marvell/bg4cd/romstage.S b/src/soc/marvell/bg4cd/romstage.S deleted file mode 100644 index 73574f2..0000000 --- a/src/soc/marvell/bg4cd/romstage.S +++ /dev/null @@ -1,79 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - */ - -#include <arch/asm.h> - -.arm -ENTRY(stage_entry) - /* - * Set the CPU to System mode with IRQ and FIQ disabled. Prefetch/Data - * aborts may happen early and crash before the abort handlers are - * installed, but at least the problem will show up near the code that - * causes it. - */ - msr cpsr_cxf, #0xdf - bl _thumb_start -ENDPROC(stage_entry) - -.thumb -ENTRY(_thumb_start) - bl arm_init_caches - - /* - * From Cortex-A Series Programmer's Guide: - * Only CPU 0 performs initialization. Other CPUs go into WFI - * to do this, first work out which CPU this is - * this code typically is run before any other initialization step - */ - mrc p15, 0, r1, c0, c0, 5 @ Read Multiprocessor Affinity Register - and r1, r1, #0x3 @ Extract CPU ID bits - cmp r1, #0 - bne wait_for_interrupt @ If this is not core0, wait - - /* - * Initialize the stack to a known value. This is used to check for - * stack overflow later in the boot process. - */ - ldr r0, =_stack - ldr r1, =_estack - ldr r2, =0xdeadbeef -init_stack_loop: - str r2, [r0] - add r0, #4 - cmp r0, r1 - bne init_stack_loop - - ldr sp, =_estack /* Set up stack pointer */ - bl main - -wait_for_interrupt: - wfi - mov pc, lr @ back to my caller -ENDPROC(_thumb_start) diff --git a/src/soc/marvell/bg4cd/sdram.c b/src/soc/marvell/bg4cd/sdram.c deleted file mode 100644 index 74c2396..0000000 --- a/src/soc/marvell/bg4cd/sdram.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#include <console/console.h> -#include <soc/sdram.h> - -void sdram_init(void) -{ - printk(BIOS_INFO, "Starting SDRAM initialization...\n"); - printk(BIOS_INFO, "Finish SDRAM initialization...\n"); -} diff --git a/src/soc/marvell/bg4cd/spi.c b/src/soc/marvell/bg4cd/spi.c deleted file mode 100644 index 188a6bd..0000000 --- a/src/soc/marvell/bg4cd/spi.c +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stddef.h> -#include <spi-generic.h> - -int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) -{ - return -1; -} -- To view, visit https://review.coreboot.org/19823 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I8faaa9bb1b90ad2936dcdbaf2882651ebba6630c Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mainboard/google/poppy: Add PowerResource for touchscreen de...
by Furquan Shaikh (Code Review) 23 May '17

23 May '17

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/19829 ) Change subject: mainboard/google/poppy: Add PowerResource for touchscreen device ...................................................................... Patch Set 2: > We needed to do this because the touchscreen wouldn't power back on on resume? Or that the timing was bad when we brought power back? Or is this to deal with s0ix? We needed to do this because power to the touchscreen device was not cut in S3. This resulted in the power rail for touchscreen being on all the time even when suspended. -- To view, visit https://review.coreboot.org/19829 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ia0bebc7259b10cc60a9fa5b53542dfdd9685663e Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-HasComments: No

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Change in coreboot[master]: detachables: Add invert parameter
by Furquan Shaikh (Code Review) 23 May '17

23 May '17

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/19698 ) Change subject: detachables: Add invert parameter ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/19698 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ide6893a26f19eb2490377d4d53366ad145a9e6e3 Gerrit-PatchSet: 11 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

1 0

Change in coreboot[master]: mainboard/google/poppy: Add PowerResource for touchscreen de...
by Duncan Laurie (Code Review) 23 May '17

23 May '17

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/19829 ) Change subject: mainboard/google/poppy: Add PowerResource for touchscreen device ...................................................................... Patch Set 2: > Did we ever figure out how to handle the wacom firmware updater? Nevermind, looks like that is taken care of in the update script. -- To view, visit https://review.coreboot.org/19829 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ia0bebc7259b10cc60a9fa5b53542dfdd9685663e Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Implement GPIO ACPI AML generating functions
by Duncan Laurie (Code Review) 23 May '17

23 May '17

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/19828 ) Change subject: soc/intel/skylake: Implement GPIO ACPI AML generating functions ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/19828 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I77e5d0decd8929a922d06b02312378f092551667 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/skylake: Implement GPIO ACPI AML generating functions
by Furquan Shaikh (Code Review) 23 May '17

23 May '17

Hello Duncan Laurie, I'd like you to reexamine a change. Please visit https://review.coreboot.org/19828 to look at the new patch set (#2). Change subject: soc/intel/skylake: Implement GPIO ACPI AML generating functions ...................................................................... soc/intel/skylake: Implement GPIO ACPI AML generating functions Implement GPIO ACPI AML generating functions that can be called by coreboot drivers to generate GPIO manipulation code in AML. Following API functions are implemented: 1. acpigen_soc_read_rx_gpio 2. acpigen_soc_get_tx_gpio 3. acpigen_soc_set_tx_gpio 4. acpigen_soc_clear_tx_gpio In addition to the API functions above, helper functions are added to gpio.asl to set/clear/get Tx value of GPIO. BUG=b:62028489 Change-Id: I77e5d0decd8929a922d06b02312378f092551667 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/acpi/gpio.asl 2 files changed, 82 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/19828/2 -- To view, visit https://review.coreboot.org/19828 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I77e5d0decd8929a922d06b02312378f092551667 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>

1 0

Change in coreboot[master]: soc/intel/skylake: Implement GPIO ACPI AML generating functions
by Furquan Shaikh (Code Review) 23 May '17

23 May '17

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/19828 ) Change subject: soc/intel/skylake: Implement GPIO ACPI AML generating functions ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/19828/1/src/soc/intel/skylake/acpi.c File src/soc/intel/skylake/acpi.c: Line 713: > maybe delete this blank line, or add one to the above function, just so the oops yeah I will delete this one. -- To view, visit https://review.coreboot.org/19828 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I77e5d0decd8929a922d06b02312378f092551667 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-HasComments: Yes

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coreboot-gerrit May 2017