coreboot-gerrit March 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mainboard: Add Sapphire Pure Platinum H61
by Nicola Corna (Code Review) 27 Mar '17

27 Mar '17

Nicola Corna has posted comments on this change. ( https://review.coreboot.org/18564 ) Change subject: mainboard: Add Sapphire Pure Platinum H61 ...................................................................... Patch Set 13: (1 comment) > Nice that you hooked up libgfxinit! Unfortunately I've just noticed that, with libgfxinit, the GPU doesn't work after a S3 resume. > Please provide raminit logs for both failing and working case. Did you try the pending ivybridge raminit patches? They might increase raminit stability. Unfortunately I can't reproduce the working case, but I can provide you the log of a failed raminit, as soon as I obtain a USB debugger. https://review.coreboot.org/#/c/18564/13//COMMIT_MSG Commit Message: PS13, Line 47: * If an external card is inserted and the option : ONBOARD_VGA_IS_PRIMARY is not enabled, the internal GPU : disappears completely from the PCI bus. > This is the result of the combination of disable_peg() in nb/sandybridge/no IMO, this is completely an unexpected behaviour, as many users (me included) use both the GPUs. The OEM bios didn't show the integrated GPU as well, which led me to think that my integrated GPU was dead. I'll give a look at the code and add a NVRAM switch if I can. -- To view, visit https://review.coreboot.org/18564 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I76aca2cfc4708c1728ae03ee4f6bc59d976c28a0 Gerrit-PatchSet: 13 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/common/block: Add Intel common UART code
by Aamir Bohra (Code Review) 27 Mar '17

27 Mar '17

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/18952 ) Change subject: soc/intel/common/block: Add Intel common UART code ...................................................................... Patch Set 2: (3 comments) https://review.coreboot.org/#/c/18952/2/src/soc/intel/common/block/uart/uar… File src/soc/intel/common/block/uart/uart.c: Line 39: tmp = read32(base + UART_CLK); > I really don't think we should be doing a read modify write. If the values Okay.Revised for direct write since registers are getting programmed for first time post reset. PS2, Line 40: N_VAL > These are not very descriptive w.r.t. to the global namespace of the pre-pr Done. Line 41: UART_CLK_EN | UART_CLK_UPDATE; > I see skylake is doing this in one full swoop. Is that appropriate for all? revised to program n and m values with clock update flag and then enabling the clock on next write -- To view, visit https://review.coreboot.org/18952 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I3843fac88cfb7bbb405be50d69f555b274f0d72a Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: Yes

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Change in coreboot[master]: nb/intel/sandybridge: Use DIV_ROUND_UP macro to select timings
by Arthur Heymans (Code Review) 27 Mar '17

27 Mar '17

Arthur Heymans has submitted this change and it was merged. ( https://review.coreboot.org/18960 ) Change subject: nb/intel/sandybridge: Use DIV_ROUND_UP macro to select timings ...................................................................... nb/intel/sandybridge: Use DIV_ROUND_UP macro to select timings This is a cosmetic change. Change-Id: Iea4dd97e9d83594447427abd9f844e507b805192 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/18960 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/northbridge/intel/sandybridge/raminit_ivy.c M src/northbridge/intel/sandybridge/raminit_sandy.c 2 files changed, 20 insertions(+), 20 deletions(-) Approvals: Patrick Rudolph: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c index 9349cf7..f13d613 100644 --- a/src/northbridge/intel/sandybridge/raminit_ivy.c +++ b/src/northbridge/intel/sandybridge/raminit_ivy.c @@ -210,7 +210,7 @@ printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", val32); /* Find CAS latency */ - val = (ctrl->tAA + ctrl->tCK - 1) / ctrl->tCK; + val = DIV_ROUND_UP(ctrl->tAA, ctrl->tCK); printk(BIOS_DEBUG, "Minimum CAS latency : %uT\n", val); /* Find lowest supported CAS latency that satisfies the minimum value */ while (!((ctrl->cas_supported >> (val - MIN_CAS)) & 1) @@ -234,38 +234,38 @@ printk(BIOS_DEBUG, "Selected CWL latency : %uT\n", ctrl->CWL); /* Find tRCD */ - ctrl->tRCD = (ctrl->tRCD + ctrl->tCK - 1) / ctrl->tCK; + ctrl->tRCD = DIV_ROUND_UP(ctrl->tRCD, ctrl->tCK); printk(BIOS_DEBUG, "Selected tRCD : %uT\n", ctrl->tRCD); - ctrl->tRP = (ctrl->tRP + ctrl->tCK - 1) / ctrl->tCK; + ctrl->tRP = DIV_ROUND_UP(ctrl->tRP, ctrl->tCK); printk(BIOS_DEBUG, "Selected tRP : %uT\n", ctrl->tRP); /* Find tRAS */ - ctrl->tRAS = (ctrl->tRAS + ctrl->tCK - 1) / ctrl->tCK; + ctrl->tRAS = DIV_ROUND_UP(ctrl->tRAS, ctrl->tCK); printk(BIOS_DEBUG, "Selected tRAS : %uT\n", ctrl->tRAS); /* Find tWR */ - ctrl->tWR = (ctrl->tWR + ctrl->tCK - 1) / ctrl->tCK; + ctrl->tWR = DIV_ROUND_UP(ctrl->tWR, ctrl->tCK); printk(BIOS_DEBUG, "Selected tWR : %uT\n", ctrl->tWR); /* Find tFAW */ - ctrl->tFAW = (ctrl->tFAW + ctrl->tCK - 1) / ctrl->tCK; + ctrl->tFAW = DIV_ROUND_UP(ctrl->tFAW, ctrl->tCK); printk(BIOS_DEBUG, "Selected tFAW : %uT\n", ctrl->tFAW); /* Find tRRD */ - ctrl->tRRD = (ctrl->tRRD + ctrl->tCK - 1) / ctrl->tCK; + ctrl->tRRD = DIV_ROUND_UP(ctrl->tRRD, ctrl->tCK); printk(BIOS_DEBUG, "Selected tRRD : %uT\n", ctrl->tRRD); /* Find tRTP */ - ctrl->tRTP = (ctrl->tRTP + ctrl->tCK - 1) / ctrl->tCK; + ctrl->tRTP = DIV_ROUND_UP(ctrl->tRTP, ctrl->tCK); printk(BIOS_DEBUG, "Selected tRTP : %uT\n", ctrl->tRTP); /* Find tWTR */ - ctrl->tWTR = (ctrl->tWTR + ctrl->tCK - 1) / ctrl->tCK; + ctrl->tWTR = DIV_ROUND_UP(ctrl->tWTR, ctrl->tCK); printk(BIOS_DEBUG, "Selected tWTR : %uT\n", ctrl->tWTR); /* Refresh-to-Active or Refresh-to-Refresh (tRFC) */ - ctrl->tRFC = (ctrl->tRFC + ctrl->tCK - 1) / ctrl->tCK; + ctrl->tRFC = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK); printk(BIOS_DEBUG, "Selected tRFC : %uT\n", ctrl->tRFC); ctrl->tREFI = get_REFI(ctrl->tCK); diff --git a/src/northbridge/intel/sandybridge/raminit_sandy.c b/src/northbridge/intel/sandybridge/raminit_sandy.c index a83cb35..84c2374 100644 --- a/src/northbridge/intel/sandybridge/raminit_sandy.c +++ b/src/northbridge/intel/sandybridge/raminit_sandy.c @@ -210,7 +210,7 @@ printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", val32); /* Find CAS latency */ - val = (ctrl->tAA + ctrl->tCK - 1) / ctrl->tCK; + val = DIV_ROUND_UP(ctrl->tAA, ctrl->tCK); printk(BIOS_DEBUG, "Minimum CAS latency : %uT\n", val); /* Find lowest supported CAS latency that satisfies the minimum value */ while (!((ctrl->cas_supported >> (val - MIN_CAS)) & 1) @@ -234,38 +234,38 @@ printk(BIOS_DEBUG, "Selected CWL latency : %uT\n", ctrl->CWL); /* Find tRCD */ - ctrl->tRCD = (ctrl->tRCD + ctrl->tCK - 1) / ctrl->tCK; + ctrl->tRCD = DIV_ROUND_UP(ctrl->tRCD, ctrl->tCK); printk(BIOS_DEBUG, "Selected tRCD : %uT\n", ctrl->tRCD); - ctrl->tRP = (ctrl->tRP + ctrl->tCK - 1) / ctrl->tCK; + ctrl->tRP = DIV_ROUND_UP(ctrl->tRP, ctrl->tCK); printk(BIOS_DEBUG, "Selected tRP : %uT\n", ctrl->tRP); /* Find tRAS */ - ctrl->tRAS = (ctrl->tRAS + ctrl->tCK - 1) / ctrl->tCK; + ctrl->tRAS = DIV_ROUND_UP(ctrl->tRAS, ctrl->tCK); printk(BIOS_DEBUG, "Selected tRAS : %uT\n", ctrl->tRAS); /* Find tWR */ - ctrl->tWR = (ctrl->tWR + ctrl->tCK - 1) / ctrl->tCK; + ctrl->tWR = DIV_ROUND_UP(ctrl->tWR, ctrl->tCK); printk(BIOS_DEBUG, "Selected tWR : %uT\n", ctrl->tWR); /* Find tFAW */ - ctrl->tFAW = (ctrl->tFAW + ctrl->tCK - 1) / ctrl->tCK; + ctrl->tFAW = DIV_ROUND_UP(ctrl->tFAW, ctrl->tCK); printk(BIOS_DEBUG, "Selected tFAW : %uT\n", ctrl->tFAW); /* Find tRRD */ - ctrl->tRRD = (ctrl->tRRD + ctrl->tCK - 1) / ctrl->tCK; + ctrl->tRRD = DIV_ROUND_UP(ctrl->tRRD, ctrl->tCK); printk(BIOS_DEBUG, "Selected tRRD : %uT\n", ctrl->tRRD); /* Find tRTP */ - ctrl->tRTP = (ctrl->tRTP + ctrl->tCK - 1) / ctrl->tCK; + ctrl->tRTP = DIV_ROUND_UP(ctrl->tRTP, ctrl->tCK); printk(BIOS_DEBUG, "Selected tRTP : %uT\n", ctrl->tRTP); /* Find tWTR */ - ctrl->tWTR = (ctrl->tWTR + ctrl->tCK - 1) / ctrl->tCK; + ctrl->tWTR = DIV_ROUND_UP(ctrl->tWTR, ctrl->tCK); printk(BIOS_DEBUG, "Selected tWTR : %uT\n", ctrl->tWTR); /* Refresh-to-Active or Refresh-to-Refresh (tRFC) */ - ctrl->tRFC = (ctrl->tRFC + ctrl->tCK - 1) / ctrl->tCK; + ctrl->tRFC = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK - 1); printk(BIOS_DEBUG, "Selected tRFC : %uT\n", ctrl->tRFC); ctrl->tREFI = get_REFI(ctrl->tCK); -- To view, visit https://review.coreboot.org/18960 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: Iea4dd97e9d83594447427abd9f844e507b805192 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins)

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Change in coreboot[master]: amd/pi/hudson: Add fanless SMU firmware to build
by build bot (Jenkins) (Code Review) 27 Mar '17

27 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19002 ) Change subject: amd/pi/hudson: Add fanless SMU firmware to build ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/50699/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/6678/ : SUCCESS -- To view, visit https://review.coreboot.org/19002 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ib44860780c8d5fb00c47f775a2a83b82ff3e1821 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common/block: Add Intel common UART code
by Subrata Banik (Code Review) 27 Mar '17

27 Mar '17

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/18952 ) Change subject: soc/intel/common/block: Add Intel common UART code ...................................................................... Patch Set 4: (3 comments) https://review.coreboot.org/#/c/18952/4/src/soc/intel/common/block/include/… File src/soc/intel/common/block/include/intelblocks/uart.h: PS4, Line 19: #include <arch/io.h> why we need this here? https://review.coreboot.org/#/c/18952/4/src/soc/intel/common/block/uart/uar… File src/soc/intel/common/block/uart/uart.c: Line 18: #include <soc/uart.h> u need io.h here PS4, Line 36: clk_sel = UART_CLK_DIV_N(UART_CLK_N_VAL) | UART_CLK_DIV_M(UART_CLK_M_VAL); >80 -- To view, visit https://review.coreboot.org/18952 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I3843fac88cfb7bbb405be50d69f555b274f0d72a Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: Yes

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Change in coreboot[master]: amd/pi/hudson: Reduce amdfw space requirement
by build bot (Jenkins) (Code Review) 27 Mar '17

27 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18990 ) Change subject: amd/pi/hudson: Reduce amdfw space requirement ...................................................................... Patch Set 3: Build Failed https://qa.coreboot.org/job/coreboot-gerrit/50697/ : FAILURE -- To view, visit https://review.coreboot.org/18990 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I139f3bfdb319af803fef64e7bd848e95945f41aa Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: northbridge/amd/stoney: Add FT4 package
by build bot (Jenkins) (Code Review) 27 Mar '17

27 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18989 ) Change subject: northbridge/amd/stoney: Add FT4 package ...................................................................... Patch Set 3: Build Failed https://qa.coreboot.org/job/coreboot-gerrit/50696/ : FAILURE -- To view, visit https://review.coreboot.org/18989 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I7bb15bc4c85c5b4d3d5a6c926c4bc346a282ef27 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Clean up serialio header file.
by Subrata Banik (Code Review) 27 Mar '17

27 Mar '17

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/19001 ) Change subject: soc/intel/skylake: Clean up serialio header file. ...................................................................... Patch Set 1: (6 comments) https://review.coreboot.org/#/c/19001/1/src/soc/intel/skylake/bootblock/i2c… File src/soc/intel/skylake/bootblock/i2c.c: PS1, Line 25: #include <soc/i2c.h> watch out for alphabetic order https://review.coreboot.org/#/c/19001/1/src/soc/intel/skylake/include/soc/i… File src/soc/intel/skylake/include/soc/i2c.h: PS1, Line 19: #define I2C_RESET 0x204 I2C_SOFT_RESET PS1, Line 20: #define I2C_RESET_EN (3 << 0) what is this 3 mean? mention bit field names 00 = I2C Host Controller is in reset (Reset Asserted) 01 = Reserved 10 = Reserved 11 = I2C Host Controller is NOT at reset (Reset Released) https://review.coreboot.org/#/c/19001/1/src/soc/intel/skylake/include/soc/u… File src/soc/intel/skylake/include/soc/uart.h: PS1, Line 22: #define UART_CLK_N_VAL 0xc35 : #define UART_CLK_M_VAL 0x30 move this macros below, lets have all bit definition intact PS1, Line 27: #define UART_RESET 0x204 -same PS1, Line 28: #define UART_RESET_EN (3 << 0) -same -- To view, visit https://review.coreboot.org/19001 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I881da01be8191270d9505737f68a6d2d8cd8cc69 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: Yes

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Change in coreboot[master]: amd/pi/hudson: Add fanless SMU firmware to build
by Marshall Dawson (Code Review) 27 Mar '17

27 Mar '17

Marshall Dawson has uploaded a new change for review. ( https://review.coreboot.org/19002 ) Change subject: amd/pi/hudson: Add fanless SMU firmware to build ...................................................................... amd/pi/hudson: Add fanless SMU firmware to build Use the new parameters in amdfwtool to include the additional SMU firmware into amdfw.rom. Change-Id: Ib44860780c8d5fb00c47f775a2a83b82ff3e1821 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/southbridge/amd/pi/hudson/Makefile.inc 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/19002/1 diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 9bc2dec..5f5b1c8 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -124,6 +124,7 @@ ###8 CONFIG_SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE).sbin +CONFIG_SMUFWM_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE)_FN.sbin ###95 CONFIG_SMUSCS_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuScs$(FIRMWARE_TYPE).bin @@ -152,6 +153,7 @@ ###18 ifeq ($(CONFIG_CPU_AMD_PI_00670F00_FP4)$(CONFIG_CPU_AMD_PI_00670F00_FT4), y) CONFIG_SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE).sbin +CONFIG_SMUFIRMWARE2_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE)_FN.sbin else ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) CONFIG_SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_$(FIRMWARE_TYPE).sbin endif @@ -171,6 +173,7 @@ CONFIG_2AMD_PUBKEY_FILE =$(CONFIG_AMD_PUBKEY_FILE) CONFIG_2PSPBTLDR_FILE =$(CONFIG_PSPBTLDR_FILE) CONFIG_2SMUFWM_FILE =$(CONFIG_SMUFWM_FILE) + CONFIG_2SMUFWM_FN_FILE =$(CONFIG_SMUFWM_FN_FILE) CONFIG_2PSPRCVR_FILE =$(CONFIG_PSPRCVR_FILE) CONFIG_2PUBSIGNEDKEY_FILE =$(CONFIG_PUBSIGNEDKEY_FILE) CONFIG_2PSPSCUREOS_FILE =$(CONFIG_PSPSCUREOS_FILE) @@ -179,6 +182,7 @@ CONFIG_2PSPTRUSTLETS_FILE =$(CONFIG_PSPTRUSTLETS_FILE) CONFIG_2TRUSTLETKEY_FILE =$(CONFIG_TRUSTLETKEY_FILE) CONFIG_2SMUFIRMWARE2_FILE =$(CONFIG_SMUFIRMWARE2_FILE) + CONFIG_2SMUFIRMWARE2_FN_FILE =$(CONFIG_SMUFIRMWARE2_FN_FILE) CONFIG_2SMUSCS_FILE =$(CONFIG_SMUSCS_FILE) OPT_2AMD_PUBKEY_FILE=$(call add_opt_prefix, $(CONFIG_2AMD_PUBKEY_FILE), --pubkey2) @@ -193,6 +197,8 @@ OPT_2TRUSTLETKEY_FILE=$(call add_opt_prefix, $(CONFIG_2TRUSTLETKEY_FILE), --trustletkey2) OPT_2SMUFIRMWARE2_FILE=$(call add_opt_prefix, $(CONFIG_2SMUFIRMWARE2_FILE), --smufirmware2_2) OPT_2SMUSCS_FILE=$(call add_opt_prefix, $(CONFIG_2SMUSCS_FILE), --smuscs2) + OPT_2SMUFWM_FN_FILE=$(call add_opt_prefix, $(CONFIG_2SMUFWM_FN_FILE), --smufnfirmware_2) + OPT_2SMUFIRMWARE2_FN_FILE=$(call add_opt_prefix, $(CONFIG_2SMUFIRMWARE2_FN_FILE), --smufnfirmware2_2) else OPT_AMD_PUBKEY_FILE=$(call add_opt_prefix, $(CONFIG_AMD_PUBKEY_FILE), --pubkey) OPT_PSPBTLDR_FILE=$(call add_opt_prefix, $(CONFIG_PSPBTLDR_FILE), --bootloader) @@ -227,6 +233,7 @@ $(call strip_quotes, $(CONFIG_2PUBSIGNEDKEY_FILE)) \ $(call strip_quotes, $(CONFIG_2PSPBTLDR_FILE)) \ $(call strip_quotes, $(CONFIG_2SMUFWM_FILE)) \ + $(call strip_quotes, $(CONFIG_2SMUFWM_FN_FILE)) \ $(call strip_quotes, $(CONFIG_2PSPRCVR_FILE)) \ $(call strip_quotes, $(CONFIG_2PSPSCUREOS_FILE)) \ $(call strip_quotes, $(CONFIG_2PSPNVRAM_FILE)) \ @@ -235,6 +242,7 @@ $(call strip_quotes, $(CONFIG_2PSPTRUSTLETS_FILE)) \ $(call strip_quotes, $(CONFIG_2TRUSTLETKEY_FILE)) \ $(call strip_quotes, $(CONFIG_2SMUFIRMWARE2_FILE)) \ + $(call strip_quotes, $(CONFIG_2SMUFIRMWARE2_FN_FILE)) \ $(AMDFWTOOL) rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" @@ -257,6 +265,7 @@ $(OPT_2AMD_PUBKEY_FILE) \ $(OPT_2PSPBTLDR_FILE) \ $(OPT_2SMUFWM_FILE) \ + $(OPT_2SMUFWM_FN_FILE) \ $(OPT_2PSPRCVR_FILE) \ $(OPT_2PUBSIGNEDKEY_FILE) \ $(OPT_2PSPSCUREOS_FILE) \ @@ -265,6 +274,7 @@ $(OPT_2PSPTRUSTLETS_FILE) \ $(OPT_2TRUSTLETKEY_FILE) \ $(OPT_2SMUFIRMWARE2_FILE) \ + $(OPT_2SMUFIRMWARE2_FN_FILE) \ $(OPT_2SMUSCS_FILE) \ --flashsize $(CONFIG_ROM_SIZE) \ --output $@ -- To view, visit https://review.coreboot.org/19002 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Ib44860780c8d5fb00c47f775a2a83b82ff3e1821 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: util/amdfwtool: Add fanless SMU firmware
by Marshall Dawson (Code Review) 27 Mar '17

27 Mar '17

Hello Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/18991 to look at the new patch set (#3). Change subject: util/amdfwtool: Add fanless SMU firmware ...................................................................... util/amdfwtool: Add fanless SMU firmware The Stoney Ridge program has OPNs that are considered fanless. These APUs are strapped to search for unique SMU firmware, indicated by Type[8]=1 in the directory table entry. Add new options to amdfwtool and include the blobs in the build with the appropriate bit set in the Type encoding. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit 8df0d6847c39bb021271983018ac6f448f9ff9da) Change-Id: I4b80ccf8fd9644f9a9d300e6c67aed9834a2c7a7 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 85 insertions(+), 63 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/18991/3 -- To view, visit https://review.coreboot.org/18991 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I4b80ccf8fd9644f9a9d300e6c67aed9834a2c7a7 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins)

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coreboot-gerrit March 2017