coreboot-gerrit March 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/common/block: Add Intel common UART code
by build bot (Jenkins) (Code Review) 27 Mar '17

27 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18952 ) Change subject: soc/intel/common/block: Add Intel common UART code ...................................................................... Patch Set 5: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/50702/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/6681/ : SUCCESS -- To view, visit https://review.coreboot.org/18952 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I3843fac88cfb7bbb405be50d69f555b274f0d72a Gerrit-PatchSet: 5 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Clean up serialio header file.
by build bot (Jenkins) (Code Review) 27 Mar '17

27 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19001 ) Change subject: soc/intel/skylake: Clean up serialio header file. ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/50701/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/6680/ : SUCCESS -- To view, visit https://review.coreboot.org/19001 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I881da01be8191270d9505737f68a6d2d8cd8cc69 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Clean up serialio header file.
by Subrata Banik (Code Review) 27 Mar '17

27 Mar '17

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/19001 ) Change subject: soc/intel/skylake: Clean up serialio header file. ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/#/c/19001/2/src/soc/intel/skylake/include/soc/i… File src/soc/intel/skylake/include/soc/i2c.h: PS2, Line 31: #define I2C_RESET_EN (3 << 0) this name doesn't goes well with bit field. and why we need to use <<0 , its 0-1 indeed. https://review.coreboot.org/#/c/19001/2/src/soc/intel/skylake/include/soc/u… File src/soc/intel/skylake/include/soc/uart.h: PS2, Line 18: : #define UART_CLK 0x200 : #define UART_RESET 0x204 : : #define UART_CLK_UPDATE (1 << 31) : #define UART_CLK_EN (1 << 0) : #define UART_RESET_EN (3 << 0) : #define UART_RESET_DMA_EN (1 << 2) i think you misunderstood. i meant, club registers and its own big definition together example: #define reg 1 #define reg_bit 1 #define reg_2 2 #define reg_2_bit 2 Then you define macro those are not big definition but some value macro. -- To view, visit https://review.coreboot.org/19001 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I881da01be8191270d9505737f68a6d2d8cd8cc69 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/skylake: Clean up serialio header file.
by Aamir Bohra (Code Review) 27 Mar '17

27 Mar '17

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/19001 ) Change subject: soc/intel/skylake: Clean up serialio header file. ...................................................................... Patch Set 1: (6 comments) https://review.coreboot.org/#/c/19001/1/src/soc/intel/skylake/bootblock/i2c… File src/soc/intel/skylake/bootblock/i2c.c: PS1, Line 25: #include <soc/i2c.h> > watch out for alphabetic order Oops.Done. https://review.coreboot.org/#/c/19001/1/src/soc/intel/skylake/include/soc/i… File src/soc/intel/skylake/include/soc/i2c.h: PS1, Line 19: #define I2C_RESET 0x204 > I2C_SOFT_RESET Done.revised as per EDS. PS1, Line 20: #define I2C_RESET_EN (3 << 0) > what is this 3 mean? Done https://review.coreboot.org/#/c/19001/1/src/soc/intel/skylake/include/soc/u… File src/soc/intel/skylake/include/soc/uart.h: PS1, Line 22: #define UART_CLK_N_VAL 0xc35 : #define UART_CLK_M_VAL 0x30 > move this macros below, lets have all bit definition intact Done PS1, Line 27: #define UART_RESET 0x204 > -same Done PS1, Line 28: #define UART_RESET_EN (3 << 0) > -same Done -- To view, visit https://review.coreboot.org/19001 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I881da01be8191270d9505737f68a6d2d8cd8cc69 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/skylake: Clean up serialio header file.
by Aamir Bohra (Code Review) 27 Mar '17

27 Mar '17

Hello Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19001 to look at the new patch set (#2). Change subject: soc/intel/skylake: Clean up serialio header file. ...................................................................... soc/intel/skylake: Clean up serialio header file. Move and rename I2C and UART specific macro definitions under serialio.h to i2c.h and uart.h respectively. Change-Id: I881da01be8191270d9505737f68a6d2d8cd8cc69 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/skylake/bootblock/i2c.c M src/soc/intel/skylake/bootblock/uart.c A src/soc/intel/skylake/include/soc/i2c.h M src/soc/intel/skylake/include/soc/serialio.h A src/soc/intel/skylake/include/soc/uart.h 5 files changed, 79 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/19001/2 -- To view, visit https://review.coreboot.org/19001 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I881da01be8191270d9505737f68a6d2d8cd8cc69 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins)

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Change in coreboot[master]: mainboard: Add Sapphire Pure Platinum H61
by Arthur Heymans (Code Review) 27 Mar '17

27 Mar '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/18564 ) Change subject: mainboard: Add Sapphire Pure Platinum H61 ...................................................................... Patch Set 13: (1 comment) https://review.coreboot.org/#/c/18564/13//COMMIT_MSG Commit Message: PS13, Line 47: * If an external card is inserted and the option : ONBOARD_VGA_IS_PRIMARY is not enabled, the internal GPU : disappears completely from the PCI bus. > IMO, this is completely an unexpected behaviour, as many users (me included I'm not entirely sure IGD can work when it's not PRIMARY. uma resources (somewhat accidentally) are still allocated on sandy/ivy bridge, so just removing that line in disable_peg() should provide an answer if this is possible. -- To view, visit https://review.coreboot.org/18564 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I76aca2cfc4708c1728ae03ee4f6bc59d976c28a0 Gerrit-PatchSet: 13 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/skylake: Use intel/common/uart driver
by build bot (Jenkins) (Code Review) 27 Mar '17

27 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19003 ) Change subject: soc/intel/skylake: Use intel/common/uart driver ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/50700/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/6679/ : SUCCESS -- To view, visit https://review.coreboot.org/19003 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Id132df15ae5a6aef75d6434df18fc71d8d28c3ca Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: 3rdparty/blobs: Update for AMD Stoney Ridge
by build bot (Jenkins) (Code Review) 27 Mar '17

27 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18988 ) Change subject: 3rdparty/blobs: Update for AMD Stoney Ridge ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/50695/ : SUCCESS -- To view, visit https://review.coreboot.org/18988 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I1c9b5ded6b494fac1553cc2ec7756a7a47386ecf Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Use intel/common/uart driver
by Aamir Bohra (Code Review) 27 Mar '17

27 Mar '17

Aamir Bohra has uploaded a new change for review. ( https://review.coreboot.org/19003 ) Change subject: soc/intel/skylake: Use intel/common/uart driver ...................................................................... soc/intel/skylake: Use intel/common/uart driver Change-Id: Id132df15ae5a6aef75d6434df18fc71d8d28c3ca Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/bootblock/bootblock.c M src/soc/intel/skylake/bootblock/uart.c M src/soc/intel/skylake/include/soc/bootblock.h 4 files changed, 9 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/19003/1 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index a56d044..d68736b 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -49,6 +49,7 @@ select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_UART select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_LPSS_I2C select SOC_INTEL_COMMON_NHLT diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c index c11d3d2..eb1ff5c 100644 --- a/src/soc/intel/skylake/bootblock/bootblock.c +++ b/src/soc/intel/skylake/bootblock/bootblock.c @@ -30,7 +30,7 @@ pch_early_iorange_init(); if (IS_ENABLED(CONFIG_UART_DEBUG)) - pch_uart_init(); + soc_console_uart_init(); } void bootblock_soc_init(void) diff --git a/src/soc/intel/skylake/bootblock/uart.c b/src/soc/intel/skylake/bootblock/uart.c index 4889428..5fad038 100644 --- a/src/soc/intel/skylake/bootblock/uart.c +++ b/src/soc/intel/skylake/bootblock/uart.c @@ -15,15 +15,13 @@ * GNU General Public License for more details. */ -#include <arch/io.h> #include <console/uart.h> -#include <device/pci_def.h> -#include <stdint.h> +#include <gpio.h> +#include <intelblocks/uart.h> #include <soc/bootblock.h> #include <soc/pci_devs.h> #include <soc/pcr.h> -#include <soc/uart.h> -#include <gpio.h> + /* UART2 pad configuration. Support RXD and TXD for now. */ static const struct pad_config uart2_pads[] = { @@ -31,35 +29,10 @@ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), }; -void pch_uart_init(void) +void soc_console_uart_init(void) { - device_t dev = PCH_DEV_UART2; - u32 tmp; - u8 *base = (void *)uart_platform_base(CONFIG_UART_FOR_CONSOLE); - - /* Set configured UART2 base address */ - pci_write_config32(dev, PCI_BASE_ADDRESS_0, (u32)base); - - /* Enable memory access and bus master */ - tmp = pci_read_config32(dev, PCI_COMMAND); - tmp |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, tmp); - - /* Take UART2 out of reset */ - tmp = read32(base + UART_RESET); - tmp |= UART_RESET_EN | UART_RESET_DMA_EN; - write32(base + UART_RESET, tmp); - - /* - * Set M and N divisor inputs and enable clock. - * Main reference frequency to UART is: - * 120MHz * M / N = 120MHz * 48 / 3125 = 1843200Hz - */ - tmp = read32(base + UART_CLK); - tmp |= UART_CLK_EN | UART_CLK_UPDATE | - UART_CLK_DIV_N(UART_CLK_N_VAL) | - UART_CLK_DIV_M(UART_CLK_M_VAL); - write32(base + UART_CLK, tmp); + soc_uart_init(PCH_DEV_UART2, + uart_platform_base(CONFIG_UART_FOR_CONSOLE)); /* Put UART2 in byte access mode for 16550 compatibility */ if (!IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32)) diff --git a/src/soc/intel/skylake/include/soc/bootblock.h b/src/soc/intel/skylake/include/soc/bootblock.h index df81d3f..0a4c4af 100644 --- a/src/soc/intel/skylake/include/soc/bootblock.h +++ b/src/soc/intel/skylake/include/soc/bootblock.h @@ -26,7 +26,7 @@ void bootblock_cpu_init(void); void bootblock_pch_early_init(void); void bootblock_systemagent_early_init(void); -void pch_uart_init(void); +void soc_console_uart_init(void); /* Bootblock post console init programing */ void enable_smbus(void); -- To view, visit https://review.coreboot.org/19003 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Id132df15ae5a6aef75d6434df18fc71d8d28c3ca Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com>

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Change in coreboot[master]: util/amdfwtool: Add fanless SMU firmware
by build bot (Jenkins) (Code Review) 27 Mar '17

27 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18991 ) Change subject: util/amdfwtool: Add fanless SMU firmware ...................................................................... Patch Set 3: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/50698/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/6677/ : SUCCESS -- To view, visit https://review.coreboot.org/18991 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I4b80ccf8fd9644f9a9d300e6c67aed9834a2c7a7 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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coreboot-gerrit March 2017