build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18984 )
Change subject: vboot: Move remaining features out of vendorcode/google/chromeos
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Patch Set 9: Verified+1
Build Successful
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https://qa.coreboot.org/job/coreboot-checkpatch/6795/ : SUCCESS
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Barnali Sarkar has posted comments on this change. ( https://review.coreboot.org/18557 )
Change subject: soc/intel/common/block: [WIP]Add Intel common FAST_SPI code
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Patch Set 12:
(1 comment)
https://review.coreboot.org/#/c/18557/12/src/soc/intel/common/block/include…
File src/soc/intel/common/block/include/intelblocks/fast_spi.h:
Line 87: #define SPIBAR_HSFSTS_W1C_BITS (0xff)
> Okay, I think I got your point.
Aaron,
I did like what I mentioned in the above comment.
But while doing so, came across many places where the MACROs of SPI MMIO register definitions are used throughout the code like, skylake/bootblock/cpu.c, skylake/flash_controller.c, skylake/pch.c, skylake/finalize.c, etc.
So, in that case I had to explicitly add fast_spi_def.h (as I mentioned in the above comment) from many places in the code.
SO, I think we should keep the current implementation as is with a single header file intelblocks/fast_spi.h having everything, and include this header from wherever required (like that is done for systemagent).
What is your suggestion on this?
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18984 )
Change subject: vboot: Move remaining features out of vendorcode/google/chromeos
......................................................................
Patch Set 8:
Build Failed
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https://qa.coreboot.org/job/coreboot-checkpatch/6787/ : ABORTED
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Change subject: vboot: Disallow separate verstage after romstage, try to clarify logic
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Patch Set 8:
Build Failed
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https://qa.coreboot.org/job/coreboot-checkpatch/6786/ : SUCCESS
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