coreboot-gerrit March 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/apollolake: Code clean up by using common PCR module
by build bot (Jenkins) (Code Review) 29 Mar '17

29 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18673 ) Change subject: soc/intel/apollolake: Code clean up by using common PCR module ...................................................................... Patch Set 6: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/50901/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/6872/ : SUCCESS -- To view, visit https://review.coreboot.org/18673 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Iacbf58dbd55bf3915676d875fcb484362d357a44 Gerrit-PatchSet: 6 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: Fix debug build booting issue
by Subrata Banik (Code Review) 29 Mar '17

29 Mar '17

Subrata Banik has uploaded a new change for review. ( https://review.coreboot.org/19036 ) Change subject: soc/intel/apollolake: Fix debug build booting issue ...................................................................... soc/intel/apollolake: Fix debug build booting issue This patch fix apollolake devices unable to boot with coreboot debug image issue. Change-Id: I28943100ba19dec1e540fdbba1c1e110c6af1488 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/apollolake/pmutil.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/19036/1 diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 7d3cb07..9e57b28 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -505,7 +505,7 @@ ROMSTAGE_CONST struct soc_intel_apollolake_config *config; /* Look up the device in devicetree */ - ROMSTAGE_CONST struct device *dev = SA_DEV_ROOT; + ROMSTAGE_CONST struct device *dev = dev_find_slot(0, SA_DEVFN_ROOT); if (!dev || !dev->chip_info) { printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); return; -- To view, visit https://review.coreboot.org/19036 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I28943100ba19dec1e540fdbba1c1e110c6af1488 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/skylake: Code clean up by using common PCR module
by Subrata Banik (Code Review) 29 Mar '17

29 Mar '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/18674 to look at the new patch set (#6). Change subject: soc/intel/skylake: Code clean up by using common PCR module ...................................................................... soc/intel/skylake: Code clean up by using common PCR module This patch creates PCR library to perform CRRd and CRWr operation using Port Ids, define inside soc/pci_ids.h Change-Id: Id9336883514298e7f93fbc95aef8228202aa6fb9 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/Makefile.inc M src/soc/intel/skylake/acpi/irqlinks.asl M src/soc/intel/skylake/acpi/pch.asl M src/soc/intel/skylake/acpi/pcr.asl M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/skylake/bootblock/uart.c M src/soc/intel/skylake/finalize.c M src/soc/intel/skylake/gpio.c M src/soc/intel/skylake/include/soc/iomap.h D src/soc/intel/skylake/include/soc/pcr.h A src/soc/intel/skylake/include/soc/pcr_ids.h M src/soc/intel/skylake/lpc.c D src/soc/intel/skylake/pcr.c M src/soc/intel/skylake/pmc.c M src/soc/intel/skylake/smihandler.c 16 files changed, 144 insertions(+), 338 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/18674/6 -- To view, visit https://review.coreboot.org/18674 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: Id9336883514298e7f93fbc95aef8228202aa6fb9 Gerrit-PatchSet: 6 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com>

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Change in coreboot[master]: soc/intel/common/block: Add Intel common PCR support
by Subrata Banik (Code Review) 29 Mar '17

29 Mar '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/18669 to look at the new patch set (#4). Change subject: soc/intel/common/block: Add Intel common PCR support ...................................................................... soc/intel/common/block: Add Intel common PCR support IOSF_SB message space is used to access registers mapped on IOSF-SB. These registers include uncore CRs (configuration registers) and chipset specific registers. The Private Configuration Register (PCR) space is accessed on IOSF-SB using destination ID also known as Port ID. Access to IOSF-SB by the Host or System Agent is possible over PSF via the Primary to Sideband Bridge (P2SB). P2SB will forward properly formatted register access requests as CRRd and CRWr request via IOSF-SB. Change-Id: I78526a86b6d10f226570c08050327557e0bb2c78 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- A src/soc/intel/common/block/include/intelblocks/pcr.h A src/soc/intel/common/block/pcr/Kconfig A src/soc/intel/common/block/pcr/Makefile.inc A src/soc/intel/common/block/pcr/pcr.c 4 files changed, 214 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/18669/4 -- To view, visit https://review.coreboot.org/18669 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I78526a86b6d10f226570c08050327557e0bb2c78 Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com>

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Change in coreboot[master]: soc/intel/apollolake: Code clean up by using common PCR module
by Subrata Banik (Code Review) 29 Mar '17

29 Mar '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/18673 to look at the new patch set (#6). Change subject: soc/intel/apollolake: Code clean up by using common PCR module ...................................................................... soc/intel/apollolake: Code clean up by using common PCR module This patch creates PCR library to perform CRRd and CRWr operation using Port Ids, define inside soc/pci_ids.h Change-Id: Iacbf58dbd55bf3915676d875fcb484362d357a44 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/acpi/gpio.asl M src/soc/intel/apollolake/acpi/scs.asl M src/soc/intel/apollolake/bootblock/bootblock.c M src/soc/intel/apollolake/gpio.c M src/soc/intel/apollolake/include/soc/gpio_defs.h M src/soc/intel/apollolake/include/soc/iomap.h D src/soc/intel/apollolake/include/soc/iosf.h A src/soc/intel/apollolake/include/soc/pcr_ids.h M src/soc/intel/apollolake/itss.c 10 files changed, 122 insertions(+), 132 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/18673/6 -- To view, visit https://review.coreboot.org/18673 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iacbf58dbd55bf3915676d875fcb484362d357a44 Gerrit-PatchSet: 6 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com>

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Change in coreboot[master]: soc/intel/common/block: Add Intel common PCR support
by Subrata Banik (Code Review) 29 Mar '17

29 Mar '17

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/18669 ) Change subject: soc/intel/common/block: Add Intel common PCR support ...................................................................... Patch Set 3: (13 comments) https://review.coreboot.org/#/c/18669/3/src/soc/intel/apollolake/include/so… File src/soc/intel/apollolake/include/soc/pcr_ids.h: PS3, Line 43: ~3 > This should have parens Done https://review.coreboot.org/#/c/18669/3/src/soc/intel/common/block/include/… File src/soc/intel/common/block/include/intelblocks/pcr.h: Line 19: #if !defined(__ASSEMBLER__) && !defined(__ACPI__) > Why would this header be included from assembler or ACPI code when it's all Done Line 23: int pcr_read32(u8 pid, u16 offset, u32 *outdata); > Can you just use uintX_t variants, please? Done https://review.coreboot.org/#/c/18669/3/src/soc/intel/common/block/pcr/pcr.c File src/soc/intel/common/block/pcr/pcr.c: PS3, Line 42: u32 > size_t for size Done PS3, Line 65: (u32 *) > cast not needed Done PS3, Line 70: (u32 *) > cast is wrong Done PS3, Line 75: (u32 *) > cast is wrong Done PS3, Line 93: (u32) > casts not needed here Done Line 109: pcr_read32(pid, offset, &data); > This is actually a property of inconsistent designed IPs on certain SoCs th >> This is actually a property of inconsistent designed IPs on certain SoCs that have posted write semantics. Is every SoC supposed to be impacted by that going forward? expectation may not be true for all future soc as well but its a safe mechanism to perform a read after write via IOSF-SB. >> And why was the construction (including comment) completely dropped. Presumably you were using skylake as the basis for "everything common" ? Apparently pcr library has been taken from big core code and after comparing small core IOSF read/write, its seems same as i have explained over commit message, both are performing access through PSF via IOSF_SB to PCRs. So, i don;t think there might be any reason to call it even skylake code or apollolake code, its a IP CR access mechanism. But i'm agree with you on SKL, we have seen some case where immediate read is needed after writing through SB registers. Hence we have added those "safety" piece of code in common library. I guess time taken for MMIO read should be marginal enough so, we should be good. >> Lastly, if you already had the address calculated (as you should pcr_reg_address(). Then all you need to do is read. But here you are reading a 32-bit address regardless of size passed in. That's wrong as well. good point, i have addressed PS3, Line 116: u32 > you should replace all these types with the 'indata' since the compiler kno Done PS3, Line 137: u32 > size_t for size Done PS3, Line 141: data32 = 0; > Why does this need to be initialized? Done Line 150: status = pch_pcr_write(pid, offset, size, data32); > Just 'return pch_pcr_write()'? Done -- To view, visit https://review.coreboot.org/18669 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I78526a86b6d10f226570c08050327557e0bb2c78 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: Yes

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Change in coreboot[master]: siemens/mc_apl1: Adjust gpio settings
by Werner Zeh (Code Review) 29 Mar '17

29 Mar '17

Werner Zeh has submitted this change and it was merged. ( https://review.coreboot.org/18995 ) Change subject: siemens/mc_apl1: Adjust gpio settings ...................................................................... siemens/mc_apl1: Adjust gpio settings Adjust gpio settings according to the hardware layout. Change-Id: I2f440e863c2e6f59298c500ac5aefa3b7386bcdf Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/18995 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/Makefile.inc M src/mainboard/siemens/mc_apl1/brd_gpio.h A src/mainboard/siemens/mc_apl1/gpio.c M src/mainboard/siemens/mc_apl1/mainboard.c M src/mainboard/siemens/mc_apl1/romstage.c 5 files changed, 444 insertions(+), 38 deletions(-) Approvals: Werner Zeh: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/mainboard/siemens/mc_apl1/Makefile.inc b/src/mainboard/siemens/mc_apl1/Makefile.inc index b4ab8a4..21df84c 100644 --- a/src/mainboard/siemens/mc_apl1/Makefile.inc +++ b/src/mainboard/siemens/mc_apl1/Makefile.inc @@ -4,5 +4,7 @@ # It is put down only to the better understanding. # The file is already included over src/arch/x86/Makefile.inc. romstage-y += romstage.c +romstage-y += gpio.c ramstage-y += mainboard.c +ramstage-y += gpio.c diff --git a/src/mainboard/siemens/mc_apl1/brd_gpio.h b/src/mainboard/siemens/mc_apl1/brd_gpio.h index 564ee69..0858a1a 100644 --- a/src/mainboard/siemens/mc_apl1/brd_gpio.h +++ b/src/mainboard/siemens/mc_apl1/brd_gpio.h @@ -16,39 +16,9 @@ #include <soc/gpio.h> -#if ENV_ROMSTAGE - -static const struct pad_config gpio_table[] = { - /* Debug tracing. */ - PAD_CFG_NF(GPIO_0, NATIVE, DEEP, NF1), - PAD_CFG_NF(GPIO_1, NATIVE, DEEP, NF1), - PAD_CFG_NF(GPIO_2, NATIVE, DEEP, NF1), - PAD_CFG_NF(GPIO_3, NATIVE, DEEP, NF1), - PAD_CFG_NF(GPIO_4, NATIVE, DEEP, NF1), - PAD_CFG_NF(GPIO_5, NATIVE, DEEP, NF1), - PAD_CFG_NF(GPIO_6, NATIVE, DEEP, NF1), - PAD_CFG_NF(GPIO_7, NATIVE, DEEP, NF1), - PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1), - - PAD_CFG_GPI(GPIO_152, DN_20K, DEEP), /* Unused */ - PAD_CFG_GPI(GPIO_19, UP_20K, DEEP), /* Unused */ - PAD_CFG_GPI(GPIO_13, UP_20K, DEEP), /* Unused */ - PAD_CFG_GPI(GPIO_17, UP_20K, DEEP), /* Unused */ - PAD_CFG_GPI(GPIO_15, UP_20K, DEEP), /* Unused */ - - PAD_CFG_NF(GPIO_210, NATIVE, DEEP, NF1), /* CLKREQ# */ - - PAD_CFG_NF(SMB_CLK, NATIVE, DEEP, NF1), - PAD_CFG_NF(SMB_DATA, NATIVE, DEEP, NF1), - PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), - PAD_CFG_NF(LPC_CLKOUT0, NATIVE, DEEP, NF1), - PAD_CFG_GPI(LPC_CLKOUT1, UP_20K, DEEP), /* LPC_CLKOUT1 -- unused */ - PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1), - PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1), - PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1), - PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1), - PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1), - PAD_CFG_NF(LPC_FRAMEB, UP_20K, DEEP, NF1), -}; - -#endif +/* + * The next set of functions return the gpio table and fill in the number of + * entries for each table. + */ +const struct pad_config *brd_gpio_table(size_t *num); +const struct pad_config *brd_early_gpio_table(size_t *num); diff --git a/src/mainboard/siemens/mc_apl1/gpio.c b/src/mainboard/siemens/mc_apl1/gpio.c new file mode 100644 index 0000000..bdeff73 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/gpio.c @@ -0,0 +1,425 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * Copyright (C) 2017 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <soc/gpio.h> +#include <commonlib/helpers.h> +#include "brd_gpio.h" + +/* + * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing' + * table found in EDS vol 1, but some pins aren't grouped functionally in + * the table so those were moved for more logical grouping. + */ +static const struct pad_config gpio_table[] = { + + /* Southwest Community */ + + /* PCIE_WAKE[0:3]_N */ + PAD_CFG_NF(GPIO_205, UP_20K, DEEP, NF1), /* PCIE_WAKE0_N */ + PAD_CFG_NF(GPIO_206, UP_20K, DEEP, NF1), /* PCIE_WAKE1_N */ + PAD_CFG_NF(GPIO_207, UP_20K, DEEP, NF1), /* PCIE_WAKE2_N */ + PAD_CFG_NF(GPIO_208, UP_20K, DEEP, NF1), /* PCIE_WAKE3_N */ + + /* EMMC interface. */ + PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1), /* EMMC_CLK */ + PAD_CFG_NF(GPIO_157, UP_20K, DEEP, NF1), /* EMMC_D0 */ + PAD_CFG_NF(GPIO_158, UP_20K, DEEP, NF1), /* EMMC_D1 */ + PAD_CFG_NF(GPIO_159, UP_20K, DEEP, NF1), /* EMMC_D2 */ + PAD_CFG_NF(GPIO_160, UP_20K, DEEP, NF1), /* EMMC_D3 */ + PAD_CFG_NF(GPIO_161, UP_20K, DEEP, NF1), /* EMMC_D4 */ + PAD_CFG_NF(GPIO_162, UP_20K, DEEP, NF1), /* EMMC_D5 */ + PAD_CFG_NF(GPIO_163, UP_20K, DEEP, NF1), /* EMMC_D6 */ + PAD_CFG_NF(GPIO_164, UP_20K, DEEP, NF1), /* EMMC_D7 */ + PAD_CFG_NF(GPIO_165, UP_20K, DEEP, NF1), /* EMMC_CMD */ + PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1), /* EMMC_RCLK */ + + /* SDIO -- unused */ + PAD_CFG_GPI(GPIO_166, DN_20K, DEEP), /* SDIO_CLK */ + PAD_CFG_GPI(GPIO_167, DN_20K, DEEP), /* SDIO_D0 */ + /* Configure SDIO to enable power gating. */ + PAD_CFG_GPI(GPIO_168, DN_20K, DEEP), /* SDIO_D1 */ + PAD_CFG_GPI(GPIO_169, DN_20K, DEEP), /* SDIO_D2 */ + PAD_CFG_GPI(GPIO_170, DN_20K, DEEP), /* SDIO_D3 */ + PAD_CFG_GPI(GPIO_171, DN_20K, DEEP), /* SDIO_CMD */ + + /* SDCARD */ + /* Pull down clock by 20K. */ + PAD_CFG_NF(GPIO_172, DN_20K, DEEP, NF1), /* SDCARD_CLK */ + PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1), /* SDCARD_D0 */ + PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1), /* SDCARD_D1 */ + PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1), /* SDCARD_D2 */ + PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1), /* SDCARD_D3 */ + /* Card detect is active LOW with external pull up. */ + PAD_CFG_NF(GPIO_177, UP_20K, DEEP, NF1), /* SDCARD_CD_N */ + PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1), /* SDCARD_CMD */ + /* CLK feedback, internal signal, needs 20K pull down. */ + PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1), /* SDCARD_CLK_FB */ + PAD_CFG_GPI(GPIO_186, UP_20K, DEEP), /* SDCARD_LVL_WP */ + /* EN_SD_SOCKET_PWR_L for SD slot power control. Default on. */ + PAD_CFG_GPO(GPIO_183, 0, DEEP), /* SDIO_PWR_DOWN_N */ + + /* SMBus */ + PAD_CFG_GPI(SMB_ALERTB, UP_20K, DEEP), /* SMB_ALERT _N */ + PAD_CFG_NF(SMB_CLK, UP_20K, DEEP, NF1), /* SMB_CLK */ + PAD_CFG_NF(SMB_DATA, UP_20K, DEEP, NF1), /* SMB_DATA */ + + /* LPC */ + PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), /* LPC_SERIRQ */ + PAD_CFG_NF(LPC_CLKOUT0, NONE, DEEP, NF1), /* LPC_CLKOUT0 */ + PAD_CFG_GPI(LPC_CLKOUT1, UP_20K, DEEP), /* LPC_CLKOUT1 */ + PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1), /* LPC_AD0 */ + PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1), /* LPC_AD1 */ + PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1), /* LPC_AD2 */ + PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1), /* LPC_AD3 */ + PAD_CFG_GPI(LPC_CLKRUNB, UP_20K, DEEP), /* LPC_CLKRUN_N */ + PAD_CFG_NF(LPC_FRAMEB, UP_20K, DEEP, NF1), /* LPC_FRAME_N */ + + /* West Community */ + + /* I2C0 - I2C Level Shifter */ + PAD_CFG_NF(GPIO_124, UP_2K, DEEP, NF1), /* LPSS_I2C0_SDA */ + PAD_CFG_NF(GPIO_125, UP_2K, DEEP, NF1), /* LPSS_I2C0_SCL */ + + /* I2C[1:7] -- unused */ + PAD_CFG_GPI(GPIO_126, UP_20K, DEEP), /* LPSS_I2C1_SDA */ + PAD_CFG_GPI(GPIO_127, UP_20K, DEEP), /* LPSS_I2C1_SCL */ + PAD_CFG_GPI(GPIO_128, UP_20K, DEEP), /* LPSS_I2C2_SDA */ + PAD_CFG_GPI(GPIO_129, UP_20K, DEEP), /* LPSS_I2C2_SCL */ + PAD_CFG_GPI(GPIO_130, UP_20K, DEEP), /* LPSS_I2C3_SDA */ + PAD_CFG_GPI(GPIO_131, UP_20K, DEEP), /* LPSS_I2C3_SCL */ + PAD_CFG_GPI(GPIO_132, UP_20K, DEEP), /* LPSS_I2C4_SDA */ + PAD_CFG_GPI(GPIO_133, UP_20K, DEEP), /* LPSS_I2C4_SCL */ + PAD_CFG_GPI(GPIO_134, UP_20K, DEEP), /* LPSS_I2C5_SDA */ + PAD_CFG_GPI(GPIO_135, UP_20K, DEEP), /* LPSS_I2C5_SCL */ + PAD_CFG_GPI(GPIO_136, UP_20K, DEEP), /* LPSS_I2C6_SDA */ + PAD_CFG_GPI(GPIO_137, UP_20K, DEEP), /* LPSS_I2C6_SCL */ + PAD_CFG_GPI(GPIO_138, UP_20K, DEEP), /* LPSS_I2C7_SDA */ + PAD_CFG_GPI(GPIO_139, UP_20K, DEEP), /* LPSS_I2C7_SCL */ + + /* ISH_GPIO_[0:9] -- unused */ + PAD_CFG_GPI(GPIO_146, DN_20K, DEEP), /* ISH_GPIO_0 */ + PAD_CFG_GPI(GPIO_147, DN_20K, DEEP), /* ISH_GPIO_1 */ + PAD_CFG_GPI(GPIO_148, DN_20K, DEEP), /* ISH_GPIO_2 */ + PAD_CFG_GPI(GPIO_149, DN_20K, DEEP), /* ISH_GPIO_3 */ + PAD_CFG_GPI(GPIO_150, DN_20K, DEEP), /* ISH_GPIO_4 */ + PAD_CFG_GPI(GPIO_151, DN_20K, DEEP), /* ISH_GPIO_5 */ + PAD_CFG_GPI(GPIO_152, DN_20K, DEEP), /* ISH_GPIO_6 */ + PAD_CFG_GPI(GPIO_153, DN_20K, DEEP), /* ISH_GPIO_7 */ + PAD_CFG_GPI(GPIO_154, DN_20K, DEEP), /* ISH_GPIO_8 */ + PAD_CFG_GPI(GPIO_155, DN_20K, DEEP), /* ISH_GPIO_9 */ + + /* PCIE_CLKREQ[0:3]_N */ + PAD_CFG_NF(GPIO_209, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_210, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_211, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_212, UP_20K, DEEP, NF1), + + /* OSC_CLK_OUT_0 - RES_CLK_CPU_FPGA */ + PAD_CFG_NF(OSC_CLK_OUT_0, DN_20K, DEEP, NF1), + /* OSC_CLK_OUT_[1:4] -- unused */ + PAD_CFG_GPI(OSC_CLK_OUT_1, DN_20K, DEEP), + PAD_CFG_GPI(OSC_CLK_OUT_2, DN_20K, DEEP), + PAD_CFG_GPI(OSC_CLK_OUT_3, DN_20K, DEEP), + PAD_CFG_GPI(OSC_CLK_OUT_4, DN_20K, DEEP), + + /* PMU Signals */ + PAD_CFG_GPI(PMU_AC_PRESENT, DN_20K, DEEP), /* PMU_AC_PRESENT */ + PAD_CFG_NF(PMU_BATLOW_B, UP_20K, DEEP, NF1), /* PMU_BATLOW_N */ + PAD_CFG_NF(PMU_PLTRST_B, NONE, DEEP, NF1), /* PMU_PLTRST_N */ + PAD_CFG_NF(PMU_PWRBTN_B, UP_20K, DEEP, NF1), /* PMU_PWRBTN_N */ + PAD_CFG_NF(PMU_RESETBUTTON_B, NONE, DEEP, NF1), /* PMU_RSTBTN_N */ + /* PMU_SLP_S0_N */ + PAD_CFG_NF_IOSSTATE(PMU_SLP_S0_B, NONE, DEEP, NF1, IGNORE), + PAD_CFG_NF(PMU_SLP_S3_B, NONE, DEEP, NF1), /* PMU_SLP_S3_N */ + PAD_CFG_NF(PMU_SLP_S4_B, NONE, DEEP, NF1), /* PMU_SLP_S4_N */ + PAD_CFG_NF(PMU_SUSCLK, NONE, DEEP, NF1), /* PMU_SUSCLK */ + PAD_CFG_GPO(PMU_WAKE_B, 1, DEEP), /* EN_PP3300_EMMC */ + PAD_CFG_NF(SUS_STAT_B, NONE, DEEP, NF1), /* SUS_STAT_N */ + PAD_CFG_NF(SUSPWRDNACK, NONE, DEEP, NF1), /* SUSPWRDNACK */ + + /* Northwest Community */ + + /* DDI0 SDA and SCL -- unused */ + PAD_CFG_GPI(GPIO_187, DN_20K, DEEP), /* HV_DDI0_DDC_SDA */ + PAD_CFG_GPI(GPIO_188, DN_20K, DEEP), /* HV_DDI0_DDC_SCL */ + /* DDI1 SDA and SCL - Display-Port */ + PAD_CFG_NF(GPIO_189, UP_20K, DEEP, NF1), /* HV_DDI1_DDC_SDA */ + PAD_CFG_NF(GPIO_190, UP_20K, DEEP, NF1), /* HV_DDI1_DDC_SCL */ + + /* MIPI I2C -- unused */ + PAD_CFG_GPI(GPIO_191, DN_20K, DEEP), /* MIPI_I2C_SDA */ + PAD_CFG_GPI(GPIO_192, DN_20K, DEEP), /* MIPI_I2C_SCL */ + + /* Panel 0 control -- unused */ + PAD_CFG_GPI(GPIO_193, DN_20K, DEEP), /* PNL0_VDDEN */ + PAD_CFG_GPI(GPIO_194, DN_20K, DEEP), /* PNL0_BKLTEN */ + PAD_CFG_GPI(GPIO_195, DN_20K, DEEP), /* PNL0_BKLTCTL */ + + /* Panel 1 control -- unused */ + PAD_CFG_NF(GPIO_196, DN_20K, DEEP, NF1), /* PNL1_VDDEN */ + PAD_CFG_NF(GPIO_197, DN_20K, DEEP, NF1), /* PNL1_BKLTEN */ + PAD_CFG_NF(GPIO_198, DN_20K, DEEP, NF1), /* PNL1_BKLTCTL */ + + /* DDI[0:1]_HPD -- unused */ + PAD_CFG_GPI(GPIO_199, UP_20K, DEEP), /* XHPD_DP */ + PAD_CFG_GPI(GPIO_200, DN_20K, DEEP), /* unused */ + + /* MDSI signals -- unused */ + PAD_CFG_GPI(GPIO_201, DN_20K, DEEP), /* MDSI_A_TE */ + PAD_CFG_GPI(GPIO_202, DN_20K, DEEP), /* MDSI_C_TE */ + + /* USB overcurrent pins. */ + PAD_CFG_NF(GPIO_203, UP_20K, DEEP, NF1), /* USB_OC0_N */ + PAD_CFG_NF(GPIO_204, UP_20K, DEEP, NF1), /* USB_OC1_N */ + + /* PMC SPI -- almost entirely unused. */ + PAD_CFG_GPI(PMC_SPI_FS0, UP_20K, DEEP), + PAD_CFG_NF(PMC_SPI_FS1, UP_20K, DEEP, NF2), /* XHPD_EDP_APL */ + PAD_CFG_GPI(PMC_SPI_FS2, UP_20K, DEEP), + PAD_CFG_GPI(PMC_SPI_RXD, DN_20K, DEEP), + PAD_CFG_GPI(PMC_SPI_TXD, DN_20K, DEEP), + PAD_CFG_GPI(PMC_SPI_CLK, DN_20K, DEEP), + + /* PMIC Signals unused signals related to an old PMIC interface. */ + PAD_CFG_GPO(PMIC_PWRGOOD, 1, DEEP), /* PMIC_PWRGOOD */ + PAD_CFG_GPI(PMIC_RESET_B, NONE, DEEP), /* PMIC_RESET_B */ + PAD_CFG_GPI(GPIO_213, DN_20K, DEEP), /* NFC_OUT_RESERVE */ + PAD_CFG_GPI(GPIO_214, DN_20K, DEEP), /* NFC_EN */ + PAD_CFG_GPI(GPIO_215, DN_20K, DEEP), /* NFC_IN_RESERVE */ + /* THERMTRIP_N */ + PAD_CFG_NF(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1), + PAD_CFG_GPO(PMIC_STDBY, 1, DEEP), /* unused */ + PAD_CFG_NF(PROCHOT_B, UP_20K, DEEP, NF1), /* PROCHOT_N */ + PAD_CFG_NF(PMIC_I2C_SCL, UP_1K, DEEP, NF1), /* PMIC_I2C_SCL */ + PAD_CFG_NF(PMIC_I2C_SDA, UP_1K, DEEP, NF1), /* PMIC_I2C_SDA */ + + /* I2S1 -- unused */ + PAD_CFG_GPI(GPIO_74, DN_20K, DEEP), /* I2S1_MCLK */ + PAD_CFG_GPI(GPIO_75, DN_20K, DEEP), /* I2S1_BCLK */ + PAD_CFG_GPI(GPIO_76, DN_20K, DEEP), /* I2S1_WS_SYNC */ + PAD_CFG_GPI(GPIO_77, DN_20K, DEEP), /* I2S1_SDI */ + PAD_CFG_GPI(GPIO_78, DN_20K, DEEP), /* I2S1_SDO */ + + /* DMIC or I2S4 -- unused */ + PAD_CFG_GPI(GPIO_79, DN_20K, DEEP), /* AVS_M_CLK_A1 */ + PAD_CFG_GPI(GPIO_80, DN_20K, DEEP), /* AVS_M_CLK_B1 */ + PAD_CFG_GPI(GPIO_81, DN_20K, DEEP), /* AVS_M_DATA_1 */ + PAD_CFG_GPI(GPIO_82, DN_20K, DEEP), /* AVS_M_CLK_AB2 */ + PAD_CFG_GPI(GPIO_83, DN_20K, DEEP), /* AVS_M_DATA_2 */ + + /* I2S2 -- unused */ + PAD_CFG_GPI(GPIO_84, DN_20K, DEEP), /* AVS_I2S2_MCLK */ + PAD_CFG_GPI(GPIO_85, DN_20K, DEEP), /* AVS_I2S2_BCLK */ + PAD_CFG_GPI(GPIO_86, DN_20K, DEEP), /* AVS_I2S2_WS_SYNC */ + PAD_CFG_GPI(GPIO_87, DN_20K, DEEP), /* AVS_I2S2_SDI */ + PAD_CFG_GPI(GPIO_88, DN_20K, DEEP), /* AVS_I2S2_SDO */ + + /* I2S3 -- unused */ + PAD_CFG_GPI(GPIO_89, DN_20K, DEEP), /* AVS_I2S3_BCLK */ + PAD_CFG_GPI(GPIO_90, DN_20K, DEEP), /* AVS_I2S3_WS_SYNC */ + PAD_CFG_GPI(GPIO_91, DN_20K, DEEP), /* AVS_I2S3_SDI */ + PAD_CFG_GPI(GPIO_92, DN_20K, DEEP), /* AVS_I2S3_SDO */ + + /* Fast SPI */ + /* FST_SPI_CS0_B */ + PAD_CFG_NF_IOSSTATE(GPIO_97, NATIVE, DEEP, NF1, IGNORE), + /* FST_SPI_CS1_B -- unused */ + PAD_CFG_GPI(GPIO_98, DN_20K, DEEP), + /* FST_SPI_MOSI_IO0 */ + PAD_CFG_NF_IOSSTATE(GPIO_99, NATIVE, DEEP, NF1, IGNORE), + /* FST_SPI_MISO_IO1 */ + PAD_CFG_NF_IOSSTATE(GPIO_100, NATIVE, DEEP, NF1, IGNORE), + /* FST_IO2 -- MEM_CONFIG0 */ + PAD_CFG_NF(GPIO_101, NATIVE, DEEP, NF1), + /* FST_IO3 -- MEM_CONFIG1 */ + PAD_CFG_NF(GPIO_102, NATIVE, DEEP, NF1), + /* FST_SPI_CLK */ + PAD_CFG_NF_IOSSTATE(GPIO_103, NATIVE, DEEP, NF1, IGNORE), + /* FST_SPI_CLK_FB */ + PAD_CFG_NF_IOSSTATE(FST_SPI_CLK_FB, NATIVE, DEEP, NF1, IGNORE), + + /* SIO_SPI_0 -- unused */ + PAD_CFG_GPI(GPIO_104, DN_20K, DEEP), /* GP_SSP_0_CLK */ + PAD_CFG_GPI(GPIO_105, DN_20K, DEEP), /* GP_SSP_0_FS0 */ + PAD_CFG_GPI(GPIO_106, UP_20K, DEEP), /* GP_SSP_0_FS1 */ + PAD_CFG_GPI(GPIO_109, DN_20K, DEEP), /* GP_SSP_0_RXD */ + PAD_CFG_GPI(GPIO_110, DN_20K, DEEP), /* GP_SSP_0_TXD */ + + /* SIO_SPI_1 -- unused */ + PAD_CFG_GPI(GPIO_111, DN_20K, DEEP), /* GP_SSP_1_CLK */ + PAD_CFG_GPI(GPIO_112, DN_20K, DEEP), /* GP_SSP_1_FS0 */ + PAD_CFG_GPI(GPIO_113, DN_20K, DEEP), /* GP_SSP_1_FS1 */ + PAD_CFG_GPI(GPIO_116, DN_20K, DEEP), /* GP_SSP_1_RXD */ + PAD_CFG_GPI(GPIO_117, DN_20K, DEEP), /* GP_SSP_1_TXD */ + + /* SIO_SPI_2 -- unused */ + PAD_CFG_GPI(GPIO_118, DN_20K, DEEP), /* GP_SSP_2_CLK */ + PAD_CFG_GPI(GPIO_119, DN_20K, DEEP), /* GP_SSP_2_FS0 */ + PAD_CFG_GPI(GPIO_120, DN_20K, DEEP), /* GP_SSP_2_FS1 */ + PAD_CFG_GPI(GPIO_121, DN_20K, DEEP), /* GP_SSP_2_FS2 */ + PAD_CFG_GPI(GPIO_122, DN_20K, DEEP), /* GP_SSP_2_RXD */ + PAD_CFG_GPI(GPIO_123, UP_20K, DEEP), /* GP_SSP_2_TXD */ + + /* North Community */ + + /* Debug tracing. */ + PAD_CFG_GPI(GPIO_0, DN_20K, DEEP), /* TRACE_0_CLK_VNN */ + PAD_CFG_GPI(GPIO_1, DN_20K, DEEP), /* TRACE_0_DATA0_VNN */ + PAD_CFG_GPI(GPIO_2, DN_20K, DEEP), /* TRACE_0_DATA1_VNN */ + PAD_CFG_GPI(GPIO_3, DN_20K, DEEP), /* TRACE_0_DATA2_VNN */ + PAD_CFG_GPI(GPIO_4, DN_20K, DEEP), /* TRACE_0_DATA3_VNN */ + PAD_CFG_GPI(GPIO_5, DN_20K, DEEP), /* TRACE_0_DATA4_VNN */ + PAD_CFG_GPI(GPIO_6, DN_20K, DEEP), /* TRACE_0_DATA5_VNN */ + PAD_CFG_GPI(GPIO_7, DN_20K, DEEP), /* TRACE_0_DATA6_VNN */ + PAD_CFG_GPI(GPIO_8, DN_20K, DEEP), /* TRACE_0_DATA7_VNN */ + + PAD_CFG_GPI(GPIO_9, DN_20K, DEEP), /* TRACE_1_CLK_VNN */ + PAD_CFG_GPI(GPIO_10, DN_20K, DEEP), /* TRACE_1_DATA0_VNN */ + PAD_CFG_GPI(GPIO_11, DN_20K, DEEP), /* TRACE_1_DATA1_VNN */ + PAD_CFG_GPI(GPIO_12, DN_20K, DEEP), /* TRACE_1_DATA2_VNN */ + PAD_CFG_GPI(GPIO_13, DN_20K, DEEP), /* TRACE_1_DATA3_VNN */ + PAD_CFG_GPI(GPIO_14, DN_20K, DEEP), /* TRACE_1_DATA4_VNN */ + PAD_CFG_GPI(GPIO_15, DN_20K, DEEP), /* TRACE_1_DATA5_VNN */ + PAD_CFG_GPI(GPIO_16, DN_20K, DEEP), /* TRACE_1_DATA6_VNN */ + PAD_CFG_GPI(GPIO_17, DN_20K, DEEP), /* TRACE_1_DATA7_VNN */ + + PAD_CFG_GPI(GPIO_18, UP_20K, DEEP), /* TRACE_2_CLK_VNN */ + PAD_CFG_GPI(GPIO_19, UP_20K, DEEP), /* TRACE_2_DATA0_VNN */ + PAD_CFG_GPI(GPIO_20, DN_20K, DEEP), /* TRACE_2_DATA1_VNN */ + PAD_CFG_GPI(GPIO_21, DN_20K, DEEP), /* TRACE_2_DATA2_VNN */ + PAD_CFG_GPI(GPIO_22, DN_20K, DEEP), /* TRACE_2_DATA3_VNN */ + PAD_CFG_GPI(GPIO_23, DN_20K, DEEP), /* TRACE_2_DATA4_VNN */ + PAD_CFG_GPI(GPIO_24, DN_20K, DEEP), /* TRACE_2_DATA5_VNN */ + PAD_CFG_GPI(GPIO_25, DN_20K, DEEP), /* TRACE_2_DATA6_VNN */ + PAD_CFG_GPI(GPIO_26, DN_20K, DEEP), /* TRACE_2_DATA7_VNN */ + + PAD_CFG_GPI(GPIO_27, DN_20K, DEEP), /* TRIGOUT_0 */ + PAD_CFG_GPI(GPIO_28, DN_20K, DEEP), /* TRIGOUT_1 */ + PAD_CFG_GPI(GPIO_29, DN_20K, DEEP), /* TRIGIN_0 */ + + PAD_CFG_GPI(GPIO_30, DN_20K, DEEP), /* ISH_GPIO_12 */ + PAD_CFG_GPI(GPIO_31, DN_20K, DEEP), /* ISH_GPIO_13 */ + PAD_CFG_GPI(GPIO_32, DN_20K, DEEP), /* ISH_GPIO_14 */ + PAD_CFG_GPI(GPIO_33, DN_20K, DEEP), /* ISH_GPIO_15 */ + + /* PWM[0:3] -- unused */ + PAD_CFG_GPI(GPIO_34, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_35, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_36, DN_20K, DEEP), + PAD_CFG_GPI(GPIO_37, DN_20K, DEEP), + + /* LPSS_UART[0:2] */ + PAD_CFG_GPI(GPIO_38, UP_20K, DEEP), /* LPSS_UART0_RXD - unused */ + PAD_CFG_GPI(GPIO_39, DN_20K, DEEP), /* LPSS_UART0_TXD - unused */ + PAD_CFG_GPI(GPIO_40, DN_20K, DEEP), /* LPSS_UART0_RTS - unused */ + PAD_CFG_GPI(GPIO_41, UP_20K, DEEP), /* LPSS_UART0_CTS - unused */ + PAD_CFG_GPI(GPIO_42, UP_20K, DEEP), /* LPSS_UART1_RXD - unused */ + PAD_CFG_GPI(GPIO_43, DN_20K, DEEP), /* LPSS_UART1_TXD - unused */ + PAD_CFG_GPI(GPIO_44, UP_20K, DEEP), /* LPSS_UART1_RTS - unused */ + PAD_CFG_GPI(GPIO_45, UP_20K, DEEP), /* LPSS_UART1_CTS - unused */ + PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* LPSS_UART2_RXD */ + /* LPSS_UART2_TXD */ + PAD_CFG_NF_IOSSTATE(GPIO_47, NATIVE, DEEP, NF1, Tx1RXDCRx0), + PAD_CFG_GPI(GPIO_48, DN_20K, DEEP), /* LPSS_UART2_RTS - unused */ + PAD_CFG_GPI(GPIO_49, UP_20K, DEEP), /* LPSS_UART2_CTS - unused */ + + /* Camera interface -- completely unused. */ + PAD_CFG_GPI(GPIO_62, DN_20K, DEEP), /* GP_CAMERASB00 */ + PAD_CFG_GPI(GPIO_63, DN_20K, DEEP), /* GP_CAMERASB01 */ + PAD_CFG_GPI(GPIO_64, DN_20K, DEEP), /* GP_CAMERASB02 */ + PAD_CFG_GPI(GPIO_65, DN_20K, DEEP), /* GP_CAMERASB03 */ + PAD_CFG_GPI(GPIO_66, DN_20K, DEEP), /* GP_CAMERASB04 */ + PAD_CFG_GPI(GPIO_67, DN_20K, DEEP), /* GP_CAMERASB05 */ + PAD_CFG_GPI(GPIO_68, DN_20K, DEEP), /* GP_CAMERASB06 */ + PAD_CFG_GPI(GPIO_69, DN_20K, DEEP), /* GP_CAMERASB07 */ + PAD_CFG_GPI(GPIO_70, DN_20K, DEEP), /* GP_CAMERASB08 */ + PAD_CFG_GPI(GPIO_71, DN_20K, DEEP), /* GP_CAMERASB09 */ + PAD_CFG_GPI(GPIO_72, DN_20K, DEEP), /* GP_CAMERASB10 */ + PAD_CFG_GPI(GPIO_73, DN_20K, DEEP), /* GP_CAMERASB11 */ + + /* JTAG interface. */ + PAD_CFG_NF(TCK, DN_20K, DEEP, NF1), /* TCK */ + PAD_CFG_NF(TRST_B, DN_20K, DEEP, NF1), /* TRST_B */ + PAD_CFG_NF(TMS, UP_20K, DEEP, NF1), /* TMS */ + PAD_CFG_NF(TDI, UP_20K, DEEP, NF1), /* TDI */ + PAD_CFG_NF(CX_PMODE, NONE, DEEP, NF1), /* CX_PMODE */ + PAD_CFG_NF(CX_PREQ_B, UP_20K, DEEP, NF1), /* CX_PREQ_B */ + PAD_CFG_NF(JTAGX, UP_20K, DEEP, NF1), /* JTAGX */ + PAD_CFG_NF(CX_PRDY_B, UP_20K, DEEP, NF1), /* CX_PRDY_B */ + PAD_CFG_NF(TDO, UP_20K, DEEP, NF1), /* TDO */ + + /* CNV bridge described into IAFW Vol2. */ + /* GPIO_[216:219] described into EDS Vol1. */ + PAD_CFG_GPO(CNV_BRI_DT, 0, DEEP), /* Reserve of FPGA */ + PAD_CFG_GPO(CNV_BRI_RSP, 0, DEEP), /* Reserve of FPGA */ + PAD_CFG_GPO(CNV_RGI_DT, 0, DEEP), /* Reserve of FPGA */ + PAD_CFG_NF(CNV_RGI_RSP, UP_20K, DEEP, NF1), /* eMMC */ + + /* Serial VID */ + PAD_CFG_NF(SVID0_ALERT_B, NONE, DEEP, NF1), /* SVID0_ALERT_B */ + PAD_CFG_NF(SVID0_DATA, UP_20K, DEEP, NF1), /* SVID0_DATA */ + PAD_CFG_NF(SVID0_CLK, UP_20K, DEEP, NF1), /* SVID0_CLK */ +}; + +const struct pad_config *__attribute__((weak)) brd_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* GPIOs needed prior to ramstage. */ +static const struct pad_config early_gpio_table[] = { + + /* Debug tracing. */ + PAD_CFG_GPI(GPIO_0, DN_20K, DEEP), /* TRACE_0_CLK_VNN */ + PAD_CFG_GPI(GPIO_1, DN_20K, DEEP), /* TRACE_0_DATA0_VNN */ + PAD_CFG_GPI(GPIO_2, DN_20K, DEEP), /* TRACE_0_DATA1_VNN */ + PAD_CFG_GPI(GPIO_3, DN_20K, DEEP), /* TRACE_0_DATA2_VNN */ + PAD_CFG_GPI(GPIO_4, DN_20K, DEEP), /* TRACE_0_DATA3_VNN */ + PAD_CFG_GPI(GPIO_5, DN_20K, DEEP), /* TRACE_0_DATA4_VNN */ + PAD_CFG_GPI(GPIO_6, DN_20K, DEEP), /* TRACE_0_DATA5_VNN */ + PAD_CFG_GPI(GPIO_7, DN_20K, DEEP), /* TRACE_0_DATA6_VNN */ + PAD_CFG_GPI(GPIO_8, DN_20K, DEEP), /* TRACE_0_DATA7_VNN */ + + PAD_CFG_GPO(GPIO_13, 0, DEEP), /* PERST# */ + PAD_CFG_GPO(GPIO_15, 0, DEEP), /* PERST# */ + PAD_CFG_GPO(GPIO_17, 1, DEEP), /* PFET */ + PAD_CFG_GPO(GPIO_19, 1, DEEP), /* PFET */ + PAD_CFG_GPO(GPIO_152, 0, DEEP), /* PERST# */ + + /* SMBus */ + PAD_CFG_NF(SMB_CLK, UP_20K, DEEP, NF1), /* SMB_CLK */ + PAD_CFG_NF(SMB_DATA, UP_20K, DEEP, NF1), /* SMB_DATA */ + + /* LPC */ + PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), /* LPC_SERIRQ */ + PAD_CFG_NF(LPC_CLKOUT0, UP_20K, DEEP, NF1), /* LPC_CLKOUT0 */ + /* LPC_CLKOUT1 - unused */ + PAD_CFG_GPI(LPC_CLKOUT1, DN_20K, DEEP), + PAD_CFG_NF(LPC_AD0, UP_20K, DEEP, NF1), /* LPC_AD0 */ + PAD_CFG_NF(LPC_AD1, UP_20K, DEEP, NF1), /* LPC_AD1 */ + PAD_CFG_NF(LPC_AD2, UP_20K, DEEP, NF1), /* LPC_AD2 */ + PAD_CFG_NF(LPC_AD3, UP_20K, DEEP, NF1), /* LPC_AD3 */ + PAD_CFG_GPI(LPC_CLKRUNB, UP_20K, DEEP), /* LPC_CLKRUN_N */ + PAD_CFG_NF(LPC_FRAMEB, UP_20K, DEEP, NF1), /* LPC_FRAME_N */ +}; + +const struct pad_config *__attribute__((weak)) +brd_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/siemens/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/mainboard.c index 1c2dd19..692a076 100644 --- a/src/mainboard/siemens/mc_apl1/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/mainboard.c @@ -19,6 +19,7 @@ #include <string.h> #include <hwilib.h> #include <i210.h> +#include "brd_gpio.h" #define MAX_PATH_DEPTH 12 #define MAX_NUM_MAPPINGS 10 @@ -100,7 +101,11 @@ static void mainboard_init(void *chip_info) { - /* Nothing Here Yet */ + const struct pad_config *pads; + size_t num; + + pads = brd_gpio_table(&num); + gpio_configure_pads(pads, num); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/siemens/mc_apl1/romstage.c b/src/mainboard/siemens/mc_apl1/romstage.c index 9dd42bc..3347f23 100644 --- a/src/mainboard/siemens/mc_apl1/romstage.c +++ b/src/mainboard/siemens/mc_apl1/romstage.c @@ -47,8 +47,12 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) { + const struct pad_config *pads; + size_t num; + /* setup early gpio before memory */ - gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + pads = brd_early_gpio_table(&num); + gpio_configure_pads(pads, num); /* DRAM Config settings */ memupd->FspmConfig.Package = 0x1; -- To view, visit https://review.coreboot.org/18995 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I2f440e863c2e6f59298c500ac5aefa3b7386bcdf Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins)

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Change in coreboot[master]: cbfstool/ifwitool: Remove unnecessary assignment
by Werner Zeh (Code Review) 29 Mar '17

29 Mar '17

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/18667 ) Change subject: cbfstool/ifwitool: Remove unnecessary assignment ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/18667 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I6c322a335a371a20561b32e04e7dcc7310dab607 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: intel/minnow3: Clean up Kconfig, devicetree and FMAP
by Werner Zeh (Code Review) 29 Mar '17

29 Mar '17

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/18963 ) Change subject: intel/minnow3: Clean up Kconfig, devicetree and FMAP ...................................................................... Patch Set 3: Code-Review+1 You are losing a lot of flash space due to the flashmap setup. Is there a reason not using as much space for CBFS as possible? -- To view, visit https://review.coreboot.org/18963 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I620dcbcd622f9326917c74b2a38984d9e49cff2b Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Brenton Dong <brenton.m.dong(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: Brenton Dong <brenton.m.dong(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/google/reef: turn off DMIC_CLK_B1 in S0ix
by Martin Roth (Code Review) 29 Mar '17

29 Mar '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19018 ) Change subject: mainboard/google/reef: turn off DMIC_CLK_B1 in S0ix ...................................................................... mainboard/google/reef: turn off DMIC_CLK_B1 in S0ix Wake On Voice stream capture configuration is mono. It is sufficient to keep DMIC_CLK_A1 on in S0ix; so, turning off DMIC_CLK_B1. Power saving should be visible in the boards which has more than one DMIC connected. BUG=None BRANCH=None TEST=WoV and quad channel DMIC capture works Change-Id: Ic46d4c7b30b945eba47a05d78386f48e4a675a03 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Reviewed-on: https://review.coreboot.org/19018 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> Tested-by: build bot (Jenkins) --- M src/mainboard/google/reef/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 2 deletions(-) Approvals: Aaron Durbin: Looks good to me, approved Venkateswarlu V Vinjamuri: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c index c572b1e..a4cef02 100644 --- a/src/mainboard/google/reef/variants/baseboard/gpio.c +++ b/src/mainboard/google/reef/variants/baseboard/gpio.c @@ -222,8 +222,7 @@ /* DMIC or I2S4 */ /* AVS_DMIC_CLK_A1 */ PAD_CFG_NF_IOSSTATE(GPIO_79, NATIVE, DEEP, NF1, IGNORE), - /* AVS_DMIC_CLK_B1 */ - PAD_CFG_NF_IOSSTATE(GPIO_80, NATIVE, DEEP, NF1, IGNORE), + PAD_CFG_NF(GPIO_80, NATIVE, DEEP, NF1), /* AVS_DMIC_CLK_B1 */ PAD_CFG_NF(GPIO_81, NATIVE, DEEP, NF1), /* AVS_DMIC_DATA_1 */ PAD_CFG_GPI(GPIO_82, DN_20K, DEEP), /* unused -- strap */ PAD_CFG_NF(GPIO_83, NATIVE, DEEP, NF1), /* AVS_DMIC_DATA_2 */ -- To view, visit https://review.coreboot.org/19018 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: Ic46d4c7b30b945eba47a05d78386f48e4a675a03 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: HARSHAPRIYA N <harshapriya.n(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> Gerrit-Reviewer: build bot (Jenkins)

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coreboot-gerrit March 2017