coreboot-gerrit March 2017

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Change in coreboot[master]: soc/intel/apollolake: Fix debug build booting issue
by Martin Roth (Code Review) 29 Mar '17

29 Mar '17

Martin Roth has posted comments on this change. ( https://review.coreboot.org/19036 ) Change subject: soc/intel/apollolake: Fix debug build booting issue ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/19036 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I28943100ba19dec1e540fdbba1c1e110c6af1488 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: [NOTFORMERGE] squashed no AGESA_LEGACY_WRAPPER
by build bot (Jenkins) (Code Review) 29 Mar '17

29 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18629 ) Change subject: [NOTFORMERGE] squashed no AGESA_LEGACY_WRAPPER ...................................................................... Patch Set 7: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/50913/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/6884/ : SUCCESS -- To view, visit https://review.coreboot.org/18629 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ib5b52d08875165dbf0dfefcc56a8913d607493c9 Gerrit-PatchSet: 7 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: AGESA: Introduce AGESA_LEGACY_WRAPPER and its counterpart
by build bot (Jenkins) (Code Review) 29 Mar '17

29 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18628 ) Change subject: AGESA: Introduce AGESA_LEGACY_WRAPPER and its counterpart ...................................................................... Patch Set 7: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/50912/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/6883/ : SUCCESS -- To view, visit https://review.coreboot.org/18628 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Iac3d7f8b0354e9f02c2625576f36fe06b05eb4ce Gerrit-PatchSet: 7 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: siemens/mc_apl1: Activate PTN3460 eDP to LVDS bridge IC
by build bot (Jenkins) (Code Review) 29 Mar '17

29 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19043 ) Change subject: siemens/mc_apl1: Activate PTN3460 eDP to LVDS bridge IC ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/6882/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/50911/ : SUCCESS -- To view, visit https://review.coreboot.org/19043 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ib8fa79bb608f1842f26c1af3d7bf4bb0513fa94d Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: siemens/mc_apl1: Activate PTN3460 eDP to LVDS bridge IC
by Mario Scheithauer (Code Review) 29 Mar '17

29 Mar '17

Mario Scheithauer has uploaded a new change for review. ( https://review.coreboot.org/19043 ) Change subject: siemens/mc_apl1: Activate PTN3460 eDP to LVDS bridge IC ...................................................................... siemens/mc_apl1: Activate PTN3460 eDP to LVDS bridge IC This mainboard uses a LVDS connection for LCD panels. Apollo Lake SoC provides a display controller with three independent pipes (1x eDP and 2x DP/HDMI). PTN3460 is an embedded DisplayPort to LVDS bridge device that enables connectivity between an eDP source and LVDS display panel. The bridge contains an On-chip EDIT emulation for EDIT data structures. This patch sets up PTN3460 to be used with the appropriate LCD panel. Change-Id: Ib8fa79bb608f1842f26c1af3d7bf4bb0513fa94d Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/Makefile.inc A src/mainboard/siemens/mc_apl1/lcd_panel.c A src/mainboard/siemens/mc_apl1/lcd_panel.h M src/mainboard/siemens/mc_apl1/mainboard.c A src/mainboard/siemens/mc_apl1/ptn3460.c A src/mainboard/siemens/mc_apl1/ptn3460.h 6 files changed, 358 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/19043/1 diff --git a/src/mainboard/siemens/mc_apl1/Makefile.inc b/src/mainboard/siemens/mc_apl1/Makefile.inc index 21df84c..847b264 100644 --- a/src/mainboard/siemens/mc_apl1/Makefile.inc +++ b/src/mainboard/siemens/mc_apl1/Makefile.inc @@ -8,3 +8,5 @@ ramstage-y += mainboard.c ramstage-y += gpio.c +ramstage-y += lcd_panel.c +ramstage-y += ptn3460.c diff --git a/src/mainboard/siemens/mc_apl1/lcd_panel.c b/src/mainboard/siemens/mc_apl1/lcd_panel.c new file mode 100644 index 0000000..b639769 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/lcd_panel.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014-2017 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbfs.h> +#include <console/console.h> +#include <string.h> +#include "soc/gpio.h" +#include "lcd_panel.h" +#include "ptn3460.h" + +/** + * Set up LCD panel. + * + * @param No parameters. + * @return 0 on success otherwise error value. + */ +int setup_lcd_panel(void) +{ + int status; + char blockname[33]; + + strcpy(blockname, "hwinfo.hex"); + /* Now that we have the panel type, set up the DP2LVDS converter. */ + status = ptn3460_init(blockname); + if (status) + printk(BIOS_ERR, "LCD: Setup PTN with status 0x%x\n", status); + else + printk(BIOS_INFO, "LCD: Setup PTN with status 0x%x\n", status); + + return status; +} diff --git a/src/mainboard/siemens/mc_apl1/lcd_panel.h b/src/mainboard/siemens/mc_apl1/lcd_panel.h new file mode 100644 index 0000000..1a89974 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/lcd_panel.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014-2017 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _LCD_PANEL_H_ +#define _LCD_PANEL_H_ + +/* This GPIOs are used for LCD panel type encoding. */ +#define LCD_TYPE_GPIO_BIT0 40 +#define LCD_TYPE_GPIO_BIT1 41 +#define LCD_TYPE_GPIO_BIT2 42 +#define LCD_TYPE_GPIO_BIT3 43 + +#define LCD_PANEL_TYPE_10_INCH 4 +#define LCD_PANEL_TYPE_12_INCH 7 +#define LCD_PANEL_TYPE_15_INCH 6 +#define LCD_PANEL_TYPE_19_INCH 1 +#define LCD_PANEL_TYPE_EDID 15 + +int setup_lcd_panel(void); + +#endif /* _LCD_PANEL_H_ */ diff --git a/src/mainboard/siemens/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/mainboard.c index 692a076..63944c3 100644 --- a/src/mainboard/siemens/mc_apl1/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/mainboard.c @@ -14,12 +14,15 @@ * GNU General Public License for more details. */ +#include <device/pci.h> #include <device/device.h> #include <console/console.h> +#include <soc/pci_devs.h> #include <string.h> #include <hwilib.h> #include <i210.h> #include "brd_gpio.h" +#include "lcd_panel.h" #define MAX_PATH_DEPTH 12 #define MAX_NUM_MAPPINGS 10 @@ -108,6 +111,16 @@ gpio_configure_pads(pads, num); } +/** + * mainboard_final() is executed after enumerate_buses(). + * setup_lcd_panel() may only be execute after i2c bus init. + */ +static void mainboard_final(void *chip_info) +{ + setup_lcd_panel(); +} + struct chip_operations mainboard_ops = { .init = mainboard_init, + .final = mainboard_final, }; diff --git a/src/mainboard/siemens/mc_apl1/ptn3460.c b/src/mainboard/siemens/mc_apl1/ptn3460.c new file mode 100644 index 0000000..be9c9dd --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/ptn3460.c @@ -0,0 +1,174 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014-2017 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <lib.h> +#include <hwilib.h> +#include <device/i2c.h> +#include <soc/i2c.h> +#include "ptn3460.h" + +/** + * This functions sets up the DP2LVDS-converter to be used with the appropriate + * lcd panel. + * + * @param *hwi_block Filename in CBFS of the block to use as HW-Info. + * @return 0 on success or error code. + */ +int ptn3460_init(char *hwi_block) +{ + struct ptn_3460_config cfg; + int status; + uint8_t disp_con = 0, color_depth = 0; + uint8_t edid_data[0x80]; + int i; + + if (!hwi_block || hwilib_find_blocks(hwi_block) != CB_SUCCESS) { + printk(BIOS_ERR, "LCD: Info block \"%s\" not found!\n", + hwi_block); + return 1; + } + /* Get all needed information from hwinfo block. */ + if (hwilib_get_field(Edid, edid_data, 0x80) != sizeof(edid_data)) { + printk(BIOS_ERR, "LCD: No EDID data available in %s\n", + hwi_block); + return 1; + } + if ((hwilib_get_field(PF_DisplCon, &disp_con, 1) != 1)) { + printk(BIOS_ERR, "LCD: Missing panel features from %s\n", + hwi_block); + return 1; + } + if (hwilib_get_field(PF_Color_Depth, &color_depth, 1) != 1) { + printk(BIOS_ERR, "LCD: Missing panel features from %s\n", + hwi_block); + return 1; + } + /* + * Here, all the desired information for setting up DP2LVDS converter + * are present. Inside the converter, table 6 will be used for the + * timings. + */ + status = ptn3460_write_edid(6, edid_data); + if (status) + return status; + /* Select this table to be emulated. */ + ptn_select_edid(6); + /* Read PTN configuration data. */ + status = i2c_read_bytes(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, + PTN_CONFIG_OFF, (uint8_t *)&cfg, + PTN_CONFIG_LEN); + if (status) + return (PTN_BUS_ERROR | status); + /* Set up configuration data according to the hwinfo blocks we get. */ + cfg.dp_interface_ctrl = 0; + cfg.lvds_interface_ctrl1 = 0x00; + if (disp_con == PF_DISPLCON_LVDS_DUAL) + /* Turn on dual LVDS lane and clock. */ + cfg.lvds_interface_ctrl1 |= 0x0b; + if (color_depth == PF_COLOR_DEPTH_6BIT) + /* Use 18 bits per pixel. */ + cfg.lvds_interface_ctrl1 |= 0x20; + + /* No clock spreading, 300 mV LVDS swing. */ + cfg.lvds_interface_ctrl2 = 0x03; + /* No LVDS signal swap. */ + cfg.lvds_interface_ctrl3 = 0x00; + /* Delay T2 (VDD to LVDS active) by 16 ms. */ + cfg.t2_delay = 1; + /* 250 ms from LVDS to backlight active. */ + cfg.t3_timing = 5; + /* 1 second re-power delay. */ + cfg.t12_timing = 20; + /* 150 ms backlight off to LVDS inactive. */ + cfg.t4_timing = 3; + /* Delay T5 (LVDS to VDD inactive) by 16 ms. */ + cfg.t5_delay = 1; + /* Enable backlight control. */ + cfg.backlight_ctrl = 0; + + /* Write back configuration data to PTN3460. */ + for (i = 0; i < sizeof(struct ptn_3460_config); i++) { + status = i2c_writeb(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, + PTN_CONFIG_OFF+i, + (uint8_t)*(((uint8_t *)&cfg)+i)); + if (status) + return (PTN_BUS_ERROR | status); + } + + /* Read PTN configuration data. */ + status = i2c_read_bytes(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, + PTN_CONFIG_OFF, (uint8_t *)&cfg, PTN_CONFIG_LEN); + if (status) + return (PTN_BUS_ERROR | status); + + return PTN_NO_ERROR; +} + +/** + * This functions writes one EDID data structure to PTN3460. + * + * @param edid_num Number of EDID that must be written (0..6). + * @param *data Pointer to a buffer where data to write is stored in. + * @return 0 on success or error code. + */ +int ptn3460_write_edid(u8 edid_num, u8 *data) +{ + int status; + int i; + + if (edid_num > PTN_MAX_EDID_NUM) + return PTN_INVALID_EDID; + + /* First enable access to the desired EDID table. */ + status = i2c_writeb(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, + PTN_CONFIG_OFF + 5, edid_num); + if (status) + return (PTN_BUS_ERROR | status); + + /* Now we can simply write EDID-data to ptn3460. */ + for (i = 0; i < PTN_EDID_LEN; i++) { + status = i2c_writeb(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, + PTN_EDID_OFF + i, data[i]); + if (status) + return (PTN_BUS_ERROR | status); + } + + return PTN_NO_ERROR; +} + +/** + * This functions selects one of 7 EDID-tables inside PTN3460 which should be + * emulated on display port and turn emulation ON. + * + * @param edid_num Number of EDID to emulate (0..6). + * @return 0 on success or error code. + */ +int ptn_select_edid(u8 edid_num) +{ + int status; + uint8_t val; + + if (edid_num > PTN_MAX_EDID_NUM) + return PTN_INVALID_EDID; + /* Enable emulation of the desired EDID table. */ + val = (edid_num << 1) | 1; + status = i2c_writeb(PTN_I2C_CONTROLLER, PTN_SLAVE_ADR, + PTN_CONFIG_OFF + 4, val); + if (status) + return (PTN_BUS_ERROR | status); + else + return PTN_NO_ERROR; +} diff --git a/src/mainboard/siemens/mc_apl1/ptn3460.h b/src/mainboard/siemens/mc_apl1/ptn3460.h new file mode 100644 index 0000000..9f44074 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/ptn3460.h @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014-2017 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef PTN3460_H_ +#define PTN3460_H_ + +#include <delay.h> +#include "lcd_panel.h" + +#define PTN_SLAVE_ADR 0x20 +#define PTN_I2C_CONTROLLER 0 + +#define PTN_EDID_OFF 0x00 +#define PTN_EDID_LEN 0x80 +#define PTN_CONFIG_OFF 0x80 +#define PTN_CONFIG_LEN 0x19 +#define PTN_FLASH_CFG_OFF 0xE8 +#define PTN_FLASH_CFG_LEN 0x04 +#define PTN_MAX_EDID_NUM 6 + +/* Define some error codes that can be used. */ +#define PTN_NO_ERROR 0x00000000 +#define PTN_BUS_ERROR 0x10000000 +#define PTN_INVALID_EDID 0x20000000 + +struct ptn_3460_config { + /* DiplayPort interface control. */ + u8 dp_interface_ctrl; + /* LVDS interface control register 1. */ + u8 lvds_interface_ctrl1; + /* LVDS interface control register 2. */ + u8 lvds_interface_ctrl2; + /* LVDS interface control register 3. */ + u8 lvds_interface_ctrl3; + /* Select which EDID-block is emulated. */ + u8 edid_rom_emulation; + /* Select which EDID block to map to 0..0x7F. */ + u8 edid_rom_access_ctrl; + /* Smallest PWM frequency for back light. */ + u8 pwm_min[3]; + /* Biggest PWM frequency for back light. */ + u8 pwm_max[3]; + /* Fast link training control register. */ + u8 fast_link_ctrl; + /* Pin configuration control register 1. */ + u8 pin_cfg_ctrl1; + /* Pin configuration control register 2. */ + u8 pin_cfg_ctrl2; + /* Default PWM bit count in DPCD register. */ + u8 pwm_default; + /* Current PWM bit count in DPCD register. */ + u16 pwm_value; + /* Default PWM frequency in DPCD register. */ + u8 pwm_default_freq; + /* Panel T3 timing value. */ + u8 t3_timing; + /* Panel T12 timing value. */ + u8 t12_timing; + /* Back light control register. */ + u8 backlight_ctrl; + /* Panel T2 delay. */ + u8 t2_delay; + /* Panel T4 timing value. */ + u8 t4_timing; + /* Panel T5 delay. */ + u8 t5_delay; +} __attribute__((packed)); + +struct ptn_3460_flash { + /* Flash command (erase or erase and flash). */ + u8 cmd; + /* Magic number needed by the flash algorithm. */ + u16 magic; + /* Trigger for starting flash operation. */ + u8 trigger; +} __attribute__((packed)); + +int ptn3460_init(char *hwi_block); +int ptn3460_write_edid(u8 edid_num, u8 *data); +int ptn_select_edid(u8 edid_num); +#endif /* PTN3460_H_ */ -- To view, visit https://review.coreboot.org/19043 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Ib8fa79bb608f1842f26c1af3d7bf4bb0513fa94d Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com>

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Change in coreboot[master]: AGESA: Disable CAR with empty stack
by build bot (Jenkins) (Code Review) 29 Mar '17

29 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18626 ) Change subject: AGESA: Disable CAR with empty stack ...................................................................... Patch Set 6: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/6881/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/50910/ : SUCCESS -- To view, visit https://review.coreboot.org/18626 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I986bb7a88f53f7f7a0b05d4edcd5020f5dbeb4b7 Gerrit-PatchSet: 6 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Code clean up by using common PCR module
by build bot (Jenkins) (Code Review) 29 Mar '17

29 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18674 ) Change subject: soc/intel/skylake: Code clean up by using common PCR module ...................................................................... Patch Set 7: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/6880/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/50908/ : SUCCESS -- To view, visit https://review.coreboot.org/18674 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Id9336883514298e7f93fbc95aef8228202aa6fb9 Gerrit-PatchSet: 7 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: Code clean up by using common PCR module
by build bot (Jenkins) (Code Review) 29 Mar '17

29 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18673 ) Change subject: soc/intel/apollolake: Code clean up by using common PCR module ...................................................................... Patch Set 7: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/6879/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/50909/ : SUCCESS -- To view, visit https://review.coreboot.org/18673 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Iacbf58dbd55bf3915676d875fcb484362d357a44 Gerrit-PatchSet: 7 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common/block: Add Intel common PCR support
by build bot (Jenkins) (Code Review) 29 Mar '17

29 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18669 ) Change subject: soc/intel/common/block: Add Intel common PCR support ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/6878/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/50907/ : SUCCESS -- To view, visit https://review.coreboot.org/18669 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I78526a86b6d10f226570c08050327557e0bb2c78 Gerrit-PatchSet: 5 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common/block: Add Intel common PCR support
by Subrata Banik (Code Review) 29 Mar '17

29 Mar '17

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/18669 ) Change subject: soc/intel/common/block: Add Intel common PCR support ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/#/c/18669/4/src/soc/intel/common/block/pcr/pcr.c File src/soc/intel/common/block/pcr/pcr.c: PS4, Line 117: int pcr_write32(uint8_t pid, uint16_t offset, uint32_t indata) : { : return pch_pcr_write(pid, offset, sizeof(indata), indata); : } : : int pcr_write16(uint8_t pid, uint16_t offset, uint16_t indata) : { : return pch_pcr_write(pid, offset, sizeof(indata), indata); : } : : int pcr_write8(uint8_t pid, uint16_t offset, uint8_t indata) : { : return pch_pcr_write(pid, offset, sizeof(indata), indata); : } : : /* : * Write PCR register. (This is internal function) : * It programs PCR register and size in 1/2/4 bytes. : * The offset should not exceed 0xFFFF and must be aligned with size : * : * u8 defines as 8 bit Port ID that will be used when sending : * transaction to sideband. : */ : static int pcr_and_then_or(uint8_t pid, uint16_t offset, size_t size, : uint32_t anddata, uint32_t ordata) : { : uint32_t data32; : : if (pch_pcr_read(pid, offset, size, &data32) != 0) : return -1; : : data32 &= anddata; : data32 |= ordata; : : return pch_pcr_write(pid, offset, size, data32); : } : : int pcr_andthenor32(uint8_t pid, uint16_t offset, uint32_t anddata, : uint32_t ordata) : { : return pcr_and_then_or(pid, offset, sizeof(anddata), anddata, ordata); : } : : int pcr_andthenor16(uint8_t pid, uint16_t offset, uint16_t anddata, : uint16_t ordata) : { : return pcr_and_then_or(pid, offset, sizeof(anddata), anddata, ordata); : } : : int pcr_andthenor8(uint8_t pid, uint16_t offset, uint8_t anddata, : > i'm in a process to fix this as well Done -- To view, visit https://review.coreboot.org/18669 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I78526a86b6d10f226570c08050327557e0bb2c78 Gerrit-PatchSet: 5 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: Yes

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coreboot-gerrit March 2017