Barnali Sarkar (barnali.sarkar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18418
-gerrit
commit b580f90fb827ca1b89f4c36aa6d1c98eb0c47843
Author: Barnali Sarkar <barnali.sarkar(a)intel.com>
Date: Tue Feb 21 16:24:49 2017 +0530
soc/intel/common: Save Memory DIMM Information in SMBIOS Table
Save SMBIOS memory information from FSP MEM_INFO_DATA_HOB in CBMEM.
BUG=chrome-os-partner:61729
BRANCH=none
TEST=Build and boot KBLRVP to verify the Type17 DIMM Info coming in
SMBIOS Table from Kernel.
Change-Id: I0fd7c9887076d3fdd320fcbdcc873cb1965b950c
Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com>
---
src/soc/intel/common/Makefile.inc | 1 +
src/soc/intel/common/smbios.c | 55 +++++++++++++++++++++++++++++++++++++++
src/soc/intel/common/smbios.h | 23 ++++++++++++++++
3 files changed, 79 insertions(+)
diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc
index d6e1e75..25e51cd 100644
--- a/src/soc/intel/common/Makefile.inc
+++ b/src/soc/intel/common/Makefile.inc
@@ -13,6 +13,7 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c
romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
romstage-y += util.c
romstage-$(CONFIG_MMA) += mma.c
+romstage-y += smbios.c
postcar-y += util.c
postcar-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
diff --git a/src/soc/intel/common/smbios.c b/src/soc/intel/common/smbios.c
new file mode 100644
index 0000000..278de8e
--- /dev/null
+++ b/src/soc/intel/common/smbios.c
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <memory_info.h>
+#include <string.h>
+#include <smbios.h>
+#include "smbios.h"
+#include <console/console.h>
+
+
+void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type,
+ u32 frequency, u8 channel_id, u8 dimm_id, u8 *module_part_num,
+ u16 data_width)
+{
+ dimm->dimm_size = dimm_capacity;
+ dimm->ddr_type = ddr_type;
+ dimm->ddr_frequency = frequency;
+ dimm->channel_num = channel_id;
+ dimm->dimm_num = dimm_id;
+ strncpy((char *)dimm->module_part_number,
+ (char *)module_part_num,
+ sizeof(dimm->module_part_number));
+ switch (data_width) {
+ case 8:
+ dimm->bus_width = MEMORY_BUS_WIDTH_8;
+ break;
+ case 16:
+ dimm->bus_width = MEMORY_BUS_WIDTH_16;
+ break;
+ case 32:
+ dimm->bus_width = MEMORY_BUS_WIDTH_32;
+ break;
+ case 64:
+ dimm->bus_width = MEMORY_BUS_WIDTH_64;
+ break;
+ case 128:
+ dimm->bus_width = MEMORY_BUS_WIDTH_128;
+ break;
+ default:
+ printk(BIOS_ERR, "Incorrect DIMM Data Width");
+ }
+}
diff --git a/src/soc/intel/common/smbios.h b/src/soc/intel/common/smbios.h
new file mode 100644
index 0000000..34e1f37
--- /dev/null
+++ b/src/soc/intel/common/smbios.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _COMMON_SMBIOS_H_
+#define _COMMON_SMBIOS_H_
+
+void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type,
+ u32 frequency, u8 channel_id, u8 dimm_id, u8 *module_part_num,
+ u16 data_width);
+
+#endif /* _COMMON_SMBIOS_H_ */
Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18417
-gerrit
commit e1c7f9df86f66904270afa5896dc17fa403ff686
Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>
Date: Tue Feb 21 13:10:05 2017 +0100
commonlib/fsp.h: include sys/types.h for ssize_t
This file reportedly didn't compile on SUSE Linux with gcc 4.3.4:
[...]
> HOSTCC cbfstool/fsp_relocate.o
> In file included from /home/aladyshev/coreboot_2017/src/commonlib/fsp_relocate.c:18:
> /home/aladyshev/coreboot_2017/src/commonlib/include/commonlib/fsp.h:26: error: expected '=', ',', ';', 'asm' or '__attribute__' before 'fsp_component_relocate'
[...]
According to POSIX-2008[1], sys/types.h defines ssize_t, so include it.
This should not break coreboot code (as supposed to utils code), as we
have a sys/types.h in src/include.
[1]: http://pubs.opengroup.org/onlinepubs/9699919799/basedefs/sys_types.h.html
Change-Id: Id3694dc76c41d800ba09183e4b039b0719ac3d93
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>
---
src/commonlib/include/commonlib/fsp.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/commonlib/include/commonlib/fsp.h b/src/commonlib/include/commonlib/fsp.h
index 84e2c98..a2a2fae 100644
--- a/src/commonlib/include/commonlib/fsp.h
+++ b/src/commonlib/include/commonlib/fsp.h
@@ -18,6 +18,7 @@
#include <stddef.h>
#include <stdint.h>
+#include <sys/types.h>
/*
* Relocate FSP held within buffer defined by size to new_addr. Returns < 0
Barnali Sarkar (barnali.sarkar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18418
-gerrit
commit 32bf161ddfbeaee58363a916a7224a6e5a0c03de
Author: Barnali Sarkar <barnali.sarkar(a)intel.com>
Date: Tue Feb 21 16:24:49 2017 +0530
soc/intel/common: Save Memory DIMM Information in SMBIOS Table
Save SMBIOS memory information from FSP MEM_INFO_DATA_HOB in CBMEM.
BUG=chrome-os-partner:61729
BRANCH=none
TEST=Build and boot KBLRVP to verify the Type17 DIMM Info coming in
SMBIOS Table from Kernel.
Change-Id: I0fd7c9887076d3fdd320fcbdcc873cb1965b950c
Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com>
---
src/soc/intel/common/Makefile.inc | 1 +
src/soc/intel/common/smbios.c | 54 +++++++++++++++++++++++++++++++++++++++
src/soc/intel/common/smbios.h | 22 ++++++++++++++++
3 files changed, 77 insertions(+)
diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc
index d6e1e75..25e51cd 100644
--- a/src/soc/intel/common/Makefile.inc
+++ b/src/soc/intel/common/Makefile.inc
@@ -13,6 +13,7 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c
romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
romstage-y += util.c
romstage-$(CONFIG_MMA) += mma.c
+romstage-y += smbios.c
postcar-y += util.c
postcar-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c
diff --git a/src/soc/intel/common/smbios.c b/src/soc/intel/common/smbios.c
new file mode 100644
index 0000000..57426f2
--- /dev/null
+++ b/src/soc/intel/common/smbios.c
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <memory_info.h>
+#include <string.h>
+#include <smbios.h>
+#include "smbios.h"
+#include <console/console.h>
+
+
+void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type,
+ u32 frequency, u8 channel_id, u8 dimm_id, u8 *module_part_num, u16 data_width)
+{
+ dimm->dimm_size = dimm_capacity;
+ dimm->ddr_type = ddr_type;
+ dimm->ddr_frequency = frequency;
+ dimm->channel_num = channel_id;
+ dimm->dimm_num = dimm_id;
+ strncpy((char *)dimm->module_part_number,
+ (char *)module_part_num,
+ sizeof(dimm->module_part_number));
+ switch (data_width) {
+ case 8:
+ dimm->bus_width = MEMORY_BUS_WIDTH_8;
+ break;
+ case 16:
+ dimm->bus_width = MEMORY_BUS_WIDTH_16;
+ break;
+ case 32:
+ dimm->bus_width = MEMORY_BUS_WIDTH_32;
+ break;
+ case 64:
+ dimm->bus_width = MEMORY_BUS_WIDTH_64;
+ break;
+ case 128:
+ dimm->bus_width = MEMORY_BUS_WIDTH_128;
+ break;
+ default:
+ printk(BIOS_ERR, "Incorrect DIMM Data Width");
+ }
+}
diff --git a/src/soc/intel/common/smbios.h b/src/soc/intel/common/smbios.h
new file mode 100644
index 0000000..66526bd
--- /dev/null
+++ b/src/soc/intel/common/smbios.h
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Intel Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _COMMON_SMBIOS_H_
+#define _COMMON_SMBIOS_H_
+
+void dimm_info_fill(struct dimm_info *dimm, u32 dimm_capacity, u8 ddr_type,
+ u32 frequency, u8 channel_id, u8 dimm_id, u8 *module_part_num, u16 data_width);
+
+#endif /* _COMMON_SMBIOS_H_ */
Barnali Sarkar (barnali.sarkar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18326
-gerrit
commit c0e6b1d987858e451bd5a4d28e6cbba00f15e65e
Author: Barnali Sarkar <barnali.sarkar(a)intel.com>
Date: Fri Feb 10 21:46:05 2017 +0530
src/vendorcode: Add Memory Info Data HOB Header
Add the MemInfoHob.h provided by FSP for aid in parsing the
MEM_INFO_DATA_HOB.
BUG=chrome-os-partner:61729
BRANCH=none
TEST=Build and boot KBLRVP
Change-Id: Ia2b528ba4d9f093006cc12ee317d02e7f3e83166
Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com>
---
.../intel/fsp/fsp2_0/skykabylake/FspmUpd.h | 1 +
.../intel/fsp/fsp2_0/skykabylake/MemInfoHob.h | 214 +++++++++++++++++++++
2 files changed, 215 insertions(+)
diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h
index 89dc419..6bb57a1 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h
@@ -34,6 +34,7 @@ are permitted provided that the following conditions are met:
#define __FSPMUPD_H__
#include <FspUpd.h>
+#include "MemInfoHob.h"
#pragma pack(1)
diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h
new file mode 100644
index 0000000..8dc2db9
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h
@@ -0,0 +1,214 @@
+/** @file
+
+Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+#ifndef _MEM_INFO_HOB_H_
+#define _MEM_INFO_HOB_H_
+
+#pragma pack (push, 1)
+
+extern EFI_GUID gSiMemoryS3DataGuid;
+extern EFI_GUID gSiMemoryInfoDataGuid;
+extern EFI_GUID gSiMemoryPlatformDataGuid;
+
+#define MAX_NODE 1
+#define MAX_CH 2
+#define MAX_DIMM 2
+
+///
+/// Host reset states from MRC.
+///
+#define WARM_BOOT 2
+
+#define R_MC_CHNL_RANK_PRESENT 0x7C
+#define B_RANK0_PRS BIT0
+#define B_RANK1_PRS BIT1
+#define B_RANK2_PRS BIT4
+#define B_RANK3_PRS BIT5
+
+///
+/// Defines taken from MRC so avoid having to include MrcInterface.h
+///
+
+//
+// Matches MAX_SPD_SAVE define in MRC
+//
+#ifndef MAX_SPD_SAVE
+#define MAX_SPD_SAVE 29
+#endif
+
+//
+// MRC version description.
+//
+typedef struct {
+ UINT8 Major; ///< Major version number
+ UINT8 Minor; ///< Minor version number
+ UINT8 Rev; ///< Revision number
+ UINT8 Build; ///< Build number
+} SiMrcVersion;
+
+//
+// Matches MrcDimmSts enum in MRC
+//
+#ifndef DIMM_ENABLED
+#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.
+#endif
+#ifndef DIMM_DISABLED
+#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.
+#endif
+#ifndef DIMM_PRESENT
+#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.
+#endif
+#ifndef DIMM_NOT_PRESENT
+#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.
+#endif
+
+//
+// Matches MrcBootMode enum in MRC
+//
+#ifndef bmCold
+#define bmCold 0 // Cold boot
+#endif
+#ifndef bmWarm
+#define bmWarm 1 // Warm boot
+#endif
+#ifndef bmS3
+#define bmS3 2 // S3 resume
+#endif
+#ifndef bmFast
+#define bmFast 3 // Fast boot
+#endif
+
+//
+// Matches MrcDdrType enum in MRC
+//
+#ifndef MRC_DDR_TYPE_DDR4
+#define MRC_DDR_TYPE_DDR4 0
+#endif
+#ifndef MRC_DDR_TYPE_DDR3
+#define MRC_DDR_TYPE_DDR3 1
+#endif
+#ifndef MRC_DDR_TYPE_LPDDR3
+#define MRC_DDR_TYPE_LPDDR3 2
+#endif
+#ifndef MRC_DDR_TYPE_UNKNOWN
+#define MRC_DDR_TYPE_UNKNOWN 3
+#endif
+
+#define MAX_PROFILE_NUM 4 // number of memory profiles supported
+#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported
+
+//
+// DIMM timings
+//
+typedef struct {
+ UINT32 tCK; ///< Memory cycle time, in femtoseconds.
+ UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.
+ UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.
+ UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
+ UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
+ UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
+ UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
+ UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
+ UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+ UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+ UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
+ UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
+ UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
+ UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
+ UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
+ UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
+ UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
+ UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
+ UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
+ UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
+} MRC_CH_TIMING;
+
+///
+/// Memory SMBIOS & OC Memory Data Hob
+///
+typedef struct {
+ UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
+ UINT8 DimmId;
+ UINT32 DimmCapacity; ///< DIMM size in MBytes.
+ UINT16 MfgId;
+ UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
+ UINT8 RankInDimm; ///< The number of ranks in this DIMM.
+ UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
+ UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
+ UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
+ UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
+} DIMM_INFO;
+
+typedef struct {
+ UINT8 Status; ///< Indicates whether this channel should be used.
+ UINT8 ChannelId;
+ UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
+ MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
+ DIMM_INFO Dimm[MAX_DIMM]; ///< Save the DIMM output characteristics.
+} CHANNEL_INFO;
+
+typedef struct {
+ UINT8 Status; ///< Indicates whether this controller should be used.
+ UINT16 DeviceId; ///< The PCI device id of this memory controller.
+ UINT8 RevisionId; ///< The PCI revision id of this memory controller.
+ UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
+ CHANNEL_INFO Channel[MAX_CH]; ///< The following are channel level definitions.
+} CONTROLLER_INFO;
+
+typedef struct {
+ UINT8 Revision;
+ UINT16 DataWidth;
+ /** As defined in SMBIOS 3.0 spec
+ Section 7.18.2 and Table 75
+ **/
+ UINT8 DdrType; ///< DDR type: DDR3, DDR4, or LPDDR3
+ UINT32 Frequency; ///< The system's common memory controller frequency in MT/s.
+ /** As defined in SMBIOS 3.0 spec
+ Section 7.17.3 and Table 72
+ **/
+ UINT8 ErrorCorrectionType;
+
+ SiMrcVersion Version;
+ UINT32 FreqMax;
+ BOOLEAN EccSupport;
+ UINT8 MemoryProfile;
+ UINT32 TotalPhysicalMemorySize;
+ UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM]; // Stores the tCK value read from SPD XMP profiles if they exist.
+ UINT8 XmpProfileEnable; // If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
+ UINT8 Ratio;
+ UINT8 RefClk;
+ UINT32 VddVoltage[MAX_PROFILE_NUM];
+ CONTROLLER_INFO Controller[MAX_NODE];
+} MEMORY_INFO_DATA_HOB;
+
+#pragma pack (pop)
+
+#endif // _MEM_INFO_HOB_H_
Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18417
-gerrit
commit 306ba317b640d440df72cea6c888dc386a4df46e
Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>
Date: Tue Feb 21 13:10:05 2017 +0100
commonlib/fsp.h: include sys/types.h for ssize_t
This file reportedly didn't compile on SUSE Linux with gcc 4.3.4:
[...]
> HOSTCC cbfstool/fsp_relocate.o
> In file included from /home/aladyshev/coreboot_2017/src/commonlib/fsp_relocate.c:18:
> /home/aladyshev/coreboot_2017/src/commonlib/include/commonlib/fsp.h:26: error: expected '=', ',', ';', 'asm' or '__attribute__' before 'fsp_component_relocate'
[...]
According to POSIX-2008[1], sys/types.h defines ssize_t, so include it.
This should not break coreboot code (as supposed to utils code), as we
have a sys/types.h in src/include.
Don't include stdint.h as it doesn't define any of the types used in fsp.h.
[1]: http://pubs.opengroup.org/onlinepubs/9699919799/basedefs/sys_types.h.html
Change-Id: Id3694dc76c41d800ba09183e4b039b0719ac3d93
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>
---
src/commonlib/include/commonlib/fsp.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/commonlib/include/commonlib/fsp.h b/src/commonlib/include/commonlib/fsp.h
index 84e2c98..ec78caf 100644
--- a/src/commonlib/include/commonlib/fsp.h
+++ b/src/commonlib/include/commonlib/fsp.h
@@ -17,7 +17,7 @@
#define _COMMONLIB_FSP_H_
#include <stddef.h>
-#include <stdint.h>
+#include <sys/types.h>
/*
* Relocate FSP held within buffer defined by size to new_addr. Returns < 0
Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18417
-gerrit
commit b7fbfbc40f8937a1fab0b3f35ae6e278a5d617f2
Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>
Date: Tue Feb 21 13:10:05 2017 +0100
commonlib/fsp.h: include sys/types.h for ssize_t
This file reportedly didn't compile on SUSE Linux with gcc 4.3.4:
[...]
> HOSTCC cbfstool/fsp_relocate.o
> In file included from /home/aladyshev/coreboot_2017/src/commonlib/fsp_relocate.c:18:
> /home/aladyshev/coreboot_2017/src/commonlib/include/commonlib/fsp.h:26: error: expected '=', ',', ';', 'asm' or '__attribute__' before 'fsp_component_relocate'
[...]
According to the POSIX-2008[1], sys/types.h defines ssize_t, so include it.
This should not break coreboot code (as supposed to utils code), as we have a
sys/types.h in src/include.
Don't include stdint.h as it doesn't define any of the types used in fsp.h.
[1]: http://pubs.opengroup.org/onlinepubs/9699919799/basedefs/sys_types.h.html
Change-Id: Id3694dc76c41d800ba09183e4b039b0719ac3d93
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>
---
src/commonlib/include/commonlib/fsp.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/commonlib/include/commonlib/fsp.h b/src/commonlib/include/commonlib/fsp.h
index 84e2c98..ec78caf 100644
--- a/src/commonlib/include/commonlib/fsp.h
+++ b/src/commonlib/include/commonlib/fsp.h
@@ -17,7 +17,7 @@
#define _COMMONLIB_FSP_H_
#include <stddef.h>
-#include <stdint.h>
+#include <sys/types.h>
/*
* Relocate FSP held within buffer defined by size to new_addr. Returns < 0