Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18429
-gerrit
commit 2fa9d4473d342518d31220e8001c34934cd2535c
Author: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Date: Sun Jan 8 14:49:15 2017 -0500
amd/gardenia: Add cbmem_init to romstage
When EARLY_CBMEM_INIT is in effect, initialize cbmem during the mainboard's
romstage.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com>
(cherry picked from commit dbea129a63fa11e9f582075b432fdda3cc5b2a9c)
Change-Id: Ic336213580c4c8bf7e3b42c9adbbf0051982fec4
Signed-off-by: Marc Jones <marcj303(a)gmail.com>
---
src/mainboard/amd/gardenia/romstage.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/src/mainboard/amd/gardenia/romstage.c b/src/mainboard/amd/gardenia/romstage.c
index eca9d3b..2b495c8 100644
--- a/src/mainboard/amd/gardenia/romstage.c
+++ b/src/mainboard/amd/gardenia/romstage.c
@@ -14,6 +14,7 @@
*/
#include <console/console.h>
+#include <cbmem.h>
#include <arch/acpi.h>
#include <arch/io.h>
#include <arch/stages.h>
@@ -66,8 +67,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (!s3resume) {
post_code(0x40);
AGESAWRAPPER(amdinitpost);
+
+#if IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)
+ cbmem_initialize_empty();
+#endif
+
post_code(0x41);
AGESAWRAPPER(amdinitenv);
+
/* TODO: Disable cache is not ok. */
disable_cache_as_ram();
} else { /* S3 detect */
Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18428
-gerrit
commit d568cbda5dcd1f79f44bac7a789577d054fe2806
Author: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Date: Sun Jan 8 14:36:46 2017 -0500
amd/pi/stoney: Add memmap file
In preparation for supporting EARLY_CBMEM_INIT, add a new file that
will contain cbmem_top() and that can be used in all stages. Later
patches will also be able to use the support routines.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com>
(cherry picked from commit 4fec9f6754675bbe0c8fbfc031c5c5665dace34b)
Change-Id: I8ddaa8359536081752fb8e47e49f4d5958416620
Signed-off-by: Marc Jones <marcj303(a)gmail.com>
---
src/northbridge/amd/pi/00670F00/Makefile.inc | 3 +
src/northbridge/amd/pi/00670F00/memmap.c | 101 +++++++++++++++++++++++++++
src/northbridge/amd/pi/00670F00/memmap.h | 25 +++++++
3 files changed, 129 insertions(+)
diff --git a/src/northbridge/amd/pi/00670F00/Makefile.inc b/src/northbridge/amd/pi/00670F00/Makefile.inc
index 7107d84..46617b9 100644
--- a/src/northbridge/amd/pi/00670F00/Makefile.inc
+++ b/src/northbridge/amd/pi/00670F00/Makefile.inc
@@ -16,3 +16,6 @@
romstage-y += dimmSpd.c
ramstage-y += northbridge.c
+
+romstage-y += memmap.c
+ramstage-y += memmap.c
\ No newline at end of file
diff --git a/src/northbridge/amd/pi/00670F00/memmap.c b/src/northbridge/amd/pi/00670F00/memmap.c
new file mode 100644
index 0000000..02bfc13
--- /dev/null
+++ b/src/northbridge/amd/pi/00670F00/memmap.c
@@ -0,0 +1,101 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015-2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <cbmem.h>
+#include <cpu/amd/mtrr.h>
+#include "Porting.h"
+#include <AMD.h>
+#include "amdlib.h"
+#include "memmap.h"
+
+static uint32_t installed_dram(void)
+{
+ uint64_t topmem, topmem2;
+ uint32_t sysmem_mb, sysmem_gb;
+ AMD_CONFIG_PARAMS StdHeader;
+
+ LibAmdMsrRead (TOP_MEM, &topmem, &StdHeader);
+ LibAmdMsrRead (TOP_MEM2, &topmem2, &StdHeader);
+
+ if (!topmem && !topmem2)
+ return 0;
+
+ sysmem_mb = (topmem + (16ull << ONE_MB_SHIFT)) >> ONE_MB_SHIFT;
+ sysmem_mb += topmem2 ? ((topmem2 >> ONE_MB_SHIFT) - 4096) : 0;
+ sysmem_gb = sysmem_mb >> (ONE_GB_SHIFT - ONE_MB_SHIFT);
+
+ return sysmem_gb;
+}
+
+/*
+ * Return the size likely assigned to UMA when UMA_AUTO is specified.
+ * This is the only setting the wrapper currently implements. Refer to the
+ * BKDG for Family 15h Model 70h-7Fh Procesors (PID #55072) to find the
+ * following recommended configurations:
+ * Total system memory UMASize
+ * 6G+ 1024M
+ * 4G 512M
+ * 2G 256M
+ */
+uint32_t uma_size_auto(void)
+{
+ uint32_t sysmem_gb = installed_dram();
+
+ if (sysmem_gb >= 6)
+ return 1024 << ONE_MB_SHIFT;
+ if (sysmem_gb >= 4)
+ return 512 << ONE_MB_SHIFT;
+ if (sysmem_gb >= 2)
+ return 256 << ONE_MB_SHIFT;
+ if (sysmem_gb > 0)
+ return 128 << ONE_MB_SHIFT;
+ return 0;
+}
+
+/*
+ * The BinaryPI image is compiled to always assign UMA below 4GB. It will
+ * also adjust TOM/TOM2 for the C6 storage, as well as the audio controller.
+ */
+uint32_t uma_base_auto(void)
+{
+ uint64_t topmem;
+ AMD_CONFIG_PARAMS StdHeader;
+
+ LibAmdMsrRead (TOP_MEM, &topmem, &StdHeader);
+
+ if (!topmem)
+ return 0;
+
+ return (uint32_t)topmem - uma_size_auto();
+}
+
+#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT)
+unsigned long get_top_of_ram(void)
+{
+ AMD_CONFIG_PARAMS StdHeader;
+ UINT64 MsrReg;
+
+ LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader);
+ return (unsigned long)MsrReg;
+}
+#endif
+
+#if !IS_ENABLED(CONFIG_LATE_CBMEM_INIT)
+void *cbmem_top(void)
+{
+ return (void *)uma_base_auto();
+}
+#endif
diff --git a/src/northbridge/amd/pi/00670F00/memmap.h b/src/northbridge/amd/pi/00670F00/memmap.h
new file mode 100644
index 0000000..01fcdc5
--- /dev/null
+++ b/src/northbridge/amd/pi/00670F00/memmap.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef NORTHBRIDGE_AMD_MEMMAP_H
+#define NORTHBRIDGE_AMD_MEMMAP_H
+
+#define ONE_MB_SHIFT 20
+#define ONE_GB_SHIFT 30
+
+uint32_t uma_base_auto(void);
+uint32_t uma_size_auto(void);
+
+#endif /* NORTHBRIDGE_AMD_MEMMAP_H */
Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18427
-gerrit
commit 985fa75df764e3ad223fdcff7cde4671c84826d6
Author: Furquan Shaikh <furquan(a)chromium.org>
Date: Mon Feb 20 22:56:25 2017 -0800
arch/x86/acpigen: Provide helper functions for enabling/disabling GPIO
In order to allow GPIOs to be set/clear according to their polarity,
provide helper functions that check for polarity and call set/clear
SoC functions for generating ACPI code.
BUG=None
BRANCH=None
TEST=Verified that the ACPI code generated remains the same as before
for reef.
Change-Id: Ie8bdb9dc18e61a4a658f1447d6f1db0b166d9c12
Signed-off-by: Furquan Shaikh <furquan(a)chromium.org>
---
Documentation/acpi/gpio.md | 19 ++++++++++++++++++-
src/arch/x86/acpi_device.c | 10 +++++-----
src/arch/x86/acpigen.c | 23 +++++++++++++++++++++++
src/arch/x86/include/arch/acpigen.h | 11 +++++++++++
4 files changed, 57 insertions(+), 6 deletions(-)
diff --git a/Documentation/acpi/gpio.md b/Documentation/acpi/gpio.md
index 2c09148..2fb2d1d 100644
--- a/Documentation/acpi/gpio.md
+++ b/Documentation/acpi/gpio.md
@@ -3,6 +3,7 @@
# Table of contents #
- Introduction
- Platform Interface
+- Helper routines
- Implementation details
- Arguments and Local Variables Management
@@ -55,6 +56,23 @@ adding them as AML code callbacks for the following reasons:
3. Allows GPIO AML methods to be present under any device scope and
gives SoC the flexibility to call them without any restrictions.
+# Helper routines #
+
+In order to relieve drivers of the task of implementing the same code
+for enabling/disabling Tx GPIOs based on the GPIO polarity, helper
+routines are provided which implement this common code and can be used
+directly in the driver routines:
+1. Enable Tx GPIO
+ int acpigen_enable_tx_gpio(struct acpi_gpio gpio)
+2. Disable Tx GPIO
+ int acpigen_disable_tx_gpio(struct acpi_gpio gpio)
+
+Both the above functions take as input struct acpi_gpio type and
+return -1 on error and 0 on success. These helper routines end up
+calling the platform specific acpigen_soc_{set,clear}_tx_gpio
+functions internally. Thus, all the ACPI AML calling conventions for
+the platform functions apply to these helper functions as well.
+
# Implementation Details #
ACPI library in coreboot will provide weak definitions for all the
@@ -84,7 +102,6 @@ variables.
acpigen_soc_clear_tx_gpio Generate ACPI AML code to Error = -1
set Tx to 0. Success = 0
-
Ideally, the operation column in the above table should use one or
more functions implemented by the platform in AML code library (like
gpiolib.asl). In the example below SPC0 and GPC0 need to be
diff --git a/src/arch/x86/acpi_device.c b/src/arch/x86/acpi_device.c
index 4fe16a1..c4ba62e 100644
--- a/src/arch/x86/acpi_device.c
+++ b/src/arch/x86/acpi_device.c
@@ -512,14 +512,14 @@ void acpi_device_add_power_res(
/* Method (_ON, 0, Serialized) */
acpigen_write_method_serialized("_ON", 0);
if (reset_gpio)
- acpigen_soc_set_tx_gpio(reset_gpio);
+ acpigen_enable_tx_gpio(reset);
if (enable_gpio) {
- acpigen_soc_set_tx_gpio(enable_gpio);
+ acpigen_enable_tx_gpio(enable);
if (enable_delay_ms)
acpigen_write_sleep(enable_delay_ms);
}
if (reset_gpio) {
- acpigen_soc_clear_tx_gpio(reset_gpio);
+ acpigen_disable_tx_gpio(reset);
if (reset_delay_ms)
acpigen_write_sleep(reset_delay_ms);
}
@@ -528,9 +528,9 @@ void acpi_device_add_power_res(
/* Method (_OFF, 0, Serialized) */
acpigen_write_method_serialized("_OFF", 0);
if (reset_gpio)
- acpigen_soc_set_tx_gpio(reset_gpio);
+ acpigen_enable_tx_gpio(reset);
if (enable_gpio)
- acpigen_soc_clear_tx_gpio(enable_gpio);
+ acpigen_disable_tx_gpio(enable);
acpigen_pop_len(); /* _OFF method */
acpigen_pop_len(); /* PowerResource PRIC */
diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c
index 8ebdd09..d3ec05f 100644
--- a/src/arch/x86/acpigen.c
+++ b/src/arch/x86/acpigen.c
@@ -1299,3 +1299,26 @@ int __attribute__((weak)) acpigen_soc_clear_tx_gpio(unsigned int gpio_num)
acpigen_write_debug_string("clear_tx_gpio not available");
return -1;
}
+
+/*
+ * Helper functions for enabling/disabling Tx GPIOs based on the GPIO
+ * polarity. These functions end up calling acpigen_soc_{set,clear}_tx_gpio to
+ * make callbacks into SoC acpigen code.
+ *
+ * Returns 0 on success and -1 on error.
+ */
+int acpigen_enable_tx_gpio(struct acpi_gpio *gpio)
+{
+ if (gpio->polarity == ACPI_GPIO_ACTIVE_HIGH)
+ return acpigen_soc_set_tx_gpio(gpio->pins[0]);
+ else
+ return acpigen_soc_clear_tx_gpio(gpio->pins[0]);
+}
+
+int acpigen_disable_tx_gpio(struct acpi_gpio *gpio)
+{
+ if (gpio->polarity == ACPI_GPIO_ACTIVE_LOW)
+ return acpigen_soc_set_tx_gpio(gpio->pins[0]);
+ else
+ return acpigen_soc_clear_tx_gpio(gpio->pins[0]);
+}
diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h
index f76d85e..c1c4d59 100644
--- a/src/arch/x86/include/arch/acpigen.h
+++ b/src/arch/x86/include/arch/acpigen.h
@@ -21,6 +21,7 @@
#include <stdlib.h>
#include <stdint.h>
#include <arch/acpi.h>
+#include <arch/acpi_device.h>
/* Values that can be returned for ACPI Device _STA method */
#define ACPI_STATUS_DEVICE_PRESENT (1 << 0)
@@ -289,4 +290,14 @@ int acpigen_soc_set_tx_gpio(unsigned int gpio_num);
/* Generate ACPI AML code to set Tx value of GPIO to 0. */
int acpigen_soc_clear_tx_gpio(unsigned int gpio_num);
+/*
+ * Helper functions for enabling/disabling Tx GPIOs based on the GPIO
+ * polarity. These functions end up calling acpigen_soc_{set,clear}_tx_gpio to
+ * make callbacks into SoC acpigen code.
+ *
+ * Returns 0 on success and -1 on error.
+ */
+int acpigen_enable_tx_gpio(struct acpi_gpio *gpio);
+int acpigen_disable_tx_gpio(struct acpi_gpio *gpio);
+
#endif
Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18417
-gerrit
commit 6c726d68379054fb11093956a8f13d7f5e16b725
Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>
Date: Tue Feb 21 13:10:05 2017 +0100
commonlib/fsp.h: include sys/types.h for ssize_t
This file reportedly didn't compile on SUSE Linux with gcc 4.3.4:
[...]
> HOSTCC cbfstool/fsp_relocate.o
> In file included from /home/aladyshev/coreboot_2017/src/commonlib/fsp_relocate.c:18:
> /home/aladyshev/coreboot_2017/src/commonlib/include/commonlib/fsp.h:26: error: expected '=', ',', ';', 'asm' or '__attribute__' before 'fsp_component_relocate'
[...]
According to POSIX-2008[1], sys/types.h defines ssize_t, so include it.
This should not break coreboot code (as opposed to utils code), as we
have a sys/types.h in src/include.
[1]: http://pubs.opengroup.org/onlinepubs/9699919799/basedefs/sys_types.h.html
Change-Id: Id3694dc76c41d800ba09183e4b039b0719ac3d93
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>
---
src/commonlib/include/commonlib/fsp.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/commonlib/include/commonlib/fsp.h b/src/commonlib/include/commonlib/fsp.h
index 84e2c98..a2a2fae 100644
--- a/src/commonlib/include/commonlib/fsp.h
+++ b/src/commonlib/include/commonlib/fsp.h
@@ -18,6 +18,7 @@
#include <stddef.h>
#include <stdint.h>
+#include <sys/types.h>
/*
* Relocate FSP held within buffer defined by size to new_addr. Returns < 0