Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18443
-gerrit
commit 80b18b29cdcead65e28c341561756201b3092f14
Author: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Date: Tue Feb 14 17:18:45 2017 -0700
amd/gardenia: Add early_mainboard file
Add a file that can speed up the SPI interface to match the populated
SPI flash. The board uses an MX25U6435F.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com>
(cherry picked from commit cfda0166302d2c89aa09d95df84b97eb49b1f4fd)
Change-Id: Ibbad1391fb128249a58caa9358ecb5e0ca6382aa
Signed-off-by: Marc Jones <marcj303(a)gmail.com>
---
src/mainboard/amd/gardenia/Makefile.inc | 7 +++++++
src/mainboard/amd/gardenia/early_mainboard.c | 28 ++++++++++++++++++++++++++++
2 files changed, 35 insertions(+)
diff --git a/src/mainboard/amd/gardenia/Makefile.inc b/src/mainboard/amd/gardenia/Makefile.inc
index 72cd042..e501eb0 100644
--- a/src/mainboard/amd/gardenia/Makefile.inc
+++ b/src/mainboard/amd/gardenia/Makefile.inc
@@ -19,3 +19,10 @@ romstage-y += OemCustomize.c
ramstage-y += BiosCallOuts.c
ramstage-y += OemCustomize.c
ramstage-$(CONFIG_HUDSON_IMC_FWM) += fchec.c
+
+verstage-$(CONFIG_CHROMEOS) += chromeos.c
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+verstage-y += early_mainboard.c
+romstage-y += early_mainboard.c
diff --git a/src/mainboard/amd/gardenia/early_mainboard.c b/src/mainboard/amd/gardenia/early_mainboard.c
new file mode 100644
index 0000000..e89484b
--- /dev/null
+++ b/src/mainboard/amd/gardenia/early_mainboard.c
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/pi/car.h>
+#include <southbridge/amd/pi/hudson/hudson.h>
+
+void car_mainboard_pre_console_init(void)
+{
+ hudson_set_spi100(SPI_SPEED_33M,
+ SPI_SPEED_66M, SPI_SPEED_16M, SPI_SPEED_16M);
+ hudson_disable_4dw_burst();
+ hudson_read_mode(SPI_READ_MODE_QUAD114);
+}
Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18439
-gerrit
commit 9bb7b9928727e79e5a5671f8230cde9744dd545c
Author: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Date: Thu Feb 9 16:19:34 2017 -0700
amd/pi: Add verstage support
This patch takes hints from the work in commits 75c51d9 and 909c512.
Give PI-based systems the capability of running a SEPARATE_VERSTAGE.
This adds
* A verstage.c file to that initiates loading romstage (and verification)
* A new entry point in car.c that will be used when there is a separate
verstage
* Makefile flags and verstage-y additions for cpu and southbridge
* Besides AMD binary-PI changes, the x86 lapic timer is also now
included into verstage
This has been tested on Stoney (00670F000) and Gardenia. Although
additional APUs' makefiles are modified, none of those platforms are
assumed to support verstage at this time.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com>
(cherry picked from commit 15ce30cbd9d20aa0f5a5516e5f3bee7eab069852)
Change-Id: Ie43d87908c2d83b42b95b306419156e85993f7bd
Signed-off-by: Marc Jones <marcj303(a)gmail.com>
---
src/cpu/amd/pi/00630F01/Makefile.inc | 1 +
src/cpu/amd/pi/00660F01/Makefile.inc | 1 +
src/cpu/amd/pi/00670F00/Makefile.inc | 1 +
src/cpu/amd/pi/00730F01/Makefile.inc | 1 +
src/cpu/amd/pi/Makefile.inc | 4 ++++
src/cpu/amd/pi/car.c | 6 ++++++
src/cpu/amd/pi/car.h | 3 +++
src/cpu/amd/pi/romstage_after_verstage.S | 23 +++++++++++++++++++++++
src/cpu/amd/pi/verstage.c | 23 +++++++++++++++++++++++
src/cpu/x86/lapic/Makefile.inc | 1 +
src/southbridge/amd/pi/hudson/Makefile.inc | 3 +++
src/vendorcode/amd/pi/Makefile.inc | 2 ++
12 files changed, 69 insertions(+)
diff --git a/src/cpu/amd/pi/00630F01/Makefile.inc b/src/cpu/amd/pi/00630F01/Makefile.inc
index 98a7050..9dce0a8 100644
--- a/src/cpu/amd/pi/00630F01/Makefile.inc
+++ b/src/cpu/amd/pi/00630F01/Makefile.inc
@@ -13,6 +13,7 @@
# GNU General Public License for more details.
#
+verstage-y += fixme.c
romstage-y += fixme.c
ramstage-y += fixme.c
diff --git a/src/cpu/amd/pi/00660F01/Makefile.inc b/src/cpu/amd/pi/00660F01/Makefile.inc
index 6c6a2b8..acaf1f4 100644
--- a/src/cpu/amd/pi/00660F01/Makefile.inc
+++ b/src/cpu/amd/pi/00660F01/Makefile.inc
@@ -13,6 +13,7 @@
# GNU General Public License for more details.
#
+verstage-y += fixme.c
romstage-y += fixme.c
ramstage-y += fixme.c
ramstage-y += chip_name.c
diff --git a/src/cpu/amd/pi/00670F00/Makefile.inc b/src/cpu/amd/pi/00670F00/Makefile.inc
index 6c6a2b8..acaf1f4 100644
--- a/src/cpu/amd/pi/00670F00/Makefile.inc
+++ b/src/cpu/amd/pi/00670F00/Makefile.inc
@@ -13,6 +13,7 @@
# GNU General Public License for more details.
#
+verstage-y += fixme.c
romstage-y += fixme.c
ramstage-y += fixme.c
ramstage-y += chip_name.c
diff --git a/src/cpu/amd/pi/00730F01/Makefile.inc b/src/cpu/amd/pi/00730F01/Makefile.inc
index 9367b45..57cabb3 100644
--- a/src/cpu/amd/pi/00730F01/Makefile.inc
+++ b/src/cpu/amd/pi/00730F01/Makefile.inc
@@ -13,6 +13,7 @@
# GNU General Public License for more details.
#
+verstage-y += fixme.c
romstage-y += fixme.c
ramstage-y += fixme.c
diff --git a/src/cpu/amd/pi/Makefile.inc b/src/cpu/amd/pi/Makefile.inc
index ce60833..972c11d 100644
--- a/src/cpu/amd/pi/Makefile.inc
+++ b/src/cpu/amd/pi/Makefile.inc
@@ -18,7 +18,11 @@ subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01
subdirs-$(CONFIG_CPU_AMD_PI_00670F00) += 00670F00
subdirs-$(CONFIG_CPU_AMD_PI_00660F01) += 00660F01
+verstage-y += verstage.c
+verstage-y += car.c
+
romstage-y += car.c
+romstage-$(CONFIG_SEPARATE_VERSTAGE) += romstage_after_verstage.S
romstage-y += s3_resume.c
ramstage-y += s3_resume.c
diff --git a/src/cpu/amd/pi/car.c b/src/cpu/amd/pi/car.c
index 62c5338..f66f94f 100644
--- a/src/cpu/amd/pi/car.c
+++ b/src/cpu/amd/pi/car.c
@@ -66,6 +66,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
cache_as_ram_stage_main();
}
+void romstage_after_verstage(void)
+{
+ /* This does not return. */
+ cache_as_ram_stage_main();
+}
+
unsigned long __attribute__((weak)) car_bist_mask_bist(unsigned long bist)
{
return bist;
diff --git a/src/cpu/amd/pi/car.h b/src/cpu/amd/pi/car.h
index 98da75d..fdf1420 100644
--- a/src/cpu/amd/pi/car.h
+++ b/src/cpu/amd/pi/car.h
@@ -17,6 +17,9 @@
#ifndef PI_SPLIT_CAR_H
#define PI_SPLIT_CAR_H
+/* Entry points from the cache-as-ram assembly code */
+void romstage_after_verstage(void);
+
/* Early initialization immediately after CAR setup */
void cache_as_ram_stage_main(void);
diff --git a/src/cpu/amd/pi/romstage_after_verstage.S b/src/cpu/amd/pi/romstage_after_verstage.S
new file mode 100644
index 0000000..ce17ebd
--- /dev/null
+++ b/src/cpu/amd/pi/romstage_after_verstage.S
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "gcccar.inc"
+
+.text
+.global car_stage_entry, disable_cache_as_ram
+car_stage_entry:
+ call romstage_after_verstage
+
+ #include "after_raminit.S"
diff --git a/src/cpu/amd/pi/verstage.c b/src/cpu/amd/pi/verstage.c
new file mode 100644
index 0000000..c8551dd
--- /dev/null
+++ b/src/cpu/amd/pi/verstage.c
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/amd/pi/car.h>
+#include <program_loading.h>
+
+void cache_as_ram_stage_main(void)
+{
+ run_romstage();
+ /* Will not return to here. */
+}
diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc
index 9df2c5f..58f67b2 100644
--- a/src/cpu/x86/lapic/Makefile.inc
+++ b/src/cpu/x86/lapic/Makefile.inc
@@ -1,6 +1,7 @@
ramstage-y += lapic.c
ramstage-y += lapic_cpu_init.c
ramstage-y += secondary.S
+verstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
bootblock-y += boot_cpu.c
diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc
index 2153c62..4bd599b 100644
--- a/src/southbridge/amd/pi/hudson/Makefile.inc
+++ b/src/southbridge/amd/pi/hudson/Makefile.inc
@@ -42,8 +42,10 @@ ramstage-y += sd.c
ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c
ramstage-y += reset.c
+verstage-y += reset.c
romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c
ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c
+verstage-y += early_setup.c
romstage-y += early_setup.c
ifeq ($(CONFIG_HUDSON_IMC_FWM), y)
romstage-y += imc.c
@@ -51,6 +53,7 @@ ramstage-y += imc.c
endif
ifeq ($(CONFIG_HUDSON_UART), y)
+verstage-y += uart.c
romstage-y += uart.c
ramstage-y += uart.c
endif
diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc
index 2cd18c1..b782540 100644
--- a/src/vendorcode/amd/pi/Makefile.inc
+++ b/src/vendorcode/amd/pi/Makefile.inc
@@ -77,6 +77,7 @@ export AGESA_INC := $(AGESA_INC)
export AGESA_CFLAGS := $(AGESA_CFLAGS)
CC_bootblock := $(CC_bootblock) $(AGESA_INC) $(AGESA_CFLAGS)
+CC_verstage := $(CC_verstage) $(AGESA_INC) $(AGESA_CFLAGS)
CC_romstage := $(CC_romstage) $(AGESA_INC) $(AGESA_CFLAGS)
CC_ramstage := $(CC_ramstage) $(AGESA_INC) $(AGESA_CFLAGS)
CC_x86_32 := $(CC_x86_32) $(AGESA_INC) $(AGESA_CFLAGS)
@@ -139,6 +140,7 @@ $(obj)/agesa/libagesa.a: $(call src-to-obj,libagesa,$(agesa_src_files))
@printf " AGESA $(subst $(obj)/,,$(@))\n"
ar rcs $@ $+
+verstage-libs += $(obj)/agesa/libagesa.a
romstage-libs += $(obj)/agesa/libagesa.a
ramstage-libs += $(obj)/agesa/libagesa.a
Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18438
-gerrit
commit 4530b1b2c1def8206a0f16ce3f11871de9a730f7
Author: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Date: Wed Jan 25 15:23:47 2017 -0700
cpu/amd/pi: Change wrapper to use config option
Add a check for vboot when locating the binaryPI image.
There is currently an ordering problem using cbmem to locate the
image when vboot is present. Vboot inserts its locator into the
search process so that memory can be checked before flash is queried.
For the earliest calls using the wrapper, DRAM has not been set up
and cbmem not initialized in romstage. This change prevents an
endless loop when vboot searches cbmem.
This change has another side effect. When vboot is in effect, the
change forces the RO binaryPI to be used even when on either of the
RW paths. There is currently no ability to relocate the XIP image
for use in a RW region.
Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Reviewed-by: Marc Jones <marcj303(a)gmail.com>
(cherry picked from commit 6efe9217c38cf93fd9b38e52cf3ec90fee3d0474)
Change-Id: I0c14bd729f8a67bca37cbdbd3a5e266c99c86d54
Signed-off-by: Marc Jones <marcj303(a)gmail.com>
---
src/northbridge/amd/pi/agesawrapper.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c
index 0fe8eab..543aa80 100644
--- a/src/northbridge/amd/pi/agesawrapper.c
+++ b/src/northbridge/amd/pi/agesawrapper.c
@@ -603,8 +603,14 @@ const void *agesawrapper_locate_module (const CHAR8 name[8])
const AMD_MODULE_HEADER* module;
size_t file_size;
+#if IS_ENABLED(CONFIG_VBOOT)
+ /* Use phys. location in flash and prevent vboot from searching cbmem */
+ agesa = (void *)CONFIG_AGESA_BINARY_PI_LOCATION;
+ file_size = 0x100000;
+#else
agesa = cbfs_boot_map_with_leak((const char *)CONFIG_CBFS_AGESA_NAME,
CBFS_TYPE_RAW, &file_size);
+#endif
if (!agesa)
return NULL;
image = LibAmdLocateImage(agesa, agesa + file_size - 1, 4096, name);
Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18437
-gerrit
commit 14d33f8b646713d9ed3356ee4a82202e74450c01
Author: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Date: Tue Jan 17 11:57:31 2017 -0500
cpu/amd/pi: Split CAR setup for use in multiple stages
This patch uses hints from commit e6af4be to make CAR setup more
standalone. These changes will facilitate establishing CAR outside
of romstage in an upcoming separate verstage patch.
Move CAR teardown to its own file that will always be in romstage, but
isn't required in an earlier stage.
Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Reviewed-by: Marc Jones <marcj303(a)gmail.com>
(cherry picked from commit c648d2a0f88ac1161f5d2002f7b947cb8e56b03f)
Change-Id: I9fe53ca1fd6b1edd4d5e072849f3962c8bc95df0
Signed-off-by: Marc Jones <marcj303(a)gmail.com>
---
src/cpu/amd/pi/after_raminit.S | 48 +++++++++++++++++++++++++++++++++++++++++
src/cpu/amd/pi/cache_as_ram.inc | 31 ++++----------------------
2 files changed, 52 insertions(+), 27 deletions(-)
diff --git a/src/cpu/amd/pi/after_raminit.S b/src/cpu/amd/pi/after_raminit.S
new file mode 100644
index 0000000..354b22b
--- /dev/null
+++ b/src/cpu/amd/pi/after_raminit.S
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/x86/cache.h>
+
+/*
+ * This is the common entry point after DRAM has been initialized.
+ */
+disable_cache_as_ram:
+ /* Save return stack */
+ movd 0(%esp), %xmm1
+ movd %esp, %xmm0
+
+ /* Disable cache */
+ movl %cr0, %eax
+ orl $CR0_CacheDisable, %eax
+ movl %eax, %cr0
+
+ AMD_DISABLE_STACK
+
+ /* enable cache */
+ movl %cr0, %eax
+ andl $0x9fffffff, %eax
+ movl %eax, %cr0
+ xorl %eax, %eax
+
+ /* Restore the return stack */
+ wbinvd
+ movd %xmm0, %esp
+ movd %xmm1, (%esp)
+ ret
+
+cache_as_ram_setup_out:
+#ifdef __x86_64__
+.code64
+#endif
diff --git a/src/cpu/amd/pi/cache_as_ram.inc b/src/cpu/amd/pi/cache_as_ram.inc
index 24db600..b056110 100644
--- a/src/cpu/amd/pi/cache_as_ram.inc
+++ b/src/cpu/amd/pi/cache_as_ram.inc
@@ -136,31 +136,8 @@ cache_as_ram_setup:
stop:
jmp stop
-disable_cache_as_ram:
- /* Save return stack */
- movd 0(%esp), %xmm1
- movd %esp, %xmm0
-
- /* Disable cache */
- movl %cr0, %eax
- orl $CR0_CacheDisable, %eax
- movl %eax, %cr0
-
- AMD_DISABLE_STACK
-
- /* enable cache */
- movl %cr0, %eax
- andl $0x9fffffff, %eax
- movl %eax, %cr0
- xorl %eax, %eax
-
- /* Restore the return stack */
- wbinvd
- movd %xmm0, %esp
- movd %xmm1, (%esp)
- ret
-
-cache_as_ram_setup_out:
-#ifdef __x86_64__
-.code64
+/* One will never return from cache_as_ram_main() in verstage so there's
+ * no such thing as after RAM init. */
+#if !ENV_VERSTAGE
+#include "after_raminit.S"
#endif
Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18435
-gerrit
commit ad2274456b992a514430389fef887ae3fecba809
Author: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Date: Sat Jan 7 18:17:32 2017 -0500
amd/pi/hudson: Add alternate method for including amdfw
For systems using Chrome OS, place the amdfw outside of cbfs control.
The firmware must go to a fixed position at an offset of 0x20000 into
the flash device.
Potentially improve by adding a warning or error message for the
condition when sizeof(amdfw) + sizeof(cbfs and metadata) > sizeof(flash).
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com>
(cherry picked from commit 2d9d631b39d7850576438a5b0979936bd33893e1)
Change-Id: I38029bc03e5db260424cca293b1a7bceea4d0d75
Signed-off-by: Marc Jones <marcj303(a)gmail.com>
---
src/southbridge/amd/pi/hudson/Kconfig | 7 +++++++
src/southbridge/amd/pi/hudson/Makefile.inc | 13 +++++++++++++
2 files changed, 20 insertions(+)
diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig
index f6e3355..0afeeec 100644
--- a/src/southbridge/amd/pi/hudson/Kconfig
+++ b/src/southbridge/amd/pi/hudson/Kconfig
@@ -220,3 +220,10 @@ config HUDSON_UART
controller 0 registers range from FEDC_6000h
to FEDC_6FFFh. UART controller 1 registers
range from FEDC_8000h to FEDC_8FFFh.
+
+config AMDFW_OUTSIDE_CBFS
+ def_bool n
+ help
+ The AMDFW (PSP) is typically locatable in cbfs. Select this
+ option to manually attach the generated amdfw.rom at an
+ offset of 0x20000 from the bottom of the coreboot ROM image.
diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc
index 24a757c..2153c62 100644
--- a/src/southbridge/amd/pi/hudson/Makefile.inc
+++ b/src/southbridge/amd/pi/hudson/Makefile.inc
@@ -264,7 +264,20 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \
--flashsize $(CONFIG_ROM_SIZE) \
--output $@
+ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y)
+PHONY+=add_amdfw
+INTERMEDIATE+=add_amdfw
+
+add_amdfw: $(obj)/coreboot.pre $(obj)/amdfw.rom
+ printf " DD Adding AMD Firmware\n"
+ dd if=$(obj)/amdfw.rom \
+ of=$(obj)/coreboot.pre conv=notrunc bs=1 seek=131072 >/dev/null 2>&1
+
+else # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y)
+
cbfs-files-y += apu/amdfw
apu/amdfw-file := $(obj)/amdfw.rom
apu/amdfw-position := $(HUDSON_FWM_POSITION)
apu/amdfw-type := raw
+
+endif # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y)
Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18434
-gerrit
commit 7a1ffddd83b144275e4bafba5e6f5b066322b550
Author: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Date: Thu Feb 9 09:15:05 2017 -0700
amd/pi/mainboards: Consolidate early duplicated code
Make a common entry function for cache_as_ram_main for use with the
PI-based mainboards. The new function drives the typical setup, BIST
checking, product reporting, and other common functions. This work
takes hints from commit e6af4be.
Add a new car.c file that contains the early steps. This has
weak functions to hook for southbridge and mainboard setup. Some
APUs also get BIST bits masked off.
This patch is intended to prepare for an upcoming change that will
split the CAR setup from the teardown, so that CAR setup may be used
in verstage.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com>
(cherry picked from commit 9d1d92826216dee35f80ec40d722a3e8a587e996)
Change-Id: Id10580ecc439df10df26ca99881772f328e7bdd0
Signed-off-by: Marc Jones <marcj303(a)gmail.com>
---
src/cpu/amd/pi/00660F01/fixme.c | 7 ++
src/cpu/amd/pi/00670F00/fixme.c | 7 ++
src/cpu/amd/pi/Makefile.inc | 2 +
src/cpu/amd/pi/car.c | 88 +++++++++++++++++++++++
src/cpu/amd/pi/car.h | 30 ++++++++
src/mainboard/amd/bettong/romstage.c | 30 +-------
src/mainboard/amd/db-ft3b-lc/Makefile.inc | 1 +
src/mainboard/amd/db-ft3b-lc/early_mainboard.c | 31 ++++++++
src/mainboard/amd/db-ft3b-lc/romstage.c | 39 +---------
src/mainboard/amd/gardenia/romstage.c | 29 +-------
src/mainboard/amd/lamar/Makefile.inc | 2 +
src/mainboard/amd/lamar/early_mainboard.c | 44 ++++++++++++
src/mainboard/amd/lamar/romstage.c | 48 +------------
src/mainboard/amd/olivehillplus/Makefile.inc | 1 +
src/mainboard/amd/olivehillplus/early_mainboard.c | 44 ++++++++++++
src/mainboard/amd/olivehillplus/romstage.c | 47 +-----------
src/mainboard/bap/ode_e21XX/Makefile.inc | 1 +
src/mainboard/bap/ode_e21XX/early_mainboard.c | 37 ++++++++++
src/mainboard/bap/ode_e21XX/romstage.c | 43 +----------
src/mainboard/pcengines/apu2/Makefile.inc | 1 +
src/mainboard/pcengines/apu2/early_mainboard.c | 67 +++++++++++++++++
src/mainboard/pcengines/apu2/romstage.c | 74 +------------------
src/southbridge/amd/pi/hudson/early_setup.c | 11 +++
23 files changed, 388 insertions(+), 296 deletions(-)
diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c
index 6770287..973b0a7 100644
--- a/src/cpu/amd/pi/00660F01/fixme.c
+++ b/src/cpu/amd/pi/00660F01/fixme.c
@@ -16,6 +16,7 @@
#include <cpu/x86/mtrr.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include "amdlib.h"
+#include <cpu/amd/pi/car.h>
void amd_initcpuio(void)
{
@@ -85,3 +86,9 @@ void amd_initmmio(void)
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
}
+
+unsigned long car_bist_mask_bist(unsigned long bist)
+{
+ /* Mask bit 31. One result of Silicon Observation */
+ return bist & 0x7FFFFFFF;
+}
diff --git a/src/cpu/amd/pi/00670F00/fixme.c b/src/cpu/amd/pi/00670F00/fixme.c
index 86f5acf..5e9ac79 100644
--- a/src/cpu/amd/pi/00670F00/fixme.c
+++ b/src/cpu/amd/pi/00670F00/fixme.c
@@ -16,6 +16,7 @@
#include <cpu/x86/mtrr.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include "amdlib.h"
+#include <cpu/amd/pi/car.h>
void amd_initcpuio(void)
{
@@ -89,3 +90,9 @@ void amd_initmmio(void)
0x800ull;
LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);
}
+
+unsigned long car_bist_mask_bist(unsigned long bist)
+{
+ /* Mask bit 31. One result of Silicon Observation */
+ return bist & 0x7FFFFFFF;
+}
diff --git a/src/cpu/amd/pi/Makefile.inc b/src/cpu/amd/pi/Makefile.inc
index 0e31d9f..ce60833 100644
--- a/src/cpu/amd/pi/Makefile.inc
+++ b/src/cpu/amd/pi/Makefile.inc
@@ -18,6 +18,8 @@ subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01
subdirs-$(CONFIG_CPU_AMD_PI_00670F00) += 00670F00
subdirs-$(CONFIG_CPU_AMD_PI_00660F01) += 00660F01
+romstage-y += car.c
+
romstage-y += s3_resume.c
ramstage-y += s3_resume.c
ramstage-$(CONFIG_SPI_FLASH) += spi.c
diff --git a/src/cpu/amd/pi/car.c b/src/cpu/amd/pi/car.c
new file mode 100644
index 0000000..62c5338
--- /dev/null
+++ b/src/cpu/amd/pi/car.c
@@ -0,0 +1,88 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/early_variables.h>
+#include <console/console.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/x86/bist.h>
+#include <cpu/amd/car.h>
+#include <cpu/amd/pi/car.h>
+#include <northbridge/amd/pi/agesawrapper.h>
+#include <timestamp.h>
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+ u32 val;
+
+#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS)
+ /* Initialize timestamp book keeping only once. */
+ timestamp_init(timestamp_get());
+#endif
+
+ post_code(0x30);
+
+ /* Must come first to enable PCI MMCONF. */
+ amd_initmmio();
+
+ if (!cpu_init_detectedx && boot_cpu()){
+ /* Call into pre-console init code then initialize console. */
+ post_code(0x31);
+ car_sb_pre_console_init();
+
+ post_code(0x32);
+ car_mainboard_pre_console_init();
+
+ post_code(0x33);
+ console_init();
+ }
+
+ /* Halt if there was a built in self test failure */
+ post_code(0x34);
+ report_bist_failure(car_bist_mask_bist(bist));
+
+ /* Load MPB */
+ val = cpuid_eax(1);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
+
+ post_code(0x35);
+ car_sb_post_console_init();
+ post_code(0x36);
+ car_mainboard_post_console_init();
+
+ cache_as_ram_stage_main();
+}
+
+unsigned long __attribute__((weak)) car_bist_mask_bist(unsigned long bist)
+{
+ return bist;
+}
+
+void __attribute__((weak)) car_mainboard_pre_console_init(void)
+{
+}
+
+void __attribute__((weak)) car_sb_pre_console_init(void)
+{
+}
+
+void __attribute__((weak)) car_mainboard_post_console_init(void)
+{
+}
+
+void __attribute__((weak)) car_sb_post_console_init(void)
+{
+}
diff --git a/src/cpu/amd/pi/car.h b/src/cpu/amd/pi/car.h
new file mode 100644
index 0000000..98da75d
--- /dev/null
+++ b/src/cpu/amd/pi/car.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef PI_SPLIT_CAR_H
+#define PI_SPLIT_CAR_H
+
+/* Early initialization immediately after CAR setup */
+void cache_as_ram_stage_main(void);
+
+unsigned long car_bist_mask_bist(unsigned long bist);
+void car_mainboard_pre_console_init(void);
+void car_sb_pre_console_init(void);
+
+void car_mainboard_post_console_init(void);
+void car_sb_post_console_init(void);
+
+#endif
diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c
index 6b12afc..c881337 100644
--- a/src/mainboard/amd/bettong/romstage.c
+++ b/src/mainboard/amd/bettong/romstage.c
@@ -17,45 +17,19 @@
#include <arch/acpi.h>
#include <arch/io.h>
#include <arch/stages.h>
-#include <cpu/x86/lapic.h>
-#include <cpu/x86/bist.h>
#include <cpu/amd/car.h>
+#include <cpu/amd/pi/car.h>
#include <cpu/amd/pi/s3_resume.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
#include <southbridge/amd/pi/hudson/hudson.h>
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void cache_as_ram_stage_main(void)
{
- u32 val;
#if CONFIG_HAVE_ACPI_RESUME
void *resume_backup_memory;
#endif
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
-
- hudson_lpc_port80();
-
- if (!cpu_init_detectedx && boot_cpu()) {
- post_code(0x30);
-
-#if IS_ENABLED(CONFIG_HUDSON_UART)
- configure_hudson_uart();
-#endif
- post_code(0x31);
- console_init();
- }
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist & 0x7FFFFFFF); /* Mask bit 31. One result of Silicon Observation */
-
- /* Load MPB */
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
post_code(0x37);
AGESAWRAPPER(amdinitreset);
post_code(0x38);
diff --git a/src/mainboard/amd/db-ft3b-lc/Makefile.inc b/src/mainboard/amd/db-ft3b-lc/Makefile.inc
index 97c761f..01d99ac 100644
--- a/src/mainboard/amd/db-ft3b-lc/Makefile.inc
+++ b/src/mainboard/amd/db-ft3b-lc/Makefile.inc
@@ -15,6 +15,7 @@
romstage-y += BiosCallOuts.c
romstage-y += OemCustomize.c
+romstage-y += early_mainboard.c
ramstage-y += BiosCallOuts.c
ramstage-y += OemCustomize.c
diff --git a/src/mainboard/amd/db-ft3b-lc/early_mainboard.c b/src/mainboard/amd/db-ft3b-lc/early_mainboard.c
new file mode 100644
index 0000000..7d471eb
--- /dev/null
+++ b/src/mainboard/amd/db-ft3b-lc/early_mainboard.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <cpu/amd/pi/car.h>
+
+void car_mainboard_pre_console_init(void)
+{
+ /*
+ * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
+ * LpcClk[1:0]". This following register setting has been
+ * replicated in every reference design since Parmer, so it is
+ * believed to be required even though it is not documented in
+ * the SoC BKDGs. Without this setting, there is no serial
+ * output.
+ */
+ outb(0xD2, 0xcd6);
+ outb(0x00, 0xcd7);
+}
diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c
index 79cc0f9..e67f1fb 100644
--- a/src/mainboard/amd/db-ft3b-lc/romstage.c
+++ b/src/mainboard/amd/db-ft3b-lc/romstage.c
@@ -26,49 +26,14 @@
#include <console/console.h>
#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
+#include <cpu/amd/pi/car.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
-#include <cpu/x86/bist.h>
-#include <cpu/x86/lapic.h>
#include <southbridge/amd/pi/hudson/hudson.h>
#include <cpu/amd/pi/s3_resume.h>
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void cache_as_ram_stage_main(void)
{
- u32 val;
-
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
-
- /*
- * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
- * LpcClk[1:0]". This following register setting has been
- * replicated in every reference design since Parmer, so it is
- * believed to be required even though it is not documented in
- * the SoC BKDGs. Without this setting, there is no serial
- * output.
- */
- outb(0xD2, 0xcd6);
- outb(0x00, 0xcd7);
-
- hudson_lpc_port80();
-
- if (!cpu_init_detectedx && boot_cpu()) {
- post_code(0x30);
-
- post_code(0x31);
- console_init();
- }
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist);
-
- /* Load MPB */
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
post_code(0x37);
AGESAWRAPPER(amdinitreset);
diff --git a/src/mainboard/amd/gardenia/romstage.c b/src/mainboard/amd/gardenia/romstage.c
index 58ddc30..9fa2d56 100644
--- a/src/mainboard/amd/gardenia/romstage.c
+++ b/src/mainboard/amd/gardenia/romstage.c
@@ -18,44 +18,19 @@
#include <arch/acpi.h>
#include <arch/io.h>
#include <arch/stages.h>
-#include <cpu/x86/lapic.h>
-#include <cpu/x86/bist.h>
#include <cpu/amd/car.h>
+#include <cpu/amd/pi/car.h>
#include <cpu/amd/pi/s3_resume.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
#include <southbridge/amd/pi/hudson/hudson.h>
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void cache_as_ram_stage_main(void)
{
- u32 val;
#if CONFIG_HAVE_ACPI_RESUME
void *resume_backup_memory;
#endif
- amd_initmmio();
- hudson_lpc_port80();
- hudson_lpc_decode();
-
- if (!cpu_init_detectedx && boot_cpu()) {
- post_code(0x30);
-
-#if IS_ENABLED(CONFIG_HUDSON_UART)
- configure_hudson_uart();
-#endif
- post_code(0x31);
- console_init();
- }
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist & 0x7FFFFFFF); /* Mask bit 31. One result of Silicon Observation */
-
- /* Load MPB */
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
post_code(0x37);
AGESAWRAPPER(amdinitreset);
post_code(0x38);
diff --git a/src/mainboard/amd/lamar/Makefile.inc b/src/mainboard/amd/lamar/Makefile.inc
index 37c1dce..794c6dc 100644
--- a/src/mainboard/amd/lamar/Makefile.inc
+++ b/src/mainboard/amd/lamar/Makefile.inc
@@ -13,6 +13,8 @@
# GNU General Public License for more details.
#
+romstage-y += early_mainboard.c
+
romstage-y += BiosCallOuts.c
romstage-y += OemCustomize.c
diff --git a/src/mainboard/amd/lamar/early_mainboard.c b/src/mainboard/amd/lamar/early_mainboard.c
new file mode 100644
index 0000000..65aace1
--- /dev/null
+++ b/src/mainboard/amd/lamar/early_mainboard.c
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 - 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <cpu/amd/pi/car.h>
+#include <southbridge/amd/common/amd_defs.h>
+#include <southbridge/amd/pi/hudson/hudson.h>
+#include "superio/fintek/f81216h/f81216h.h"
+
+#define SERIAL_DEV PNP_DEV(0x4e, F81216H_SP1)
+
+
+void car_mainboard_pre_console_init(void)
+{
+ /*
+ * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
+ * LpcClk[1:0]". This following register setting has been
+ * replicated in every reference design since Parmer, so it is
+ * believed to be required even though it is not documented in
+ * the SoC BKDGs. Without this setting, there is no serial
+ * output.
+ */
+ outb(0xD2, 0xcd6);
+ outb(0x00, 0xcd7);
+
+ outb(0x24, 0xCD6);
+ outb(0x01, 0xCD7);
+ *(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x28) |= 1 << 18; /* 24Mhz */
+ *(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x40) &= ~(1 << 2); /* 24Mhz */
+
+ f81216h_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE, MODE_7777);
+}
diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c
index bda8c0f..9204e90 100644
--- a/src/mainboard/amd/lamar/romstage.c
+++ b/src/mainboard/amd/lamar/romstage.c
@@ -21,11 +21,11 @@
#include <arch/io.h>
#include <arch/stages.h>
#include <device/pnp_def.h>
-#include <arch/cpu.h>
#include <cpu/x86/lapic.h>
#include <console/console.h>
#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
+#include <cpu/amd/pi/car.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
#include <cpu/x86/bist.h>
@@ -34,53 +34,9 @@
#include <southbridge/amd/pi/hudson/hudson.h>
#include <cpu/amd/pi/s3_resume.h>
#include "cbmem.h"
-#include "superio/fintek/f81216h/f81216h.h"
-#define SERIAL_DEV PNP_DEV(0x4e, F81216H_SP1)
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void cache_as_ram_stage_main(void)
{
- u32 val;
-
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
-
- /*
- * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
- * LpcClk[1:0]". This following register setting has been
- * replicated in every reference design since Parmer, so it is
- * believed to be required even though it is not documented in
- * the SoC BKDGs. Without this setting, there is no serial
- * output.
- */
- outb(0xD2, 0xcd6);
- outb(0x00, 0xcd7);
-
- hudson_lpc_decode();
-
- outb(0x24, 0xCD6);
- outb(0x01, 0xCD7);
- *(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x28) |= 1 << 18; /* 24Mhz */
- *(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x40) &= ~(1 << 2); /* 24Mhz */
-
- hudson_lpc_port80();
-
- if (!cpu_init_detectedx) {
- post_code(0x30);
- f81216h_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE, MODE_7777);
- post_code(0x31);
- console_init();
- }
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist);
-
- /* Load MPB */
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
post_code(0x37);
AGESAWRAPPER(amdinitreset);
post_code(0x38);
diff --git a/src/mainboard/amd/olivehillplus/Makefile.inc b/src/mainboard/amd/olivehillplus/Makefile.inc
index 37c1dce..c1ac631 100644
--- a/src/mainboard/amd/olivehillplus/Makefile.inc
+++ b/src/mainboard/amd/olivehillplus/Makefile.inc
@@ -15,6 +15,7 @@
romstage-y += BiosCallOuts.c
romstage-y += OemCustomize.c
+romstage-y += early_mainboard.c
ramstage-y += BiosCallOuts.c
ramstage-y += OemCustomize.c
diff --git a/src/mainboard/amd/olivehillplus/early_mainboard.c b/src/mainboard/amd/olivehillplus/early_mainboard.c
new file mode 100644
index 0000000..d394c9a
--- /dev/null
+++ b/src/mainboard/amd/olivehillplus/early_mainboard.c
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 - 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <cpu/amd/pi/car.h>
+
+void car_mainboard_pre_console_init(void)
+{
+ /*
+ * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
+ * LpcClk[1:0]". This following register setting has been
+ * replicated in every reference design since Parmer, so it is
+ * believed to be required even though it is not documented in
+ * the SoC BKDGs. Without this setting, there is no serial
+ * output.
+ */
+ outb(0xD2, 0xcd6);
+ outb(0x00, 0xcd7);
+}
+
+void car_mainboard_post_console_init(void)
+{
+ /*
+ * This refers to LpcClkDrvSth settling time. Without this setting, processor
+ * initialization is slow or incorrect, so this wait has been replicated from
+ * earlier development boards.
+ */
+ {
+ int i;
+ for(i = 0; i < 200000; i++) inb(0xCD6);
+ }
+}
diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c
index 534a8e5..02fa3d1 100644
--- a/src/mainboard/amd/olivehillplus/romstage.c
+++ b/src/mainboard/amd/olivehillplus/romstage.c
@@ -26,6 +26,7 @@
#include <console/console.h>
#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
+#include <cpu/amd/pi/car.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
#include <cpu/x86/bist.h>
@@ -33,52 +34,8 @@
#include <southbridge/amd/pi/hudson/hudson.h>
#include <cpu/amd/pi/s3_resume.h>
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void cache_as_ram_stage_main(void)
{
- u32 val;
-
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
-
- /*
- * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
- * LpcClk[1:0]". This following register setting has been
- * replicated in every reference design since Parmer, so it is
- * believed to be required even though it is not documented in
- * the SoC BKDGs. Without this setting, there is no serial
- * output.
- */
- outb(0xD2, 0xcd6);
- outb(0x00, 0xcd7);
-
- hudson_lpc_port80();
-
- if (!cpu_init_detectedx && boot_cpu()) {
- post_code(0x30);
-
- post_code(0x31);
- console_init();
- }
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist);
-
- /* Load MPB */
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
- /*
- * This refers to LpcClkDrvSth settling time. Without this setting, processor
- * initialization is slow or incorrect, so this wait has been replicated from
- * earlier development boards.
- */
- {
- int i;
- for(i = 0; i < 200000; i++) inb(0xCD6);
- }
-
post_code(0x37);
AGESAWRAPPER(amdinitreset);
diff --git a/src/mainboard/bap/ode_e21XX/Makefile.inc b/src/mainboard/bap/ode_e21XX/Makefile.inc
index b0ce627..f6a27ad 100644
--- a/src/mainboard/bap/ode_e21XX/Makefile.inc
+++ b/src/mainboard/bap/ode_e21XX/Makefile.inc
@@ -15,6 +15,7 @@
romstage-y += BiosCallOuts.c
romstage-y += OemCustomize.c
+romstage-y += early_mainboard.c
ramstage-y += BiosCallOuts.c
ramstage-y += OemCustomize.c
diff --git a/src/mainboard/bap/ode_e21XX/early_mainboard.c b/src/mainboard/bap/ode_e21XX/early_mainboard.c
new file mode 100644
index 0000000..b7ffbbb
--- /dev/null
+++ b/src/mainboard/bap/ode_e21XX/early_mainboard.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <cpu/amd/pi/car.h>
+#include <superio/fintek/common/fintek.h>
+#include <superio/fintek/f81866d/f81866d.h>
+
+#define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1)
+
+void car_mainboard_pre_console_init(void)
+{
+ /*
+ * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
+ * LpcClk[1:0]". This following register setting has been
+ * replicated in every reference design since Parmer, so it is
+ * believed to be required even though it is not documented in
+ * the SoC BKDGs. Without this setting, there is no serial
+ * output.
+ */
+ outb(0xD2, 0xcd6);
+ outb(0x00, 0xcd7);
+
+ fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE);
+}
diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c
index 5deeaa8..b82b13f 100644
--- a/src/mainboard/bap/ode_e21XX/romstage.c
+++ b/src/mainboard/bap/ode_e21XX/romstage.c
@@ -26,53 +26,14 @@
#include <console/console.h>
#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
+#include <cpu/amd/pi/car.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
-#include <cpu/x86/bist.h>
-#include <cpu/x86/lapic.h>
#include <southbridge/amd/pi/hudson/hudson.h>
#include <cpu/amd/pi/s3_resume.h>
-#include <superio/fintek/common/fintek.h>
-#include <superio/fintek/f81866d/f81866d.h>
-
-#define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1)
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void cache_as_ram_stage_main(void)
{
- u32 val;
-
- /* Must come first to enable PCI MMCONF. */
- amd_initmmio();
-
- /*
- * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
- * LpcClk[1:0]". This following register setting has been
- * replicated in every reference design since Parmer, so it is
- * believed to be required even though it is not documented in
- * the SoC BKDGs. Without this setting, there is no serial
- * output.
- */
- outb(0xD2, 0xcd6);
- outb(0x00, 0xcd7);
-
- hudson_lpc_port80();
-
- if (!cpu_init_detectedx && boot_cpu()) {
- post_code(0x30);
- fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE);
- post_code(0x31);
- console_init();
- }
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist);
-
- /* Load MPB */
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
-
post_code(0x37);
AGESAWRAPPER(amdinitreset);
diff --git a/src/mainboard/pcengines/apu2/Makefile.inc b/src/mainboard/pcengines/apu2/Makefile.inc
index 77c6d78..2936f36 100644
--- a/src/mainboard/pcengines/apu2/Makefile.inc
+++ b/src/mainboard/pcengines/apu2/Makefile.inc
@@ -16,6 +16,7 @@
romstage-y += BiosCallOuts.c
romstage-y += OemCustomize.c
romstage-y += gpio_ftns.c
+romstage-y += early_mainboard.c
ramstage-y += BiosCallOuts.c
ramstage-y += OemCustomize.c
diff --git a/src/mainboard/pcengines/apu2/early_mainboard.c b/src/mainboard/pcengines/apu2/early_mainboard.c
new file mode 100644
index 0000000..9bd4ba3
--- /dev/null
+++ b/src/mainboard/pcengines/apu2/early_mainboard.c
@@ -0,0 +1,67 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 - 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <cpu/amd/pi/car.h>
+#include <southbridge/amd/pi/hudson/hudson.h>
+#include <northbridge/amd/pi/agesawrapper_call.h>
+#include <Fch/Fch.h>
+#include "gpio_ftns.h"
+
+static void early_lpc_init(void)
+{
+ u32 setting = 0x0;
+
+ //
+ // Configure output disabled, value low, pull up/down disabled
+ //
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_32, Function0, GPIO_32, setting);
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_49, Function2, GPIO_49, setting);
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_50, Function2, GPIO_50, setting);
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_71, Function0, GPIO_71, setting);
+ //
+ // Configure output enabled, value low, pull up/down disabled
+ //
+ setting = 0x1 << GPIO_OUTPUT_ENABLE;
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_57, Function1, GPIO_57, setting);
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_58, Function1, GPIO_58, setting);
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_59, Function3, GPIO_59, setting);
+ //
+ // Configure output enabled, value high, pull up/down disabled
+ //
+ setting = 0x1 << GPIO_OUTPUT_ENABLE | 0x1 << GPIO_OUTPUT_VALUE;
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_51, Function2, GPIO_51, setting);
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_55, Function3, GPIO_55, setting);
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_64, Function2, GPIO_64, setting);
+ configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_68, Function0, GPIO_68, setting);
+}
+
+void car_mainboard_pre_console_init(void)
+{
+ /*
+ * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
+ * LpcClk[1:0]". This following register setting has been
+ * replicated in every reference design since Parmer, so it is
+ * believed to be required even though it is not documented in
+ * the SoC BKDGs. Without this setting, there is no serial
+ * output.
+ */
+ outb(0xD2, 0xcd6);
+ outb(0x00, 0xcd7);
+
+ early_lpc_init();
+
+ hudson_clk_output_48Mhz();
+}
diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c
index f8ed63c..9dbf06c 100644
--- a/src/mainboard/pcengines/apu2/romstage.c
+++ b/src/mainboard/pcengines/apu2/romstage.c
@@ -26,54 +26,13 @@
#include <console/console.h>
#include <commonlib/loglevel.h>
#include <cpu/amd/car.h>
+#include <cpu/amd/pi/car.h>
#include <northbridge/amd/pi/agesawrapper.h>
#include <northbridge/amd/pi/agesawrapper_call.h>
-#include <cpu/x86/bist.h>
-#include <cpu/x86/lapic.h>
-#include <southbridge/amd/pi/hudson/hudson.h>
#include <cpu/amd/pi/s3_resume.h>
-#include <Fch/Fch.h>
-#include "gpio_ftns.h"
-
-static void early_lpc_init(void);
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+void cache_as_ram_stage_main(void)
{
- u32 val;
-
- /*
- * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
- * LpcClk[1:0]". This following register setting has been
- * replicated in every reference design since Parmer, so it is
- * believed to be required even though it is not documented in
- * the SoC BKDGs. Without this setting, there is no serial
- * output.
- */
- outb(0xD2, 0xcd6);
- outb(0x00, 0xcd7);
-
- amd_initmmio();
-
- hudson_lpc_port80();
-
- if (!cpu_init_detectedx && boot_cpu()) {
- post_code(0x30);
- early_lpc_init();
-
- hudson_clk_output_48Mhz();
- post_code(0x31);
- console_init();
- }
-
- /* Halt if there was a built in self test failure */
- post_code(0x34);
- report_bist_failure(bist);
-
- /* Load MPB */
- val = cpuid_eax(1);
- printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
- printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
-
post_code(0x37);
AGESAWRAPPER(amdinitreset);
@@ -114,32 +73,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x54); /* Should never see this post code. */
}
-
-
-static void early_lpc_init(void)
-{
- u32 setting = 0x0;
-
- //
- // Configure output disabled, value low, pull up/down disabled
- //
- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_32, Function0, GPIO_32, setting);
- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_49, Function2, GPIO_49, setting);
- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_50, Function2, GPIO_50, setting);
- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_71, Function0, GPIO_71, setting);
- //
- // Configure output enabled, value low, pull up/down disabled
- //
- setting = 0x1 << GPIO_OUTPUT_ENABLE;
- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_57, Function1, GPIO_57, setting);
- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_58, Function1, GPIO_58, setting);
- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_59, Function3, GPIO_59, setting);
- //
- // Configure output enabled, value high, pull up/down disabled
- //
- setting = 0x1 << GPIO_OUTPUT_ENABLE | 0x1 << GPIO_OUTPUT_VALUE;
- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_51, Function2, GPIO_51, setting);
- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_55, Function3, GPIO_55, setting);
- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_64, Function2, GPIO_64, setting);
- configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_68, Function0, GPIO_68, setting);
-}
diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c
index 553add9..32abaff 100644
--- a/src/southbridge/amd/pi/hudson/early_setup.c
+++ b/src/southbridge/amd/pi/hudson/early_setup.c
@@ -26,6 +26,7 @@
#include "hudson.h"
#include "pci_devs.h"
#include <Fch/Fch.h>
+#include <cpu/amd/pi/car.h>
#if IS_ENABLED(CONFIG_HUDSON_UART)
@@ -57,6 +58,16 @@ void configure_hudson_uart(void)
#endif
+void car_sb_pre_console_init(void)
+{
+ hudson_lpc_port80();
+ hudson_lpc_decode();
+
+#if IS_ENABLED(CONFIG_HUDSON_UART)
+ configure_hudson_uart();
+#endif
+}
+
void hudson_pci_port80(void)
{
u8 byte;