coreboot-gerrit December 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: intel/skylake: Perform lockdown in bootstate after MRC write
by build bot (Jenkins) (Code Review) 18 Dec '17

18 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22939 ) Change subject: intel/skylake: Perform lockdown in bootstate after MRC write ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19540/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64761/ : SUCCESS -- To view, visit https://review.coreboot.org/22939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifa4eaba72defc403908fffe3d19dbd3e16e14622 Gerrit-Change-Number: 22939 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 18 Dec 2017 23:46:44 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: google/kahlee: Create mainboard_pirq_data
by Richard Spiegel (Code Review) 18 Dec '17

18 Dec '17

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/22940 Change subject: google/kahlee: Create mainboard_pirq_data ...................................................................... google/kahlee: Create mainboard_pirq_data When booting kahlee, there's an error message: "Warning: Can't write PCI IRQ assignments because 'mainboard_pirq_data' structure does not exist". This is caused by missing mainboard_pirq_data. Create mainboard_pirq_data and update pirq_setup() to set the values of pirq_data_ptr and pirq_data_size. BUG=b:70788755 TEST=Build and boot kahlee. Warning message must be gone. Verify output from write_pci_cfg_irqs and explain anything that does not fit a pattern (what all other devices are producing). Change-Id: If07d2f54f06f6cf77566c43eddc8ee8a314e7a3a Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/mainboard/google/kahlee/mainboard.c 1 file changed, 28 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/22940/1 diff --git a/src/mainboard/google/kahlee/mainboard.c b/src/mainboard/google/kahlee/mainboard.c index 0954a29..6deac3f 100644 --- a/src/mainboard/google/kahlee/mainboard.c +++ b/src/mainboard/google/kahlee/mainboard.c @@ -22,6 +22,7 @@ #include <baseboard/variants.h> #include <boardid.h> #include <soc/nvs.h> +#include <soc/pci_devs.h> #include <soc/smi.h> #include <soc/southbridge.h> #include <variant/ec.h> @@ -77,9 +78,36 @@ [0x78] = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, }; + +/* + * This table defines the index into the picr/intr_data + * tables for each device. Any enabled device and slot + * that uses hardware interrupts should have an entry + * in this table to define its index into the FCH + * PCI_INTR register 0xC00/0xC01. This index will define + * the interrupt that it should use. Putting PIRQ_A into + * the PIN A index for a device will tell that device to + * use PIC IRQ 10 if it uses PIN A for its hardware INT. + */ +static const struct pirq_struct mainboard_pirq_data[] = { + {PCIE0_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* PCIe 0 */ + {PCIE1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* PCIe 1 */ + {PCIE2_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* PCIe 2 */ + {PCIE3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* PCIe 3 */ + {PCIE4_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D} }, /* PCIe 4 */ + {HDA0_DEVFN, {PIRQ_NC, PIRQ_HDA, PIRQ_NC, PIRQ_NC} }, /* HDA */ + {SD_DEVFN, {PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* SD */ + {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* SMBUS */ + {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* SATA */ + {EHCI1_DEVFN, {PIRQ_EHCI, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* EHCI */ + {XHCI_DEVFN, {PIRQ_XHCI, PIRQ_NC, PIRQ_NC, PIRQ_NC} }, /* XHCI */ +}; + /* PIRQ Setup */ static void pirq_setup(void) { + pirq_data_ptr = mainboard_pirq_data; + pirq_data_size = ARRAY_SIZE(mainboard_pirq_data); intr_data_ptr = mainboard_intr_data; picr_data_ptr = mainboard_picr_data; } -- To view, visit https://review.coreboot.org/22940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If07d2f54f06f6cf77566c43eddc8ee8a314e7a3a Gerrit-Change-Number: 22940 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: drivers/mrc_cache: Make bootstate for SPI writes variable
by build bot (Jenkins) (Code Review) 18 Dec '17

18 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22937 ) Change subject: drivers/mrc_cache: Make bootstate for SPI writes variable ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19538/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64759/ : SUCCESS -- To view, visit https://review.coreboot.org/22937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie7ba9070829d98414ee788e14d1a768145d742ea Gerrit-Change-Number: 22937 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 18 Dec 2017 23:39:06 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: intel/skylake: Perform lockdown in bootstate after MRC write
by Marshall Dawson (Code Review) 18 Dec '17

18 Dec '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22939 Change subject: intel/skylake: Perform lockdown in bootstate after MRC write ...................................................................... intel/skylake: Perform lockdown in bootstate after MRC write The bootstate where MRC data is written to flash is now variable. Make the lockdown procedure's timing variable too, and follow the write by one state. Change-Id: Ifa4eaba72defc403908fffe3d19dbd3e16e14622 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/intel/skylake/lockdown.c 1 file changed, 18 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/22939/1 diff --git a/src/soc/intel/skylake/lockdown.c b/src/soc/intel/skylake/lockdown.c index 79f6f70..31a9b34 100644 --- a/src/soc/intel/skylake/lockdown.c +++ b/src/soc/intel/skylake/lockdown.c @@ -109,5 +109,21 @@ pmc_lockdown_config(); } -BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, platform_lockdown_config, - NULL); +#define LOCKDOWN_BOOTSTATE (CONFIG_MRC_WRITE_BOOTSTATE + 1) + +#if LOCKDOWN_BOOTSTATE == 3 +BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, + platform_lockdown_config, NULL); +#elif LOCKDOWN_BOOTSTATE == 4 +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, + platform_lockdown_config, NULL); +#elif LOCKDOWN_BOOTSTATE == 5 +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, + platform_lockdown_config, NULL); +#elif LOCKDOWN_BOOTSTATE == 6 +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, + platform_lockdown_config, NULL); +#elif LOCKDOWN_BOOTSTATE == 7 +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_EXIT, + platform_lockdown_config, NULL); +#endif -- To view, visit https://review.coreboot.org/22939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifa4eaba72defc403908fffe3d19dbd3e16e14622 Gerrit-Change-Number: 22939 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: intel/cannonlake: Perform lockdown in bootstate after MRC write
by Marshall Dawson (Code Review) 18 Dec '17

18 Dec '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22938 Change subject: intel/cannonlake: Perform lockdown in bootstate after MRC write ...................................................................... intel/cannonlake: Perform lockdown in bootstate after MRC write The bootstate where MRC data is written to flash is now variable. Make the lockdown procedure's timing variable too, and follow the write by one state. Change-Id: I7e8776e216e2be9ba54a97dbd79b840806e12469 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/intel/cannonlake/lockdown.c 1 file changed, 18 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/22938/1 diff --git a/src/soc/intel/cannonlake/lockdown.c b/src/soc/intel/cannonlake/lockdown.c index dba5901..d9f6da6 100644 --- a/src/soc/intel/cannonlake/lockdown.c +++ b/src/soc/intel/cannonlake/lockdown.c @@ -109,5 +109,21 @@ pmc_lockdown_cfg(config); } -BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, platform_lockdown_config, - NULL); +#define LOCKDOWN_BOOTSTATE (CONFIG_MRC_WRITE_BOOTSTATE + 1) + +#if LOCKDOWN_BOOTSTATE == 3 +BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, + platform_lockdown_config, NULL); +#elif LOCKDOWN_BOOTSTATE == 4 +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, + platform_lockdown_config, NULL); +#elif LOCKDOWN_BOOTSTATE == 5 +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, + platform_lockdown_config, NULL); +#elif LOCKDOWN_BOOTSTATE == 6 +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, + platform_lockdown_config, NULL); +#elif LOCKDOWN_BOOTSTATE == 7 +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_EXIT, + platform_lockdown_config, NULL); +#endif -- To view, visit https://review.coreboot.org/22938 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7e8776e216e2be9ba54a97dbd79b840806e12469 Gerrit-Change-Number: 22938 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: drivers/mrc_cache: Make bootstate for SPI writes variable
by Marshall Dawson (Code Review) 18 Dec '17

18 Dec '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22937 Change subject: drivers/mrc_cache: Make bootstate for SPI writes variable ...................................................................... drivers/mrc_cache: Make bootstate for SPI writes variable The default bootstate for writing MRC data to flash is BS_DEV_ENUMERATE but this is too early for some implementations. Add options to Kconfig for allowing a different bootstate to be selected. It is assumed SPI lockdown will always execute in the state immediately following writing to flash. The latest that may be allowed is BS_OS_RESUME_CHECK, so the latest MRC data may be written is BS_POST_DEVICE. The earliest is maintained at BS_DEV_ENUMERATE. Change-Id: Ie7ba9070829d98414ee788e14d1a768145d742ea Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/drivers/mrc_cache/Kconfig M src/drivers/mrc_cache/mrc_cache.c 2 files changed, 35 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/22937/1 diff --git a/src/drivers/mrc_cache/Kconfig b/src/drivers/mrc_cache/Kconfig index 3e0bdda..e15696d 100644 --- a/src/drivers/mrc_cache/Kconfig +++ b/src/drivers/mrc_cache/Kconfig @@ -28,4 +28,21 @@ bool default n +config MRC_WRITE_BOOTSTATE + int "Write MRC settings at bootstate" + range 2 6 + default 2 # BS_DEV_ENUMERATE + help + This option specifies when the MRC settings are written to NVRAM. + The write occurs at the end of the bootstate indicated. These + definitions must be kept in sync with boot_state_t: + 2: BS_DEV_ENUMERATE, + 3: BS_DEV_RESOURCES, + 4: BS_DEV_ENABLE, + 5: BS_DEV_INIT, + 6: BS_POST_DEVICE, + + Any NVRAM lockdown procedure will be run in the stage after writing + the MRC settings, and before BS_OS_RESUME. + endif # CACHE_MRC_SETTINGS diff --git a/src/drivers/mrc_cache/mrc_cache.c b/src/drivers/mrc_cache/mrc_cache.c index 3a96896..c76f613 100644 --- a/src/drivers/mrc_cache/mrc_cache.c +++ b/src/drivers/mrc_cache/mrc_cache.c @@ -574,8 +574,23 @@ } /* - * Ensures MRC training data is stored into SPI after PCI enumeration is done - * during BS_DEV_ENUMERATE-BS_ON_EXIT and lock down SPI protected ranges - * during BS_DEV_RESOURCES-BS_ON_EXIT. + * Ensures MRC training data is stored into SPI after PCI enumeration is done. + * Some implementations may be require this to be later than others. Locking + * down SPI protected ranges will occur at the end of the subsequent bootstate. */ + +#if CONFIG_MRC_WRITE_BOOTSTATE == 8 /* BS_OS_RESUME */ +#error "Choose a different bootstate for writing MRC cache data" +#endif + +#if CONFIG_MRC_WRITE_BOOTSTATE == 2 BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_EXIT, update_mrc_cache, NULL); +#elif CONFIG_MRC_WRITE_BOOTSTATE == 3 +BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, update_mrc_cache, NULL); +#elif CONFIG_MRC_WRITE_BOOTSTATE == 4 +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, update_mrc_cache, NULL); +#elif CONFIG_MRC_WRITE_BOOTSTATE == 5 +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, update_mrc_cache, NULL); +#elif CONFIG_MRC_WRITE_BOOTSTATE == 6 +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, update_mrc_cache, NULL); +#endif -- To view, visit https://review.coreboot.org/22937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie7ba9070829d98414ee788e14d1a768145d742ea Gerrit-Change-Number: 22937 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: soc/intel/cannonlake: Correct PMC/GPIO routing information
by build bot (Jenkins) (Code Review) 18 Dec '17

18 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22908 ) Change subject: soc/intel/cannonlake: Correct PMC/GPIO routing information ...................................................................... Patch Set 7: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19536/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64757/ : SUCCESS -- To view, visit https://review.coreboot.org/22908 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1edb83edabc72e8a762b129cf51dcd936cd37ddf Gerrit-Change-Number: 22908 Gerrit-PatchSet: 7 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 18 Dec 2017 19:44:00 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: superio/f71869ad: Add temperature sensor type
by build bot (Jenkins) (Code Review) 18 Dec '17

18 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22935 ) Change subject: superio/f71869ad: Add temperature sensor type ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19533/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64754/ : SUCCESS -- To view, visit https://review.coreboot.org/22935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6af0d93061ec49aec7a9181cdf7affd60fbdca73 Gerrit-Change-Number: 22935 Gerrit-PatchSet: 1 Gerrit-Owner: Renze Nicolai <renze(a)rnplus.nl> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 18 Dec 2017 19:36:36 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/ms7721: Fix superio configuration
by build bot (Jenkins) (Code Review) 18 Dec '17

18 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22922 ) Change subject: mainboard/ms7721: Fix superio configuration ...................................................................... Patch Set 4: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/64755/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/19534/ : SUCCESS -- To view, visit https://review.coreboot.org/22922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6491171eacc0c9848ba86ba7a62ec440226aae36 Gerrit-Change-Number: 22922 Gerrit-PatchSet: 4 Gerrit-Owner: Renze Nicolai <renze(a)rnplus.nl> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 18 Dec 2017 19:35:27 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: superio/f71869ad: Add temperature sensor type
by Renze Nicolai (Code Review) 18 Dec '17

18 Dec '17

Renze Nicolai has uploaded this change for review. ( https://review.coreboot.org/22935 Change subject: superio/f71869ad: Add temperature sensor type ...................................................................... superio/f71869ad: Add temperature sensor type This patch makes it possible to set the "Temperature Sensor Type Register" at index 6Bh from the devicetree, allowing the use of thermistors instead of BJT type sensors. Register documentation (from page 60 of the F71869 datasheet): 6.6.25 Temperature Sensor Type Register - Index 6Bh Bit 7-4: reserved Bit 3: T3_MODE (0: thermistor, 1: BJT [default]) Bit 2: T2_MODE (0: thermistor, 1: BJT [default]) Bit 1: T1_MODE (0: thermistor, 1: BJT [default]) Bit 0: reserved Change-Id: I6af0d93061ec49aec7a9181cdf7affd60fbdca73 Signed-off-by: Renze Nicolai <renze(a)rnplus.nl> --- M src/superio/fintek/f71869ad/chip.h M src/superio/fintek/f71869ad/f71869ad_hwm.c 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/22935/1 diff --git a/src/superio/fintek/f71869ad/chip.h b/src/superio/fintek/f71869ad/chip.h index 4e4323e..42d451d 100644 --- a/src/superio/fintek/f71869ad/chip.h +++ b/src/superio/fintek/f71869ad/chip.h @@ -37,6 +37,7 @@ uint8_t hwm_fan1_seg2_speed_count; uint8_t hwm_fan1_seg3_speed_count; uint8_t hwm_fan1_temp_map_sel; + uint8_t hwm_temp_sensor_type; }; #endif /* SUPERIO_FINTEK_F71869AD_CHIP_H */ diff --git a/src/superio/fintek/f71869ad/f71869ad_hwm.c b/src/superio/fintek/f71869ad/f71869ad_hwm.c index d253e5f..b0b1a6b 100644 --- a/src/superio/fintek/f71869ad/f71869ad_hwm.c +++ b/src/superio/fintek/f71869ad/f71869ad_hwm.c @@ -50,6 +50,7 @@ #define HWM_FAN1_SEG2_SPEED_COUNT 0xAB #define HWM_FAN1_SEG3_SPEED_COUNT 0xAC #define HWM_FAN1_TEMP_MAP_SEL 0xAF +#define HWM_TEMP_SENSOR_TYPE 0x6B /* note: multifunc registers need to be tweaked before here */ void f71869ad_hwm_init(struct device *dev) @@ -97,6 +98,8 @@ pnp_write_index(port, HWM_FAN1_SEG1_SPEED_COUNT, conf->hwm_fan1_seg1_speed_count); pnp_write_index(port, HWM_FAN1_SEG2_SPEED_COUNT, conf->hwm_fan1_seg2_speed_count); pnp_write_index(port, HWM_FAN1_SEG3_SPEED_COUNT, conf->hwm_fan1_seg3_speed_count); + /* Temperature sensor type */ + pnp_write_index(port, HWM_TEMP_SENSOR_TYPE, conf->hwm_temp_sensor_type); pnp_exit_conf_mode(dev); } -- To view, visit https://review.coreboot.org/22935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6af0d93061ec49aec7a9181cdf7affd60fbdca73 Gerrit-Change-Number: 22935 Gerrit-PatchSet: 1 Gerrit-Owner: Renze Nicolai <renze(a)rnplus.nl>

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coreboot-gerrit December 2017