coreboot-gerrit December 2017

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Change in coreboot[master]: soc/intel/cannonlake: Program OPI PCR LPC registers
by build bot (Jenkins) (Code Review) 19 Dec '17

19 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22941 ) Change subject: soc/intel/cannonlake: Program OPI PCR LPC registers ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/64767/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/19545/ : SUCCESS -- To view, visit https://review.coreboot.org/22941 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I520afa8c5b2113efab7b224c7f3002fb30ff57f4 Gerrit-Change-Number: 22941 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 19 Dec 2017 03:14:01 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/cannonlake: Program OPI PCR LPC registers
by Lijian Zhao (Code Review) 19 Dec '17

19 Dec '17

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/22941 Change subject: soc/intel/cannonlake: Program OPI PCR LPC registers ...................................................................... soc/intel/cannonlake: Program OPI PCR LPC registers According to PCH BIOS spec(570374) 2.4.1, DMI cycle decoding need to be programmed before it got locked. Update lpc programming to add decode programming in DMI side as well. Small core soc such as APL,GLK don't have DMI interface, hence make the program optional with SOC. BUG=b.70765863 TEST=Apply changes and add chromeos EC decoding in mainboard ec.c, read back IO port in depthcharge cli and return is not zero. Change-Id: I520afa8c5b2113efab7b224c7f3002fb30ff57f4 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/cannonlake/include/soc/pcr_ids.h M src/soc/intel/common/block/lpc/lpc_lib.c 3 files changed, 36 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/22941/1 diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index 0deece6..088c85e 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -28,30 +28,6 @@ #include <soc/pm.h> #include <soc/smbus.h> -#define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x1400 -#define PCR_PSFX_TO_SHDW_BAR0 0 -#define PCR_PSFX_TO_SHDW_BAR1 0x4 -#define PCR_PSFX_TO_SHDW_BAR2 0x8 -#define PCR_PSFX_TO_SHDW_BAR3 0xC -#define PCR_PSFX_TO_SHDW_BAR4 0x10 -#define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 -#define PCR_PSFX_T0_SHDW_PCIEN 0x1C - -#define PCR_DMI_LPCLGIR1 0x2730 -#define PCR_DMI_LPCLGIR2 0x2734 -#define PCR_DMI_LPCLGIR3 0x2738 -#define PCR_DMI_LPCLGIR4 0x273c - -#define PCR_DMI_ACPIBA 0x27B4 -#define PCR_DMI_ACPIBDID 0x27B8 -#define PCR_DMI_PMBASEA 0x27AC -#define PCR_DMI_PMBASEC 0x27B0 -#define PCR_DMI_TCOBASE 0x2778 -#define TCOEN (1 << 1) /* Enable TCO I/O range decode. */ - -#define PCR_DMI_LPCIOD 0x2770 -#define PCR_DMI_LPCIOE 0x2774 - static void enable_p2sbbar(void) { device_t dev = PCH_DEV_P2SB; diff --git a/src/soc/intel/cannonlake/include/soc/pcr_ids.h b/src/soc/intel/cannonlake/include/soc/pcr_ids.h index 65576aa..9840f0b 100644 --- a/src/soc/intel/cannonlake/include/soc/pcr_ids.h +++ b/src/soc/intel/cannonlake/include/soc/pcr_ids.h @@ -35,4 +35,31 @@ #define PID_LPC 0xc7 #define PID_SERIALIO 0xcb +/* + * OPI PCR register + */ +#define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x1400 +#define PCR_PSFX_TO_SHDW_BAR0 0 +#define PCR_PSFX_TO_SHDW_BAR1 0x4 +#define PCR_PSFX_TO_SHDW_BAR2 0x8 +#define PCR_PSFX_TO_SHDW_BAR3 0xC +#define PCR_PSFX_TO_SHDW_BAR4 0x10 +#define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 +#define PCR_PSFX_T0_SHDW_PCIEN 0x1C + +#define PCR_DMI_LPCLGIR1 0x2730 +#define PCR_DMI_LPCLGIR2 0x2734 +#define PCR_DMI_LPCLGIR3 0x2738 +#define PCR_DMI_LPCLGIR4 0x273c + +#define PCR_DMI_ACPIBA 0x27B4 +#define PCR_DMI_ACPIBDID 0x27B8 +#define PCR_DMI_PMBASEA 0x27AC +#define PCR_DMI_PMBASEC 0x27B0 +#define PCR_DMI_TCOBASE 0x2778 +/* Enable TCO I/O range decode. */ +#define TCOEN (1 << 1) + +#define PCR_DMI_LPCIOD 0x2770 +#define PCR_DMI_LPCIOE 0x2774 #endif diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index b4b3d1b..6a0cda7 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -21,9 +21,13 @@ #include <console/console.h> #include <device/pci.h> #include <intelblocks/lpc_lib.h> +#include <intelblocks/pcr.h> #include <lib.h> #include "lpc_def.h" #include <soc/pci_devs.h> +#include <soc/pcr_ids.h> + +#define PCR_LGIR_OFFSET (PCR_DMI_LPCLGIR1 - 0x84) void lpc_enable_fixed_io_ranges(uint16_t io_enables) { @@ -32,6 +36,8 @@ reg_io_enables = pci_read_config16(PCH_DEV_LPC, LPC_IO_ENABLES); io_enables |= reg_io_enables; pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, io_enables); + if (IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE)) + pcr_write16(PID_DMI, PCR_DMI_LPCIOD, io_enables); } /* @@ -96,6 +102,9 @@ lgir |= ((window_size - 1) << 16) & LPC_LGIR_AMASK_MASK; pci_write_config32(PCH_DEV_LPC, lgir_reg_offset, lgir); + if (IS_ENABLED(CONFIG_SOC_INTEL_CANNONLAKE)) + pcr_write32(PID_DMI, + (lgir_reg_offset + PCR_LGIR_OFFSET), lgir); printk(BIOS_DEBUG, "LPC: Opened IO window LGIR%d: base %llx size %x\n", -- To view, visit https://review.coreboot.org/22941 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I520afa8c5b2113efab7b224c7f3002fb30ff57f4 Gerrit-Change-Number: 22941 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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Change in coreboot[master]: mb/google/poppy: Configure GPP_B0 for WLAN wake
by build bot (Jenkins) (Code Review) 19 Dec '17

19 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22928 ) Change subject: mb/google/poppy: Configure GPP_B0 for WLAN wake ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19543/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64765/ : SUCCESS -- To view, visit https://review.coreboot.org/22928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5198b8083a87d00f890b45986e5e3f62b81686c2 Gerrit-Change-Number: 22928 Gerrit-PatchSet: 4 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 19 Dec 2017 02:51:10 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy: Configure WWAN gpios
by build bot (Jenkins) (Code Review) 19 Dec '17

19 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22927 ) Change subject: mb/google/poppy: Configure WWAN gpios ...................................................................... Patch Set 3: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/64766/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/19544/ : SUCCESS -- To view, visit https://review.coreboot.org/22927 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If9b575568cabcbee03ad190b69d9c033890f7fa6 Gerrit-Change-Number: 22927 Gerrit-PatchSet: 3 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 19 Dec 2017 02:42:08 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy: Configure GPP_B0 for WLAN wake
by build bot (Jenkins) (Code Review) 19 Dec '17

19 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22928 ) Change subject: mb/google/poppy: Configure GPP_B0 for WLAN wake ...................................................................... Patch Set 3: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/64764/ : FAILURE -- To view, visit https://review.coreboot.org/22928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5198b8083a87d00f890b45986e5e3f62b81686c2 Gerrit-Change-Number: 22928 Gerrit-PatchSet: 3 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 19 Dec 2017 02:36:14 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/ms7721: Fix temperature sensor configuration
by build bot (Jenkins) (Code Review) 19 Dec '17

19 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22922 ) Change subject: mainboard/ms7721: Fix temperature sensor configuration ...................................................................... Patch Set 6: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19542/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64763/ : SUCCESS -- To view, visit https://review.coreboot.org/22922 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6491171eacc0c9848ba86ba7a62ec440226aae36 Gerrit-Change-Number: 22922 Gerrit-PatchSet: 6 Gerrit-Owner: Renze Nicolai <renze(a)rnplus.nl> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Renze Nicolai <renze(a)rnplus.nl> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 19 Dec 2017 00:38:36 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: google/kahlee: Create mainboard_pirq_data
by Richard Spiegel (Code Review) 19 Dec '17

19 Dec '17

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/22940 ) Change subject: google/kahlee: Create mainboard_pirq_data ...................................................................... Patch Set 1: Local test results: PCI IRQ: Found device 0:01.00 using PIN A PCI Devfn (0x8) not found in pirq_data table GFX does not has interrupt. ---------------------- PCI IRQ: Found device 0:08.00 using PIN A PCI Devfn (0x40) not found in pirq_data table PSP does not has interrupt. ---------------------- PCI IRQ: Found device 0:11.00 using PIN A Found this device in pirq_data table entry 8 Got IRQ 0x1F (disabled), perhaps this device was defined wrong? SATA PIC mode wrong in mainboard_picr_data[] ---------------------- PCI IRQ: Found device 0:14.07 using PIN A Found this device in pirq_data table entry 6 Got IRQ 0x1F (disabled), perhaps this device was defined wrong? SD PIC mode wrong in mainboard_picr_data[] ---------------------- Is PIC mode important? I believe Chromium uses APIC mode. -- To view, visit https://review.coreboot.org/22940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If07d2f54f06f6cf77566c43eddc8ee8a314e7a3a Gerrit-Change-Number: 22940 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 19 Dec 2017 00:34:36 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: google/kahlee: Create mainboard_pirq_data
by Richard Spiegel (Code Review) 19 Dec '17

19 Dec '17

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/22940 ) Change subject: google/kahlee: Create mainboard_pirq_data ...................................................................... Patch Set 1: Not sure why it failed. Following report, apparently failed building Google Bob. However, it's not even x86 (a little research indicates ARM Cortex-A72). So no kahlee change (my only change) should cause any problem. -- To view, visit https://review.coreboot.org/22940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If07d2f54f06f6cf77566c43eddc8ee8a314e7a3a Gerrit-Change-Number: 22940 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 19 Dec 2017 00:25:59 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: google/kahlee: Create mainboard_pirq_data
by build bot (Jenkins) (Code Review) 18 Dec '17

18 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22940 ) Change subject: google/kahlee: Create mainboard_pirq_data ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/64762/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/19541/ : SUCCESS -- To view, visit https://review.coreboot.org/22940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If07d2f54f06f6cf77566c43eddc8ee8a314e7a3a Gerrit-Change-Number: 22940 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 18 Dec 2017 23:49:34 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: intel/cannonlake: Perform lockdown in bootstate after MRC write
by build bot (Jenkins) (Code Review) 18 Dec '17

18 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22938 ) Change subject: intel/cannonlake: Perform lockdown in bootstate after MRC write ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/64760/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/19539/ : SUCCESS -- To view, visit https://review.coreboot.org/22938 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7e8776e216e2be9ba54a97dbd79b840806e12469 Gerrit-Change-Number: 22938 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 18 Dec 2017 23:48:57 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit December 2017