coreboot-gerrit December 2017

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Change in coreboot[master]: mb/hp/xxx0p: set ACPI and SLPT bit in _WAK and _PTS
by Arthur Heymans (Code Review) 18 Dec '17

18 Dec '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/22929 ) Change subject: mb/hp/xxx0p: set ACPI and SLPT bit in _WAK and _PTS ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/22929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2badc69510275df57938cb8607b3c4e0df50f028 Gerrit-Change-Number: 22929 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 18 Dec 2017 14:18:32 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: [WIP]mb/lenovo/x200: Use lower C-states on battery
by build bot (Jenkins) (Code Review) 18 Dec '17

18 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22932 ) Change subject: [WIP]mb/lenovo/x200: Use lower C-states on battery ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/64745/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/19524/ : SUCCESS -- To view, visit https://review.coreboot.org/22932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idf32ee2ac3272fee74ce3b92b2c537cb722991d7 Gerrit-Change-Number: 22932 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 18 Dec 2017 13:21:00 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: ec/h8: Store PWRS and notify CPU on AC power plug/unplug events
by build bot (Jenkins) (Code Review) 18 Dec '17

18 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22931 ) Change subject: ec/h8: Store PWRS and notify CPU on AC power plug/unplug events ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19523/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64744/ : SUCCESS -- To view, visit https://review.coreboot.org/22931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0818d10474523fb14f7ba7cfbf61166b89442083 Gerrit-Change-Number: 22931 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 18 Dec 2017 13:17:42 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: [WIP]mb/lenovo/x200: Use lower C-states on battery
by Arthur Heymans (Code Review) 18 Dec '17

18 Dec '17

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/22932 Change subject: [WIP]mb/lenovo/x200: Use lower C-states on battery ...................................................................... [WIP]mb/lenovo/x200: Use lower C-states on battery The PNOT method in cpu.asl is very broken as it depends on inexisting PDCx variables. This adds an array with C6 as lowest CPU cstate on battery for thinkpad x200. TODO: fix cpu.asl (newer gen seems to do it better) Fix all other boards Change-Id: Idf32ee2ac3272fee74ce3b92b2c537cb722991d7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/include/arch/acpigen.h M src/cpu/intel/common/acpi/cpu.asl M src/cpu/intel/speedstep/acpi.c M src/mainboard/lenovo/x200/cstates.c 4 files changed, 61 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/22932/1 diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 9ec6ee1..c415da1 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -277,6 +277,7 @@ uint8_t flags); int get_cst_entries(acpi_cstate_t **); +int get_bat_cst_entries(acpi_cstate_t **); /* * Soc-implemented functions for generating ACPI AML code for GPIO handling. All diff --git a/src/cpu/intel/common/acpi/cpu.asl b/src/cpu/intel/common/acpi/cpu.asl index 117ef46..456b9f7 100644 --- a/src/cpu/intel/common/acpi/cpu.asl +++ b/src/cpu/intel/common/acpi/cpu.asl @@ -25,22 +25,13 @@ Method (PNOT) { If (MPEN) { - If(And(PDC0, 0x08)) { - Notify (\_PR_.CP00, 0x80) // _PPC + Notify (\_PR_.CP00, 0x80) // _PPC + Sleep(100) + Notify(\_PR_.CP00, 0x81) // _CST - If (And(PDC0, 0x10)) { - Sleep(100) - Notify(\_PR_.CP00, 0x81) // _CST - } - } - - If(And(PDC1, 0x08)) { - Notify (\_PR_.CP01, 0x80) // _PPC - If (And(PDC1, 0x10)) { - Sleep(100) - Notify(\_PR_.CP01, 0x81) // _CST - } - } + Notify (\_PR_.CP01, 0x80) // _PPC + Sleep(100) + Notify(\_PR_.CP01, 0x81) // _CST } Else { // UP Notify (\_PR_.CP00, 0x80) diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c index c154da0..969fc9b 100644 --- a/src/cpu/intel/speedstep/acpi.c +++ b/src/cpu/intel/speedstep/acpi.c @@ -109,6 +109,19 @@ acpigen_write_PPC(0); } +static void generate_C_state_entries(acpi_cstate_t *cstate, int nentries) +{ + int i; + acpigen_write_package(nentries+1); + acpigen_write_dword(nentries); + + for (i = 0; i < nentries; i++) + acpigen_write_CST_package_entry(cstate + i); + + acpigen_pop_len(); + +} + /** * @brief Generate ACPI entries for Speedstep for each cpu */ @@ -120,8 +133,8 @@ int numcpus = totalcores/cores_per_package; /* This assumes that all CPUs share the same layout. */ - int num_cstates; - acpi_cstate_t *cstates; + int num_cstates, num_bat_cstates; + acpi_cstate_t *cstates, *bat_cstates; sst_table_t pstates; uint8_t coordination; @@ -129,6 +142,7 @@ numcpus, cores_per_package); num_cstates = get_cst_entries(&cstates); + num_bat_cstates = get_bat_cst_entries(&bat_cstates); speedstep_gen_pstates(&pstates); if (((cpuid_eax(1) >> 4) & 0xffff) == 0x1067) /* For Penryn use HW_ALL. */ @@ -154,10 +168,20 @@ cores_per_package, coordination); /* Generate c-state entries. */ - if (num_cstates > 0) - acpigen_write_CST_package( - cstates, num_cstates); - + if (num_cstates > 0) { + acpigen_write_method("_CST", 0); + acpigen_write_if(); + acpigen_emit_namestring("PWRS"); + acpigen_emit_byte(RETURN_OP); + generate_C_state_entries(cstates, num_cstates); + acpigen_pop_len(); + if (num_bat_cstates > 0) { + acpigen_emit_byte(RETURN_OP); + generate_C_state_entries(bat_cstates, + num_bat_cstates); + } + acpigen_pop_len(); + } acpigen_pop_len(); } } diff --git a/src/mainboard/lenovo/x200/cstates.c b/src/mainboard/lenovo/x200/cstates.c index 175153e..66d50ad 100644 --- a/src/mainboard/lenovo/x200/cstates.c +++ b/src/mainboard/lenovo/x200/cstates.c @@ -35,8 +35,32 @@ }, }; +static acpi_cstate_t bat_cst_entries[] = { + { + /* ACPI C1 / CPU C1 */ + 1, 0x01, 1000, + { ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0, 0 } + }, + { + /* ACPI C2 / CPU C2 */ + 2, 0x01, 500, + { ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0x10, 0 } + }, + { + /* acpi C3 / cpu C6 */ + 3, 0x37, 250, + { ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0x50, 0 } + }, +}; + int get_cst_entries(acpi_cstate_t **entries) { *entries = cst_entries; return ARRAY_SIZE(cst_entries); } + +int get_bat_cst_entries(acpi_cstate_t **entries) +{ + *entries = bat_cst_entries; + return ARRAY_SIZE(bat_cst_entries); +} -- To view, visit https://review.coreboot.org/22932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Idf32ee2ac3272fee74ce3b92b2c537cb722991d7 Gerrit-Change-Number: 22932 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: ec/h8: Store PWRS and notify CPU on AC power plug/unplug events
by Arthur Heymans (Code Review) 18 Dec '17

18 Dec '17

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/22931 Change subject: ec/h8: Store PWRS and notify CPU on AC power plug/unplug events ...................................................................... ec/h8: Store PWRS and notify CPU on AC power plug/unplug events PWRS is is the power source gnvs. Notifying CPU is needed to change P- and C-states on these events. Change-Id: I0818d10474523fb14f7ba7cfbf61166b89442083 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/ec/lenovo/h8/acpi/ac.asl M src/ec/lenovo/h8/acpi/ec.asl 2 files changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/22931/1 diff --git a/src/ec/lenovo/h8/acpi/ac.asl b/src/ec/lenovo/h8/acpi/ac.asl index 91b9d79..43b43d7 100644 --- a/src/ec/lenovo/h8/acpi/ac.asl +++ b/src/ec/lenovo/h8/acpi/ac.asl @@ -29,7 +29,10 @@ Method(_PSR, 0, NotSerialized) { - return (HPAC) + Store(HPAC, Local0) + Store(Local0, \PWRS) + \PNOT() + return (Local0) } Method(_STA, 0, NotSerialized) diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl index 944858f..b6121aa 100644 --- a/src/ec/lenovo/h8/acpi/ec.asl +++ b/src/ec/lenovo/h8/acpi/ec.asl @@ -149,6 +149,7 @@ Method(_Q26, 0, NotSerialized) { Notify (AC, 0x80) + \PNOT() } /* AC status change: not present */ @@ -156,6 +157,7 @@ { Notify (AC, 0x80) Store(0x50, EVNT) + \PNOT() } Method(_Q2A, 0, NotSerialized) -- To view, visit https://review.coreboot.org/22931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0818d10474523fb14f7ba7cfbf61166b89442083 Gerrit-Change-Number: 22931 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: mb/google/poppy: Enable speaker and codec for nami
by build bot (Jenkins) (Code Review) 18 Dec '17

18 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22861 ) Change subject: mb/google/poppy: Enable speaker and codec for nami ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19522/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64743/ : SUCCESS -- To view, visit https://review.coreboot.org/22861 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iecf4059f8ea3d5e34f33f0be227897a8cca636fa Gerrit-Change-Number: 22861 Gerrit-PatchSet: 5 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Marx Wang <marx.wang(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 18 Dec 2017 11:35:47 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/hp/xxx0p: set ACPI and SLPT bit in _WAK and _PTS
by build bot (Jenkins) (Code Review) 18 Dec '17

18 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22929 ) Change subject: mb/hp/xxx0p: set ACPI and SLPT bit in _WAK and _PTS ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19520/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64741/ : SUCCESS -- To view, visit https://review.coreboot.org/22929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2badc69510275df57938cb8607b3c4e0df50f028 Gerrit-Change-Number: 22929 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 18 Dec 2017 11:17:52 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/intel/nehalem/gma: Drop stale pre-pocessor guards
by build bot (Jenkins) (Code Review) 18 Dec '17

18 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22930 ) Change subject: nb/intel/nehalem/gma: Drop stale pre-pocessor guards ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19521/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64742/ : SUCCESS -- To view, visit https://review.coreboot.org/22930 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2490a3b4dca6c248eb37f43aa676ae619afdbfc7 Gerrit-Change-Number: 22930 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 18 Dec 2017 11:16:12 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: ec/hp/kbc1126/acpi/battery.asl: Make \ISTR serialized
by build bot (Jenkins) (Code Review) 18 Dec '17

18 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21668 ) Change subject: ec/hp/kbc1126/acpi/battery.asl: Make \ISTR serialized ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19519/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64740/ : SUCCESS -- To view, visit https://review.coreboot.org/21668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I36e814acc0746cb011b595493d8254f3fb73baf5 Gerrit-Change-Number: 21668 Gerrit-PatchSet: 2 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 18 Dec 2017 11:15:06 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/intel/nehalem/gma: Drop stale pre-pocessor guards
by Nico Huber (Code Review) 18 Dec '17

18 Dec '17

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/22930 Change subject: nb/intel/nehalem/gma: Drop stale pre-pocessor guards ...................................................................... nb/intel/nehalem/gma: Drop stale pre-pocessor guards These were forgotten when updating the caller and resulted in build failures for every but the NGI path. Change-Id: I2490a3b4dca6c248eb37f43aa676ae619afdbfc7 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/northbridge/intel/nehalem/gma.c 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/22930/1 diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c index 0db8f3c..0c681cc 100644 --- a/src/northbridge/intel/nehalem/gma.c +++ b/src/northbridge/intel/nehalem/gma.c @@ -572,8 +572,6 @@ } } -#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) - static void train_link(u8 *mmio) { /* Clear interrupts. */ @@ -1009,8 +1007,6 @@ } } -#endif - /* Enable SCI to ACPI _GPE._L06 */ static void gma_enable_swsci(void) { -- To view, visit https://review.coreboot.org/22930 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2490a3b4dca6c248eb37f43aa676ae619afdbfc7 Gerrit-Change-Number: 22930 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de>

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coreboot-gerrit December 2017