coreboot-gerrit December 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: intel/bd82x6x: Refactor IRQ routing
by build bot (Jenkins) (Code Review) 07 Dec '17

07 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22601 ) Change subject: intel/bd82x6x: Refactor IRQ routing ...................................................................... Patch Set 13: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19102/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64284/ : SUCCESS -- To view, visit https://review.coreboot.org/22601 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7229aee3817f1f4979325a2abccbb3b99ad312f6 Gerrit-Change-Number: 22601 Gerrit-PatchSet: 13 Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 Dec 2017 22:59:52 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: Update vboot submodule to upstream master
by build bot (Jenkins) (Code Review) 07 Dec '17

07 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22777 ) Change subject: Update vboot submodule to upstream master ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19100/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64282/ : SUCCESS -- To view, visit https://review.coreboot.org/22777 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I49b1349cfd9266cd815b68759ae89bdffdd0d74b Gerrit-Change-Number: 22777 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 Dec 2017 22:33:02 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: Update vboot submodule to upstream master
by Marc Jones (Code Review) 07 Dec '17

07 Dec '17

Marc Jones has posted comments on this change. ( https://review.coreboot.org/22777 ) Change subject: Update vboot submodule to upstream master ...................................................................... Patch Set 1: This fixes the build issue with depthcharge master. -- To view, visit https://review.coreboot.org/22777 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I49b1349cfd9266cd815b68759ae89bdffdd0d74b Gerrit-Change-Number: 22777 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Comment-Date: Thu, 07 Dec 2017 22:27:22 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: intel/sandybridge: Make timC training more robust.
by build bot (Jenkins) (Code Review) 07 Dec '17

07 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22776 ) Change subject: intel/sandybridge: Make timC training more robust. ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19098/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64280/ : SUCCESS -- To view, visit https://review.coreboot.org/22776 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9986616e86560c4980ccd8e3e549af53caa15c71 Gerrit-Change-Number: 22776 Gerrit-PatchSet: 1 Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 Dec 2017 22:26:36 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: Update vboot submodule to upstream master
by Marc Jones (Code Review) 07 Dec '17

07 Dec '17

Marc Jones has uploaded this change for review. ( https://review.coreboot.org/22777 Change subject: Update vboot submodule to upstream master ...................................................................... Update vboot submodule to upstream master Updating from commit id 3b80572: 2017-10-12 16:35:30 -0700 - (tlcl, tpmc: extend GetVersion to report vendor specific data) to commit id f6780a3: 2017-12-01 14:54:40 -0800 - (firmware: header tweaks for depthcharge) This brings in 19 new commits. Change-Id: I49b1349cfd9266cd815b68759ae89bdffdd0d74b Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- M 3rdparty/vboot 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/22777/1 diff --git a/3rdparty/vboot b/3rdparty/vboot index 3b80572..f6780a3 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 3b805725c15022783f0737a72b4f27962abf48cd +Subproject commit f6780a36ff19b36abcdb5ace903c4ae2272fb574 -- To view, visit https://review.coreboot.org/22777 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I49b1349cfd9266cd815b68759ae89bdffdd0d74b Gerrit-Change-Number: 22777 Gerrit-PatchSet: 1 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>

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Change in coreboot[master]: intel/sandybridge: Make timC training more robust.
by Tobias Diedrich (Code Review) 07 Dec '17

07 Dec '17

Tobias Diedrich has posted comments on this change. ( https://review.coreboot.org/22776 ) Change subject: intel/sandybridge: Make timC training more robust. ...................................................................... Patch Set 1: >From the training log output with my DDR3-1333 1.5 RAM: threshold=2001 min=2 max=4000 timC: 0, 0, 0: 0x02-0x1f-0x3d threshold=2000 min=0 max=4000 timC: 0, 0, 1: 0x00-0x1c-0x39 threshold=2001 min=2 max=4000 timC: 0, 0, 2: 0x1e-0x38-0x53 threshold=2000 min=0 max=4000 timC: 0, 0, 3: 0x25-0x42-0x60 threshold=2000 min=0 max=4000 timC: 0, 0, 4: 0x35-0x53-0x71 threshold=2000 min=0 max=4000 timC: 0, 0, 5: 0x3c-0x5a-0x78 threshold=2000 min=0 max=4000 timC: 0, 0, 6: 0x22-0x40-0x5e threshold=2000 min=0 max=4000 timC: 0, 0, 7: 0x0b-0x28-0x45 threshold=2995 min=1991 max=4000 timC: 0, 1, 0: 0x02-0x1f-0x3d threshold=2000 min=0 max=4000 timC: 0, 1, 1: 0x01-0x1d-0x3a threshold=2225 min=451 max=4000 timC: 0, 1, 2: 0x22-0x3d-0x58 threshold=2000 min=0 max=4000 timC: 0, 1, 3: 0x29-0x45-0x61 threshold=2000 min=0 max=4000 timC: 0, 1, 4: 0x39-0x56-0x73 threshold=2000 min=0 max=4000 timC: 0, 1, 5: 0x7e-0x1b-0x39 threshold=2000 min=0 max=4000 timC: 0, 1, 6: 0x22-0x3f-0x5c threshold=2000 min=0 max=4000 timC: 0, 1, 7: 0x0b-0x27-0x44 -- To view, visit https://review.coreboot.org/22776 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9986616e86560c4980ccd8e3e549af53caa15c71 Gerrit-Change-Number: 22776 Gerrit-PatchSet: 1 Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Comment-Date: Thu, 07 Dec 2017 22:22:08 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: intel/bd82x6x: Refactor IRQ routing
by build bot (Jenkins) (Code Review) 07 Dec '17

07 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22601 ) Change subject: intel/bd82x6x: Refactor IRQ routing ...................................................................... Patch Set 12: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19099/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64281/ : SUCCESS -- To view, visit https://review.coreboot.org/22601 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7229aee3817f1f4979325a2abccbb3b99ad312f6 Gerrit-Change-Number: 22601 Gerrit-PatchSet: 12 Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 Dec 2017 22:22:06 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: intel/sandybridge: Make timC training more robust.
by Tobias Diedrich (Code Review) 07 Dec '17

07 Dec '17

Tobias Diedrich has uploaded this change for review. ( https://review.coreboot.org/22776 Change subject: intel/sandybridge: Make timC training more robust. ...................................................................... intel/sandybridge: Make timC training more robust. When using native raminit with https://review.coreboot.org/#/c/22683/ I've found that timC training usually fails unless the ram is overspecced (i.e. DDR3L-1600 rated for 1.35V works most of the time with native raminit as DDR3-1333 @1.5V). Looking at the training data I've found that during timC training it is reading register values in the 0-4000 range and checking for runs of 0, but with the failing training the values don't go all the way down to 0. The solution for me has been to do a thresholing pre-pass, after which both the DDR3-1333 @1.5V and the DDR3L-1600 @1.35V work fine for me. Tested: - Intel NUC DCP847SKE - RAM slots with 2x4GB Kingston KVR1333D3S9/4G (DDR3-1333 1.5V), boots fine with native raminit @1.5V - RAM slots with 2x4GB Kingston KVR16LS11/4G (DDR3L-1600 1.35V), boots fine with native raminit @1.35V - Casual use with these settings Untested: - I haven't run any extensive longer memtest yet Change-Id: I9986616e86560c4980ccd8e3e549af53caa15c71 Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 25 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/22776/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index eaef5f7..955d44b 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1546,6 +1546,27 @@ wait_428c(channel); } +static void threshold_preprocess(int *data, int count) +{ + int min = data[0]; + int max = min; + int i; + for (i = 1; i < count; i++) { + if (min > data[i]) { + min = data[i]; + } + if (max < data[i]) { + max = data[i]; + } + } + int threshold = min/2 + max/2; + for (i = 0; i < count; i++) { + data[i] = data[i] > threshold; + } + printram("threshold=%d min=%d max=%d\n", + threshold, min, max); +} + static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank) { int timC; @@ -1577,8 +1598,10 @@ } } FOR_ALL_LANES { - struct run rn = - get_longest_zero_run(statistics[lane], MAX_TIMC + 1); + threshold_preprocess( + statistics[lane], ARRAY_SIZE(statistics[lane])); + struct run rn = get_longest_zero_run( + statistics[lane], ARRAY_SIZE(statistics[lane])); ctrl->timings[channel][slotrank].lanes[lane].timC = rn.middle; if (rn.all) { printk(BIOS_EMERG, "timC discovery failed: %d, %d, %d\n", -- To view, visit https://review.coreboot.org/22776 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9986616e86560c4980ccd8e3e549af53caa15c71 Gerrit-Change-Number: 22776 Gerrit-PatchSet: 1 Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de>

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Change in coreboot[master]: soc/amd/common: Move files to common/block
by build bot (Jenkins) (Code Review) 07 Dec '17

07 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22765 ) Change subject: soc/amd/common: Move files to common/block ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19097/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64279/ : SUCCESS -- To view, visit https://review.coreboot.org/22765 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3f965afa21124d4874d3b7bfe0f404a58b070e23 Gerrit-Change-Number: 22765 Gerrit-PatchSet: 3 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 Dec 2017 21:59:22 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/amd/common: Move files to common/block
by Richard Spiegel (Code Review) 07 Dec '17

07 Dec '17

Hello build bot (Jenkins), Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/22765 to look at the new patch set (#3). Change subject: soc/amd/common: Move files to common/block ...................................................................... soc/amd/common: Move files to common/block The following files need to be moved: amd_pci_util.c, amd_pci_util.h and spi.c. The remaining files are AGESA related and will be part of a separate issue/commit. BUG=b:62240201 TEST=Build with no error gardenia and kahlee (no code change, just folder reorg). Change-Id: I3f965afa21124d4874d3b7bfe0f404a58b070e23 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/mainboard/amd/gardenia/mainboard.c M src/mainboard/amd/gardenia/mptable.c M src/mainboard/google/kahlee/mainboard.c M src/mainboard/google/kahlee/mptable.c M src/soc/amd/common/Makefile.inc R src/soc/amd/common/block/include/amdblocks/amd_pci_util.h A src/soc/amd/common/block/pci/Kconfig A src/soc/amd/common/block/pci/Makefile.inc R src/soc/amd/common/block/pci/amd_pci_util.c A src/soc/amd/common/block/spi/Kconfig A src/soc/amd/common/block/spi/Makefile.inc R src/soc/amd/common/block/spi/spi.c M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/southbridge.c 14 files changed, 31 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/22765/3 -- To view, visit https://review.coreboot.org/22765 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I3f965afa21124d4874d3b7bfe0f404a58b070e23 Gerrit-Change-Number: 22765 Gerrit-PatchSet: 3 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit December 2017