coreboot-gerrit December 2017

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Change in coreboot[master]: soc/intel/cannonlake: Clean up UART code
by Aamir Bohra (Code Review) 08 Dec '17

08 Dec '17

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/22771 Change subject: soc/intel/cannonlake: Clean up UART code ...................................................................... soc/intel/cannonlake: Clean up UART code Clean up and move UART related code under a single uart.c file. Change-Id: I7eea910e065242689e87adac41281131674b39af Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/uart.c D src/soc/intel/cannonlake/uart_pch.c 3 files changed, 47 insertions(+), 68 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/22771/1 diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 076e76b..61318a4 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -47,7 +47,6 @@ ramstage-y += spi.c ramstage-y += systemagent.c ramstage-$(CONFIG_UART_DEBUG) += uart.c -ramstage-$(CONFIG_UART_DEBUG) += uart_pch.c ramstage-y += vr_config.c ramstage-y += sd.c @@ -55,7 +54,6 @@ smm-y += pmutil.c smm-y += smihandler.c smm-$(CONFIG_UART_DEBUG) += uart.c -smm-$(CONFIG_UART_DEBUG) += uart_pch.c postcar-y += memmap.c postcar-y += pmutil.c diff --git a/src/soc/intel/cannonlake/uart.c b/src/soc/intel/cannonlake/uart.c index 66883ec..21b6417 100644 --- a/src/soc/intel/cannonlake/uart.c +++ b/src/soc/intel/cannonlake/uart.c @@ -16,16 +16,19 @@ #define __SIMPLE_DEVICE__ #include <assert.h> +#include <cbmem.h> #include <console/uart.h> +#include <device/pci.h> #include <device/pci_def.h> #include <intelblocks/gpio.h> #include <intelblocks/lpss.h> #include <intelblocks/pcr.h> #include <intelblocks/uart.h> +#include <soc/iomap.h> +#include <soc/nvs.h> #include <soc/pch.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h> -#include <soc/iomap.h> /* Serial IO UART controller legacy mode */ #define PCR_SERIAL_IO_GPPRVRW7 0x618 @@ -48,6 +51,14 @@ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1)} /* TX */ } }; + +#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM) +uintptr_t uart_platform_base(int idx) +{ + /* We can only have one serial console at a time */ + return UART_BASE_0_ADDR(idx); +} +#endif void pch_uart_init(void) { @@ -75,10 +86,40 @@ gpio_configure_pads(p->pads, ARRAY_SIZE(p->pads)); } -#if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM) -uintptr_t uart_platform_base(int idx) +device_t pch_uart_get_debug_controller(void) { - /* We can only have one serial console at a time */ - return UART_BASE_0_ADDR(idx); + switch (CONFIG_UART_FOR_CONSOLE) { + case 0: + return PCH_DEV_UART0; + case 1: + return PCH_DEV_UART1; + case 2: + default: + return PCH_DEV_UART2; + } } -#endif + +void pch_uart_read_resources(struct device *dev) +{ + pci_dev_read_resources(dev); + + /* Set the configured UART base address for the debug port */ + if (IS_ENABLED(CONFIG_UART_DEBUG) && uart_is_debug_controller(dev)) { + struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); + /* Need to set the base and size for the resource allocator. */ + res->base = UART_BASE_0_ADDR(CONFIG_UART_FOR_CONSOLE); + res->size = UART_DEBUG_BASE_0_SIZE; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | + IORESOURCE_FIXED; + } +} + +bool pch_uart_init_debug_controller_on_resume(void) +{ + global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + + if (gnvs) + return !!gnvs->uior; + + return false; +} diff --git a/src/soc/intel/cannonlake/uart_pch.c b/src/soc/intel/cannonlake/uart_pch.c deleted file mode 100644 index 42c7a04..0000000 --- a/src/soc/intel/cannonlake/uart_pch.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. - * Copyright (C) 2017 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbmem.h> -#include <device/pci.h> -#include <intelblocks/uart.h> -#include <soc/iomap.h> -#include <soc/nvs.h> -#include <soc/pci_devs.h> - -void pch_uart_read_resources(struct device *dev) -{ - pci_dev_read_resources(dev); - - /* Set the configured UART base address for the debug port */ - if (IS_ENABLED(CONFIG_UART_DEBUG) && uart_is_debug_controller(dev)) { - struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); - /* Need to set the base and size for the resource allocator. */ - res->base = UART_BASE_0_ADDR(CONFIG_UART_FOR_CONSOLE); - res->size = UART_DEBUG_BASE_0_SIZE; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | - IORESOURCE_FIXED; - } -} - -bool pch_uart_init_debug_controller_on_resume(void) -{ - global_nvs_t *gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); - - if (gnvs) - return !!gnvs->uior; - - return false; -} - -device_t pch_uart_get_debug_controller(void) -{ - switch (CONFIG_UART_FOR_CONSOLE) { - case 0: - return PCH_DEV_UART0; - case 1: - return PCH_DEV_UART1; - case 2: - default: - return PCH_DEV_UART2; - } -} -- To view, visit https://review.coreboot.org/22771 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7eea910e065242689e87adac41281131674b39af Gerrit-Change-Number: 22771 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: mb/lenovo: add Lenovo ThinkPad X131e (Intel)
by build bot (Jenkins) (Code Review) 08 Dec '17

08 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20694 ) Change subject: mb/lenovo: add Lenovo ThinkPad X131e (Intel) ...................................................................... Patch Set 10: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19110/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64293/ : SUCCESS -- To view, visit https://review.coreboot.org/20694 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If8de3a9308997e2d57aee869023ee9a43a2db872 Gerrit-Change-Number: 20694 Gerrit-PatchSet: 10 Gerrit-Owner: James Ye <jye836(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: James Ye <jye836(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 08 Dec 2017 07:13:12 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/scarlet: support INNOLUX P097PFG panel
by Lin Huang (Code Review) 08 Dec '17

08 Dec '17

Lin Huang has posted comments on this change. ( https://review.coreboot.org/22780 ) Change subject: google/scarlet: support INNOLUX P097PFG panel ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/22780/1/src/mainboard/google/gru/mainboard.c File src/mainboard/google/gru/mainboard.c: https://review.coreboot.org/#/c/22780/1/src/mainboard/google/gru/mainboard.… PS1, Line 568: if (sku_id() == 6) { > Let's make this a switch-case statement. I think according to the current p So how to translate sku_id still do not have final decision, right? -- To view, visit https://review.coreboot.org/22780 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I43fa5d859a9a529a84c58a953b37d03953ce648a Gerrit-Change-Number: 22780 Gerrit-PatchSet: 1 Gerrit-Owner: Lin Huang <hl(a)rock-chips.com> Gerrit-Reviewer: Brian Norris <briannorris(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lin Huang <hl(a)rock-chips.com> Gerrit-Reviewer: Matthias Kaehlcke <mka(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 08 Dec 2017 03:48:07 +0000 Gerrit-HasComments: Yes

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Change in coreboot[master]: google/scarlet: support INNOLUX P097PFG panel
by Julius Werner (Code Review) 08 Dec '17

08 Dec '17

Julius Werner has posted comments on this change. ( https://review.coreboot.org/22780 ) Change subject: google/scarlet: support INNOLUX P097PFG panel ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/22780/1/src/mainboard/google/gru/mainboard.c File src/mainboard/google/gru/mainboard.c: https://review.coreboot.org/#/c/22780/1/src/mainboard/google/gru/mainboard.… PS1, Line 567: if (IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)) { Let's not add this until we have other boards that need different panels. https://review.coreboot.org/#/c/22780/1/src/mainboard/google/gru/mainboard.… PS1, Line 568: if (sku_id() == 6) { Let's make this a switch-case statement. I think according to the current plan only SKU pin 0 decides the panel, and the others are reserved for non-panel components (at least for now). So this should be: switch (sku_id()) { case 0: case 2: case 4: case 6: ...innolux... case 1: case 3: case 5: case 7: ...king... } (Although Brian just told me that apparently our SKU pins don't read the way we expected them to, so that might still change once we figure out what's going on.) -- To view, visit https://review.coreboot.org/22780 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I43fa5d859a9a529a84c58a953b37d03953ce648a Gerrit-Change-Number: 22780 Gerrit-PatchSet: 1 Gerrit-Owner: Lin Huang <hl(a)rock-chips.com> Gerrit-Reviewer: Brian Norris <briannorris(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Matthias Kaehlcke <mka(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 08 Dec 2017 03:29:38 +0000 Gerrit-HasComments: Yes

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Change in coreboot[master]: google/cyan: fix FSP memory init params
by build bot (Jenkins) (Code Review) 08 Dec '17

08 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22782 ) Change subject: google/cyan: fix FSP memory init params ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64292/ : SUCCESS -- To view, visit https://review.coreboot.org/22782 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iacfbd4bc89fa04717baf85704181d346bca2ed2f Gerrit-Change-Number: 22782 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 08 Dec 2017 03:03:38 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Add a call to gspi_early_bar_init in bootblock
by build bot (Jenkins) (Code Review) 08 Dec '17

08 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22781 ) Change subject: soc/intel/cannonlake: Add a call to gspi_early_bar_init in bootblock ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/64290/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/19108/ : SUCCESS -- To view, visit https://review.coreboot.org/22781 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I82387a76d20fb272da6271dd9e5bf2c835d5b146 Gerrit-Change-Number: 22781 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 08 Dec 2017 02:53:30 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/cyan: fix FSP memory init params
by build bot (Jenkins) (Code Review) 08 Dec '17

08 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22782 ) Change subject: google/cyan: fix FSP memory init params ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/64291/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/19109/ : SUCCESS -- To view, visit https://review.coreboot.org/22782 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iacfbd4bc89fa04717baf85704181d346bca2ed2f Gerrit-Change-Number: 22782 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 08 Dec 2017 02:48:54 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/cyan: fix FSP memory init params
by Matt DeVillier (Code Review) 08 Dec '17

08 Dec '17

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/22782 Change subject: google/cyan: fix FSP memory init params ...................................................................... google/cyan: fix FSP memory init params In the original Chromium source, PcdMemorySpdPtr is only set for cyan, but none of the other Braswell variants. When upstreamed, it was left set for all boards as it didn't appear to be problematic. In wider testing, I came across one reks board for which it caused FSP memory init to fail, so restricting the paramter to cyan only as it was originally. TEST: build/boot google/reks with Micron EDF8132A3MA-JD-F RAM, observe board now successfully boots where it did not previously. Change-Id: Iacfbd4bc89fa04717baf85704181d346bca2ed2f Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/cyan/romstage.c 1 file changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/22782/1 diff --git a/src/mainboard/google/cyan/romstage.c b/src/mainboard/google/cyan/romstage.c index c164ea4..5b4bcc0 100644 --- a/src/mainboard/google/cyan/romstage.c +++ b/src/mainboard/google/cyan/romstage.c @@ -33,11 +33,13 @@ MEMORY_INIT_UPD *memory_params) { /* Update SPD data */ - if (IS_ENABLED(CONFIG_BOARD_GOOGLE_CYAN)) + if (IS_ENABLED(CONFIG_BOARD_GOOGLE_CYAN)) { memory_params->PcdMemoryTypeEnable = MEM_DDR3; - else + memory_params->PcdMemorySpdPtr = + (u32)params->pei_data->spd_data_ch0; + } else memory_params->PcdMemoryTypeEnable = MEM_LPDDR3; - memory_params->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0; + memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config; memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config; -- To view, visit https://review.coreboot.org/22782 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iacfbd4bc89fa04717baf85704181d346bca2ed2f Gerrit-Change-Number: 22782 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: google/scarlet: support INNOLUX P097PFG panel
by build bot (Jenkins) (Code Review) 08 Dec '17

08 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22780 ) Change subject: google/scarlet: support INNOLUX P097PFG panel ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19107/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64289/ : SUCCESS -- To view, visit https://review.coreboot.org/22780 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I43fa5d859a9a529a84c58a953b37d03953ce648a Gerrit-Change-Number: 22780 Gerrit-PatchSet: 1 Gerrit-Owner: Lin Huang <hl(a)rock-chips.com> Gerrit-Reviewer: Brian Norris <briannorris(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Matthias Kaehlcke <mka(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 08 Dec 2017 02:44:40 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Add a call to gspi_early_bar_init in bootblock
by Furquan Shaikh (Code Review) 08 Dec '17

08 Dec '17

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/22781 Change subject: soc/intel/cannonlake: Add a call to gspi_early_bar_init in bootblock ...................................................................... soc/intel/cannonlake: Add a call to gspi_early_bar_init in bootblock This change adds a call to gspi_early_bar_init in bootblock to allocate a temporary BAR for any GSPI buses that are accessed before resource allocation is done in ramstage. Change-Id: I82387a76d20fb272da6271dd9e5bf2c835d5b146 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/soc/intel/cannonlake/bootblock/pch.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/22781/1 diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index 0deece6..c69fffa 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -16,6 +16,7 @@ #include <device/device.h> #include <intelblocks/fast_spi.h> +#include <intelblocks/gspi.h> #include <intelblocks/pcr.h> #include <intelblocks/rtc.h> #include <intelblocks/smbus.h> @@ -97,6 +98,7 @@ void bootblock_pch_early_init(void) { fast_spi_early_init(SPI_BASE_ADDRESS); + gspi_early_bar_init(); enable_p2sbbar(); /* * Enabling PWRM Base for accessing -- To view, visit https://review.coreboot.org/22781 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I82387a76d20fb272da6271dd9e5bf2c835d5b146 Gerrit-Change-Number: 22781 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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coreboot-gerrit December 2017