coreboot-gerrit December 2017

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Change in coreboot[master]: google/scarlet: support INNOLUX P097PFG panel
by Lin Huang (Code Review) 08 Dec '17

08 Dec '17

Lin Huang has uploaded this change for review. ( https://review.coreboot.org/22780 Change subject: google/scarlet: support INNOLUX P097PFG panel ...................................................................... google/scarlet: support INNOLUX P097PFG panel Still need to confirm this panel timing, just upload it first. Change-Id: I43fa5d859a9a529a84c58a953b37d03953ce648a Signed-off-by: Lin Huang <hl(a)rock-chips.com> --- M src/mainboard/google/gru/mainboard.c 1 file changed, 34 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/22780/1 diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c index 9a241f5..a276b17 100644 --- a/src/mainboard/google/gru/mainboard.c +++ b/src/mainboard/google/gru/mainboard.c @@ -539,12 +539,44 @@ .vspw = 2, }; +const struct mipi_panel_data inx097pfg_panel = { + .mipi_num = 2, + .format = MIPI_DSI_FMT_RGB888, + .lanes = 8, + .display_on_udelay = 120000, + .video_mode_udelay = 5000, +}; + +static const struct edid_mode inx097pfg_edid_mode = { + .name = "1536x2048@60Hz", + .pixel_clock = 220000, + .refresh = 60, + .ha = 1536, + .hbl = 224, + .hso = 100, + .hspw = 24, + .va = 2048, + .vbl = 38, + .vso = 18, + .vspw = 2, +}; + const struct mipi_panel_data *mainboard_get_mipi_mode (struct edid_mode *edid_mode) { - memcpy(edid_mode, &kd097d04_edid_mode, sizeof(struct edid_mode)); + if (IS_ENABLED(CONFIG_GRU_BASEBOARD_SCARLET)) { + if (sku_id() == 6) { + memcpy(edid_mode, &inx097pfg_edid_mode, + sizeof(struct edid_mode)); + return &inx097pfg_panel; + } - return &kd097d04_panel; + memcpy(edid_mode, &kd097d04_edid_mode, + sizeof(struct edid_mode)); + return &kd097d04_panel; + } + + return NULL; } static void mainboard_enable(device_t dev) -- To view, visit https://review.coreboot.org/22780 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I43fa5d859a9a529a84c58a953b37d03953ce648a Gerrit-Change-Number: 22780 Gerrit-PatchSet: 1 Gerrit-Owner: Lin Huang <hl(a)rock-chips.com>

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Change in coreboot[master]: mb/google/poppy/variants/nami: Implement variant_memory_params
by build bot (Jenkins) (Code Review) 08 Dec '17

08 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22779 ) Change subject: mb/google/poppy/variants/nami: Implement variant_memory_params ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19106/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64288/ : SUCCESS -- To view, visit https://review.coreboot.org/22779 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic1d0cfdb7d8b02fa0be0a4c54b20057a4c2fc3ce Gerrit-Change-Number: 22779 Gerrit-PatchSet: 3 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 08 Dec 2017 01:29:56 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/poppy/variants/nami: Implement variant_memory_params
by build bot (Jenkins) (Code Review) 08 Dec '17

08 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22779 ) Change subject: mb/google/poppy/variants/nami: Implement variant_memory_params ...................................................................... Patch Set 2: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/64287/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/19105/ : SUCCESS -- To view, visit https://review.coreboot.org/22779 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic1d0cfdb7d8b02fa0be0a4c54b20057a4c2fc3ce Gerrit-Change-Number: 22779 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 08 Dec 2017 01:23:12 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/poppy/variants/nami: Implement variant_memory_params
by Furquan Shaikh (Code Review) 08 Dec '17

08 Dec '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/22779 to look at the new patch set (#3). Change subject: mb/google/poppy/variants/nami: Implement variant_memory_params ...................................................................... mb/google/poppy/variants/nami: Implement variant_memory_params This change provides implementation of variant_memory_params for nami. Since it uses DDR4 memory, DQ-DQS mapping table is not required. Also, Rcomp resistor values are provided based on SDP v/s DDP memory. BUG=b:70188937 Change-Id: Ic1d0cfdb7d8b02fa0be0a4c54b20057a4c2fc3ce Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/mainboard/google/poppy/variants/nami/Makefile.inc A src/mainboard/google/poppy/variants/nami/memory.c 2 files changed, 52 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/22779/3 -- To view, visit https://review.coreboot.org/22779 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ic1d0cfdb7d8b02fa0be0a4c54b20057a4c2fc3ce Gerrit-Change-Number: 22779 Gerrit-PatchSet: 3 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/poppy/variants/name: Implement variant_memory_params
by build bot (Jenkins) (Code Review) 08 Dec '17

08 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22779 ) Change subject: mb/google/poppy/variants/name: Implement variant_memory_params ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/64286/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/19104/ : SUCCESS -- To view, visit https://review.coreboot.org/22779 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic1d0cfdb7d8b02fa0be0a4c54b20057a4c2fc3ce Gerrit-Change-Number: 22779 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 08 Dec 2017 01:17:50 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/poppy/variants/name: Implement variant_memory_params
by Furquan Shaikh (Code Review) 08 Dec '17

08 Dec '17

Furquan Shaikh has uploaded a new patch set (#2). ( https://review.coreboot.org/22779 ) Change subject: mb/google/poppy/variants/name: Implement variant_memory_params ...................................................................... mb/google/poppy/variants/name: Implement variant_memory_params This change provides implementation of variant_memory_params for nami. Since it uses DDR4 memory, DQ-DQS mapping table is not required. Also, Rcomp resistor values are provided based on SDP v/s DDP memory. BUG=b:70188937 Change-Id: Ic1d0cfdb7d8b02fa0be0a4c54b20057a4c2fc3ce Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/mainboard/google/poppy/variants/nami/Makefile.inc A src/mainboard/google/poppy/variants/nami/memory.c 2 files changed, 52 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/22779/2 -- To view, visit https://review.coreboot.org/22779 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ic1d0cfdb7d8b02fa0be0a4c54b20057a4c2fc3ce Gerrit-Change-Number: 22779 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: mb/google/poppy/variants/name: Implement variant_memory_params
by Furquan Shaikh (Code Review) 08 Dec '17

08 Dec '17

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/22779 Change subject: mb/google/poppy/variants/name: Implement variant_memory_params ...................................................................... mb/google/poppy/variants/name: Implement variant_memory_params This change provides implementation of variant_memory_params for nami. Since it uses DDR4 memory, DQ-DQS mapping table is not required. Also, Rcomp resistor values are provided based on SDP v/s DDP memory. BUG=b:70188937 Change-Id: Ic1d0cfdb7d8b02fa0be0a4c54b20057a4c2fc3ce Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- M src/mainboard/google/poppy/variants/nami/Makefile.inc A src/mainboard/google/poppy/variants/nami/memory.c 2 files changed, 50 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/22779/1 diff --git a/src/mainboard/google/poppy/variants/nami/Makefile.inc b/src/mainboard/google/poppy/variants/nami/Makefile.inc index 0050a3b..bbcb7d3 100644 --- a/src/mainboard/google/poppy/variants/nami/Makefile.inc +++ b/src/mainboard/google/poppy/variants/nami/Makefile.inc @@ -3,5 +3,7 @@ bootblock-y += gpio.c +romstage-y += memory.c + ramstage-y += gpio.c ramstage-y += pl2.c diff --git a/src/mainboard/google/poppy/variants/nami/memory.c b/src/mainboard/google/poppy/variants/nami/memory.c new file mode 100644 index 0000000..dec7626 --- /dev/null +++ b/src/mainboard/google/poppy/variants/nami/memory.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <string.h> + +/* Rcomp resistor */ +static const u16 rcomp_resistor_ddp[] = { 121, 81, 100 }; +static const u16 rcomp_resistor_sdp[] = { 200, 81, 100 }; + +/* Rcomp target */ +static const u16 rcomp_target[] = { 100, 40, 20, 20, 26 }; + +/* Memory ids are 1-indexed, so subtract 1 to use 0-indexed values in bitmap. */ +#define MEM_ID(x) (1 << ((x) - 1)) + +/* Bitmap to indicate which memory ids are using DDP. */ +static const uint16_t ddp_bitmap = MEM_ID(4); + +void variant_memory_params(struct memory_params *p) +{ + memset(p, 0, sizeof(*p)); + p->type = MEMORY_DDR4; + + /* Rcomp resistor values are different for SDP and DDP. */ + if (ddp_bitmap & MEM_ID(variant_memory_sku())) { + p->rcomp_resistor = rcomp_resistor_ddp; + p->rcomp_resistor_size = sizeof(rcomp_resistor_ddp); + } else { + p->rcomp_resistor = rcomp_resistor_sdp; + p->rcomp_resistor_size = sizeof(rcomp_resistor_sdp); + } + + p->rcomp_target = rcomp_target; + p->rcomp_target_size = sizeof(rcomp_target); +} -- To view, visit https://review.coreboot.org/22779 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic1d0cfdb7d8b02fa0be0a4c54b20057a4c2fc3ce Gerrit-Change-Number: 22779 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: soc/amd/stoneyridge/include: delete amd_pci_int_types.h
by build bot (Jenkins) (Code Review) 07 Dec '17

07 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22778 ) Change subject: soc/amd/stoneyridge/include: delete amd_pci_int_types.h ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19103/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64285/ : SUCCESS -- To view, visit https://review.coreboot.org/22778 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I53a9d7ebb27edbc4e136c9b17f5c709930e35223 Gerrit-Change-Number: 22778 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 Dec 2017 23:19:47 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: intel/sandybridge: Make timC training more robust.
by build bot (Jenkins) (Code Review) 07 Dec '17

07 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22776 ) Change subject: intel/sandybridge: Make timC training more robust. ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19101/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64283/ : SUCCESS -- To view, visit https://review.coreboot.org/22776 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9986616e86560c4980ccd8e3e549af53caa15c71 Gerrit-Change-Number: 22776 Gerrit-PatchSet: 2 Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 07 Dec 2017 23:16:14 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/amd/stoneyridge/include: delete amd_pci_int_types.h
by Richard Spiegel (Code Review) 07 Dec '17

07 Dec '17

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/22778 Change subject: soc/amd/stoneyridge/include: delete amd_pci_int_types.h ...................................................................... soc/amd/stoneyridge/include: delete amd_pci_int_types.h Due to review 20b8c821e4 being abandoned and review 376dc82dca being merged, file amd_pci_int_types.h became orphaned (not included by any file), while an array similar to intr_types[] (but that also includes the associated register index) was created in southbridge.c replacing the original array functionality. Remove the header amd_pci_int_types.h from the repository. BUG=b:70328428 TEST=Build kahlee with no errors. Change-Id: I53a9d7ebb27edbc4e136c9b17f5c709930e35223 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- D src/soc/amd/stoneyridge/include/amd_pci_int_types.h 1 file changed, 0 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/22778/1 diff --git a/src/soc/amd/stoneyridge/include/amd_pci_int_types.h b/src/soc/amd/stoneyridge/include/amd_pci_int_types.h deleted file mode 100644 index 08bdc10..0000000 --- a/src/soc/amd/stoneyridge/include/amd_pci_int_types.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __AMD_PCI_INT_TYPES_H__ -#define __AMD_PCI_INT_TYPES_H__ - -const char *intr_types[] = { - [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", - "INTF#\t", "INTG#\t", "INTH#\t", - [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", - "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", - [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", - "PerMon\t", "SD\t\t", - [0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", - "IMC INT4\t", "IMC INT5\t", - [0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", - "Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC", - [0x7f] = "RSVD\t", - [0x40] = "IDE\t", "SATA\t", - [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t", - [0x62] = "GPIO\t", - [0x70] = "I2C0\t", "I2C1\t", "I2C2\t", "I2C3\t", "UART0\t", "UART1\t", -}; - -#endif /* __AMD_PCI_INT_TYPES_H__ */ -- To view, visit https://review.coreboot.org/22778 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I53a9d7ebb27edbc4e136c9b17f5c709930e35223 Gerrit-Change-Number: 22778 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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coreboot-gerrit December 2017