coreboot-gerrit November 2017

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Change in coreboot[master]: sb/intel/common: Add SOUTHBRIDGE_INTEL_COMMON_SPI to include spi code
by build bot (Jenkins) (Code Review) 03 Nov '17

03 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21674 ) Change subject: sb/intel/common: Add SOUTHBRIDGE_INTEL_COMMON_SPI to include spi code ...................................................................... Patch Set 7: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17854/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/62876/ : SUCCESS -- To view, visit https://review.coreboot.org/21674 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I970408e5656c0e8812b8609e2cc10d0bc8d8f6f2 Gerrit-Change-Number: 21674 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 03 Nov 2017 11:46:06 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/x4x: Use SPI flash to cache raminit results
by build bot (Jenkins) (Code Review) 03 Nov '17

03 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21677 ) Change subject: nb/intel/x4x: Use SPI flash to cache raminit results ...................................................................... Patch Set 8: No Builds Executed -- To view, visit https://review.coreboot.org/21677 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I042dc5c52615d40781d9ef7ecd657ad0bf3ed08f Gerrit-Change-Number: 21677 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 03 Nov 2017 11:38:20 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/intel/cormotant: copying harcuvar board and adapting
by build bot (Jenkins) (Code Review) 03 Nov '17

03 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22308 ) Change subject: mainboard/intel/cormotant: copying harcuvar board and adapting ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/62870/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/17848/ : SUCCESS -- To view, visit https://review.coreboot.org/22308 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8484a0d0902339692bf77ab73a65a0065a106dd2 Gerrit-Change-Number: 22308 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 03 Nov 2017 11:14:35 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/intel/harcuvar: updating to set the HSIO lines configuration
by build bot (Jenkins) (Code Review) 03 Nov '17

03 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22310 ) Change subject: mainboard/intel/harcuvar: updating to set the HSIO lines configuration ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17849/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/62871/ : SUCCESS -- To view, visit https://review.coreboot.org/22310 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifc3423ff983fb631edcab087d04742937b25ef86 Gerrit-Change-Number: 22310 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 03 Nov 2017 11:13:14 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/denverton_ns: re-factoring hsio configuration
by build bot (Jenkins) (Code Review) 03 Nov '17

03 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22309 ) Change subject: soc/intel/denverton_ns: re-factoring hsio configuration ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17851/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/62873/ : SUCCESS -- To view, visit https://review.coreboot.org/22309 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iec65472207309eae878d14eef5bc644b80fdbb1d Gerrit-Change-Number: 22309 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 03 Nov 2017 11:09:37 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/intel/cormorant: updating to set the HSIO lines configuration
by build bot (Jenkins) (Code Review) 03 Nov '17

03 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22311 ) Change subject: mainboard/intel/cormorant: updating to set the HSIO lines configuration ...................................................................... Patch Set 2: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/62874/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/17852/ : SUCCESS -- To view, visit https://review.coreboot.org/22311 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id802ba6cd14828ffba8221eadd7af018c0bf1d6c Gerrit-Change-Number: 22311 Gerrit-PatchSet: 2 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 03 Nov 2017 11:06:29 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/intel/cormorant: updating to set the HSIO lines configuration
by build bot (Jenkins) (Code Review) 03 Nov '17

03 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22311 ) Change subject: mainboard/intel/cormorant: updating to set the HSIO lines configuration ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/62872/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/17850/ : SUCCESS -- To view, visit https://review.coreboot.org/22311 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id802ba6cd14828ffba8221eadd7af018c0bf1d6c Gerrit-Change-Number: 22311 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 03 Nov 2017 10:57:07 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/intel/cormorant: updating to set the HSIO lines configuration
by Julien Viard de Galbert (Code Review) 03 Nov '17

03 Nov '17

Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/22311 Change subject: mainboard/intel/cormorant: updating to set the HSIO lines configuration ...................................................................... mainboard/intel/cormorant: updating to set the HSIO lines configuration Change-Id: Id802ba6cd14828ffba8221eadd7af018c0bf1d6c Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/mainboard/intel/cormorant/Makefile.inc A src/mainboard/intel/cormorant/hsio.c 2 files changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/22311/1 diff --git a/src/mainboard/intel/cormorant/Makefile.inc b/src/mainboard/intel/cormorant/Makefile.inc index ba88569..3dda7c4 100644 --- a/src/mainboard/intel/cormorant/Makefile.inc +++ b/src/mainboard/intel/cormorant/Makefile.inc @@ -16,9 +16,11 @@ subdirs-$(CONFIG_ENABLE_FSP_MEMORY_DOWN) += spd romstage-y += boardid.c +romstage-y += hsio.c ramstage-y += ramstage.c ramstage-y += boardid.c +ramstage-y += hsio.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c diff --git a/src/mainboard/intel/cormorant/hsio.c b/src/mainboard/intel/cormorant/hsio.c new file mode 100644 index 0000000..86c6788 --- /dev/null +++ b/src/mainboard/intel/cormorant/hsio.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2017 Online SAS + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cormorant_boardid.h> +#include <hsio.h> +#include <soc/fiamux.h> + +size_t mainboard_get_hsio_config(BL_HSIO_INFORMATION **p_hsio_config) +{ + uint8_t boardid = board_id(); + size_t num; + switch (boardid) { + case BoardIdCormorant: + num = ARRAY_SIZE(cormorant_hsio_config); + (*p_hsio_config) = (BL_HSIO_INFORMATION *)cormorant_hsio_config; + break; + default: + num = 0; + (*p_hsio_config) = NULL; + break; + } + return num; +} -- To view, visit https://review.coreboot.org/22311 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id802ba6cd14828ffba8221eadd7af018c0bf1d6c Gerrit-Change-Number: 22311 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net>

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Change in coreboot[master]: soc/intel/denverton_ns: re-factoring hsio configuration
by Julien Viard de Galbert (Code Review) 03 Nov '17

03 Nov '17

Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/22309 Change subject: soc/intel/denverton_ns: re-factoring hsio configuration ...................................................................... soc/intel/denverton_ns: re-factoring hsio configuration The main goal is to allow configuring the HSIO lines from the mainboard code. Also share the code for both romstage and ramstage. Remove de explicit dependency on the harcuvar mainboard. Change-Id: Iec65472207309eae878d14eef5bc644b80fdbb1d Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/soc/intel/denverton_ns/chip.c M src/soc/intel/denverton_ns/fiamux.c M src/soc/intel/denverton_ns/include/soc/fiamux.h M src/soc/intel/denverton_ns/romstage.c 4 files changed, 10 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/22309/1 diff --git a/src/soc/intel/denverton_ns/chip.c b/src/soc/intel/denverton_ns/chip.c index 9547bec..813570e 100644 --- a/src/soc/intel/denverton_ns/chip.c +++ b/src/soc/intel/denverton_ns/chip.c @@ -31,8 +31,6 @@ #include <soc/ramstage.h> #include <soc/fiamux.h> #include <spi-generic.h> -#include <hsio.h> -#include <harcuvar_boardid.h> static void pci_domain_set_resources(device_t dev) { @@ -74,7 +72,6 @@ { size_t num; uint16_t supported_hsio_lanes; - uint8_t boardid = board_id(); BL_HSIO_INFORMATION *hsio_config; BL_FIA_MUX_CONFIG_HOB *fiamux_hob_data = get_fiamux_hob_data(); @@ -82,16 +79,7 @@ supported_hsio_lanes = (uint16_t)fiamux_hob_data->FiaMuxConfig.SkuNumLanesAllowed; - switch (boardid) { - case BoardIdHarcuvar: - num = ARRAY_SIZE(harcuvar_hsio_config); - hsio_config = (BL_HSIO_INFORMATION *)harcuvar_hsio_config; - break; - default: - num = 0; - hsio_config = NULL; - break; - } + num = mainboard_get_hsio_config(&hsio_config); if (get_fiamux_hsio_info(supported_hsio_lanes, num, &hsio_config)) die("HSIO Configuration is invalid, please correct it!"); diff --git a/src/soc/intel/denverton_ns/fiamux.c b/src/soc/intel/denverton_ns/fiamux.c index 282ba03..0cee5cd 100644 --- a/src/soc/intel/denverton_ns/fiamux.c +++ b/src/soc/intel/denverton_ns/fiamux.c @@ -138,3 +138,9 @@ return fiamux_hob_data; } + +__attribute__((weak)) size_t mainboard_get_hsio_config(BL_HSIO_INFORMATION **p_hsio_config) +{ + *p_hsio_config = NULL; + return 0; +} diff --git a/src/soc/intel/denverton_ns/include/soc/fiamux.h b/src/soc/intel/denverton_ns/include/soc/fiamux.h index e8aaf65..1ba57c3 100644 --- a/src/soc/intel/denverton_ns/include/soc/fiamux.h +++ b/src/soc/intel/denverton_ns/include/soc/fiamux.h @@ -24,4 +24,6 @@ BL_FIA_MUX_CONFIG_HOB *get_fiamux_hob_data(void); void print_fiamux_config_hob(BL_FIA_MUX_CONFIG_HOB *fiamux_hob_data); +size_t mainboard_get_hsio_config(BL_HSIO_INFORMATION **p_hsio_config); + #endif // _MAINBOARD_HARCUVAR_FIAMUX_H diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 512d8cc..4403b68 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -16,8 +16,6 @@ #include <cbmem.h> #include <console/console.h> #include <cpu/x86/mtrr.h> -#include <harcuvar_boardid.h> -#include <hsio.h> #include <reset.h> #include <soc/fiamux.h> #include <soc/iomap.h> @@ -237,7 +235,6 @@ FSPM_UPD *mupd = container_of(m_cfg, FSPM_UPD, FspmConfig); size_t num; uint16_t supported_hsio_lanes; - uint8_t boardid = board_id(); BL_HSIO_INFORMATION *hsio_config; /* Set the parameters for MemoryInit */ @@ -250,17 +247,7 @@ /* Assume the validating silicon has max lanes. */ supported_hsio_lanes = BL_ME_FIA_MUX_LANE_NUM_MAX; - switch (boardid) { - case BoardIdHarcuvar: - num = ARRAY_SIZE(harcuvar_hsio_config); - hsio_config = - (BL_HSIO_INFORMATION *)harcuvar_hsio_config; - break; - default: - num = 0; - hsio_config = NULL; - break; - } + num = mainboard_get_hsio_config(&hsio_config); if (get_fiamux_hsio_info(supported_hsio_lanes, num, &hsio_config)) -- To view, visit https://review.coreboot.org/22309 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iec65472207309eae878d14eef5bc644b80fdbb1d Gerrit-Change-Number: 22309 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net>

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Change in coreboot[master]: mainboard/intel/harcuvar: updating to set the HSIO lines configuration
by Julien Viard de Galbert (Code Review) 03 Nov '17

03 Nov '17

Julien Viard de Galbert has uploaded this change for review. ( https://review.coreboot.org/22310 Change subject: mainboard/intel/harcuvar: updating to set the HSIO lines configuration ...................................................................... mainboard/intel/harcuvar: updating to set the HSIO lines configuration Change-Id: Ifc3423ff983fb631edcab087d04742937b25ef86 Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/mainboard/intel/harcuvar/Makefile.inc A src/mainboard/intel/harcuvar/hsio.c 2 files changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/22310/1 diff --git a/src/mainboard/intel/harcuvar/Makefile.inc b/src/mainboard/intel/harcuvar/Makefile.inc index ba88569..3dda7c4 100644 --- a/src/mainboard/intel/harcuvar/Makefile.inc +++ b/src/mainboard/intel/harcuvar/Makefile.inc @@ -16,9 +16,11 @@ subdirs-$(CONFIG_ENABLE_FSP_MEMORY_DOWN) += spd romstage-y += boardid.c +romstage-y += hsio.c ramstage-y += ramstage.c ramstage-y += boardid.c +ramstage-y += hsio.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_tables.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c diff --git a/src/mainboard/intel/harcuvar/hsio.c b/src/mainboard/intel/harcuvar/hsio.c new file mode 100644 index 0000000..ac9056b --- /dev/null +++ b/src/mainboard/intel/harcuvar/hsio.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corporation. + * Copyright (C) 2017 Online SAS + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <harcuvar_boardid.h> +#include <hsio.h> +#include <soc/fiamux.h> + +size_t mainboard_get_hsio_config(BL_HSIO_INFORMATION **p_hsio_config) +{ + uint8_t boardid = board_id(); + size_t num; + switch (boardid) { + case BoardIdHarcuvar: + num = ARRAY_SIZE(harcuvar_hsio_config); + (*p_hsio_config) = (BL_HSIO_INFORMATION *)harcuvar_hsio_config; + break; + default: + num = 0; + (*p_hsio_config) = NULL; + break; + } + return num; +} -- To view, visit https://review.coreboot.org/22310 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifc3423ff983fb631edcab087d04742937b25ef86 Gerrit-Change-Number: 22310 Gerrit-PatchSet: 1 Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert(a)online.net>

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coreboot-gerrit November 2017