coreboot-gerrit November 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/cannonlake: provide common LPDDR4 memory init
by build bot (Jenkins) (Code Review) 03 Nov '17

03 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22204 ) Change subject: soc/intel/cannonlake: provide common LPDDR4 memory init ...................................................................... Patch Set 13: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17891/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/62928/ : SUCCESS -- To view, visit https://review.coreboot.org/22204 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4a43ea121e663b866eaca3930eca61f30bb52834 Gerrit-Change-Number: 22204 Gerrit-PatchSet: 13 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Anonymous Coward #1001775 Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Maximilian Schander <coreboot(a)mimoja.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 03 Nov 2017 22:28:35 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: gru: Fix and export SPK_PA_EN GPIO for Scarlet
by Julius Werner (Code Review) 03 Nov '17

03 Nov '17

Hello Philip Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/22323 to review the following change. Change subject: gru: Fix and export SPK_PA_EN GPIO for Scarlet ...................................................................... gru: Fix and export SPK_PA_EN GPIO for Scarlet On older Grus, GPIO0_A2 was an audio voltage rail enable line. On Scarlet, we instead moved the audio codec enable (previously on GPIO1_A2) there. Unfortunately the code still had some hardcoded leftovers that were overlooked in the initial port and make our speakers smell weird. This patch fixes the incorrect GPIO settings and adds the speaker enable pin to the GPIOs passed through the coreboot table, so that depthcharge doesn't have to keep its own definition of the pin which may go out of sync. Change-Id: I1ac70ee47ebf04b8b92ff17a46cbf5d839421a61 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/mainboard/google/gru/board.h M src/mainboard/google/gru/chromeos.c M src/mainboard/google/gru/mainboard.c 3 files changed, 6 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/22323/1 diff --git a/src/mainboard/google/gru/board.h b/src/mainboard/google/gru/board.h index 7237d46..f95db57 100644 --- a/src/mainboard/google/gru/board.h +++ b/src/mainboard/google/gru/board.h @@ -31,6 +31,7 @@ #define GPIO_P15V_EN dead_code_t(gpio_t, "PP1500 doesn't exist on Scarlet") #define GPIO_P18V_AUDIO_PWREN dead_code_t(gpio_t, "doesn't exist on Scarlet") #define GPIO_P30V_EN GPIO(0, B, 1) +#define GPIO_SPK_PA_EN GPIO(0, A, 2) #define GPIO_TP_RST_L dead_code_t(gpio_t, "don't need TP_RST_L on Scarlet") #define GPIO_TPM_IRQ GPIO(1, C, 1) #define GPIO_WP GPIO(0, B, 5) @@ -41,6 +42,7 @@ #define GPIO_P15V_EN GPIO(0, B, 2) #define GPIO_P18V_AUDIO_PWREN GPIO(0, A, 2) #define GPIO_P30V_EN GPIO(0, B, 4) +#define GPIO_SPK_PA_EN GPIO(1, A, 2) #define GPIO_TP_RST_L GPIO(3, B, 4) /* may also be an I2C pull-up enable */ #define GPIO_TPM_IRQ GPIO(0, A, 5) #define GPIO_WP GPIO(1, C, 2) diff --git a/src/mainboard/google/gru/chromeos.c b/src/mainboard/google/gru/chromeos.c index b28e9fc..0dd03ea 100644 --- a/src/mainboard/google/gru/chromeos.c +++ b/src/mainboard/google/gru/chromeos.c @@ -36,6 +36,7 @@ {GPIO_EC_IN_RW.raw, ACTIVE_HIGH, -1, "EC in RW"}, {GPIO_EC_IRQ.raw, ACTIVE_LOW, -1, "EC interrupt"}, {GPIO_RESET.raw, ACTIVE_HIGH, -1, "reset"}, + {GPIO_SPK_PA_EN.raw, ACTIVE_HIGH, -1, "speaker enable"}, #if IS_ENABLED(CONFIG_GRU_HAS_TPM2) {GPIO_TPM_IRQ.raw, ACTIVE_HIGH, -1, "TPM interrupt"}, #endif diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c index 43fbb71..3721ce8 100644 --- a/src/mainboard/google/gru/mainboard.c +++ b/src/mainboard/google/gru/mainboard.c @@ -226,11 +226,9 @@ /* AUDIO IO domain 1.8V voltage selection */ write32(&rk3399_grf->io_vsel, RK_SETBITS(1 << 1)); - /* CPU1_P1.8V_AUDIO_PWREN for P1.8_AUDIO */ - gpio_output(GPIO(0, A, 2), 1); - - /* set CPU1_SPK_PA_EN output */ - gpio_output(GPIO(1, A, 2), 0); + if (!IS_ENABLED(CONFIG_BOARD_GOOGLE_SCARLET)) + gpio_output(GPIO_P18V_AUDIO_PWREN, 1); + gpio_output(GPIO_SPK_PA_EN, 0); rkclk_configure_i2s(12288000); } -- To view, visit https://review.coreboot.org/22323 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1ac70ee47ebf04b8b92ff17a46cbf5d839421a61 Gerrit-Change-Number: 22323 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)chromium.org>

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Change in coreboot[master]: endian: Fix bebitenc() to actually encode big-endian
by build bot (Jenkins) (Code Review) 03 Nov '17

03 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22322 ) Change subject: endian: Fix bebitenc() to actually encode big-endian ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17890/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/62927/ : SUCCESS -- To view, visit https://review.coreboot.org/22322 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5c2da3a196334844ce23468bd0124bbe2f378c46 Gerrit-Change-Number: 22322 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 03 Nov 2017 21:21:36 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: endian: Loop in the right direction in bebitenc()
by build bot (Jenkins) (Code Review) 03 Nov '17

03 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22322 ) Change subject: endian: Loop in the right direction in bebitenc() ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17889/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/62926/ : SUCCESS -- To view, visit https://review.coreboot.org/22322 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5c2da3a196334844ce23468bd0124bbe2f378c46 Gerrit-Change-Number: 22322 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Edward O'Callaghan <edward.ocallaghan(a)koparo.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 03 Nov 2017 21:05:11 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: spi/tpm.c do not waste time on wake pulses unless necessary
by build bot (Jenkins) (Code Review) 03 Nov '17

03 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22321 ) Change subject: spi/tpm.c do not waste time on wake pulses unless necessary ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/62925/ : SUCCESS -- To view, visit https://review.coreboot.org/22321 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id8def1470ba3eab533075b9e7180f8a58e0b00b6 Gerrit-Change-Number: 22321 Gerrit-PatchSet: 2 Gerrit-Owner: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 03 Nov 2017 20:45:30 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: spi/tpm.c do not waste time on wake pulses unless necessary
by Vadim Bendebury (Code Review) 03 Nov '17

03 Nov '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/22321 to look at the new patch set (#2). Change subject: spi/tpm.c do not waste time on wake pulses unless necessary ...................................................................... spi/tpm.c do not waste time on wake pulses unless necessary The Cr50 secure chip implementation is guaranteed not to fall asleep for 1 second after any SPI slave activity. Let's not waste time on the wake up ping when it is not necessary. BRANCH=cr50 BUG=b:68012381 TEST=using a protocol analyzer verified that the wake pulses are generated only when the new coreboot stage or depthcharge start, not on every SPI slave transaction. Change-Id: Id8def1470ba3eab533075b9e7180f8a58e0b00b6 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- M src/drivers/spi/tpm/tpm.c 1 file changed, 28 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/22321/2 -- To view, visit https://review.coreboot.org/22321 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Id8def1470ba3eab533075b9e7180f8a58e0b00b6 Gerrit-Change-Number: 22321 Gerrit-PatchSet: 2 Gerrit-Owner: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: spi/tpm.c do not waste time on wake pulses unless necessary
by build bot (Jenkins) (Code Review) 03 Nov '17

03 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22321 ) Change subject: spi/tpm.c do not waste time on wake pulses unless necessary ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/62924/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/17888/ : SUCCESS -- To view, visit https://review.coreboot.org/22321 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id8def1470ba3eab533075b9e7180f8a58e0b00b6 Gerrit-Change-Number: 22321 Gerrit-PatchSet: 1 Gerrit-Owner: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 03 Nov 2017 20:35:50 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: spi/tpm.c do not waste time on wake pulses unless necessary
by Vadim Bendebury (Code Review) 03 Nov '17

03 Nov '17

Vadim Bendebury has uploaded this change for review. ( https://review.coreboot.org/22321 Change subject: spi/tpm.c do not waste time on wake pulses unless necessary ...................................................................... spi/tpm.c do not waste time on wake pulses unless necessary The Cr50 secure chip implementation is guaranteed not to fall asleep for 1 second after any SPI slave activity. Let's not waste time on the wake up ping when it is not necessary. BRANCH=cr50 BUG=b:68012381 TEST=using a protocol analyzer verified that the wake pulses are generated only when the new Coreboot stage or Depthcharge start, not on every SPI slave transaction. Change-Id: Id8def1470ba3eab533075b9e7180f8a58e0b00b6 Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> --- M src/drivers/spi/tpm/tpm.c 1 file changed, 28 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/22321/1 diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c index 58bf842..c47b807 100644 --- a/src/drivers/spi/tpm/tpm.c +++ b/src/drivers/spi/tpm/tpm.c @@ -109,6 +109,9 @@ struct stopwatch sw; static int tpm_sync_needed CAR_GLOBAL; struct spi_slave *spi_slave = car_get_var_ptr(&g_spi_slave); + int wakeup_needed = 1; + static long prev_us CAR_GLOBAL; + struct mono_time mt; /* Wait for tpm to finish previous transaction if needed */ if (car_get_var(tpm_sync_needed)) @@ -116,11 +119,31 @@ else car_set_var(tpm_sync_needed, 1); - /* Try to wake cr50 if it is asleep. */ - spi_claim_bus(spi_slave); - udelay(1); - spi_release_bus(spi_slave); - udelay(100); + if (IS_ENABLED(CONFIG_HAVE_MONOTONIC_TIMER)) { + timer_monotonic_get(&mt); + + if (car_get_var(prev_us)) + /* + * If there is a timestamp, check if SPI slave timeout + * has expired. + * + * The Cr50 on H1 does not go to sleep for 1 second + * after any SPI slave activity, let's be conservative + * and limit the window to 900 ms. + */ + if (mt.microseconds < + (car_get_var(prev_us) + 900 * 1000)) + wakeup_needed = 0; + car_set_var(prev_us, mt.microseconds); + } + + if (wakeup_needed) { + /* Just in case Cr50 is asleep. */ + spi_claim_bus(spi_slave); + udelay(1); + spi_release_bus(spi_slave); + udelay(100); + } /* * The first byte of the frame header encodes the transaction type -- To view, visit https://review.coreboot.org/22321 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id8def1470ba3eab533075b9e7180f8a58e0b00b6 Gerrit-Change-Number: 22321 Gerrit-PatchSet: 1 Gerrit-Owner: Vadim Bendebury <vbendeb(a)chromium.org>

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Change in coreboot[master]: sb/intel/common: Add SOUTHBRIDGE_INTEL_COMMON_SPI
by build bot (Jenkins) (Code Review) 03 Nov '17

03 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21674 ) Change subject: sb/intel/common: Add SOUTHBRIDGE_INTEL_COMMON_SPI ...................................................................... Patch Set 8: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/62905/ : SUCCESS -- To view, visit https://review.coreboot.org/21674 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I970408e5656c0e8812b8609e2cc10d0bc8d8f6f2 Gerrit-Change-Number: 21674 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 03 Nov 2017 18:02:33 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Turn off XTAL Disqualification for XTAL Shutdown
by build bot (Jenkins) (Code Review) 03 Nov '17

03 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22237 ) Change subject: soc/intel/skylake: Turn off XTAL Disqualification for XTAL Shutdown ...................................................................... Patch Set 6: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17869/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/62904/ : SUCCESS -- To view, visit https://review.coreboot.org/22237 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8abc6e9b88b3bc25cf865824aa14b292ac0524ef Gerrit-Change-Number: 22237 Gerrit-PatchSet: 6 Gerrit-Owner: Roy Mingi Park <roy.mingi.park(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rajneesh Bhardwaj <rajneesh.bhardwaj(a)intel.corp-partner.google.com> Gerrit-Reviewer: Roy Mingi Park <roy.mingi.park(a)intel.com> Gerrit-Reviewer: Rushikesh S Kadam <rushikesh.s.kadam(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 03 Nov 2017 16:41:50 +0000 Gerrit-HasComments: No

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coreboot-gerrit November 2017