coreboot-gerrit November 2017

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Change in coreboot[master]: nb/intel/x4x: Refactor setting default dll settings
by Arthur Heymans (Code Review) 04 Nov '17

04 Nov '17

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/22327 Change subject: nb/intel/x4x: Refactor setting default dll settings ...................................................................... nb/intel/x4x: Refactor setting default dll settings This patch pushes these large default delay tables to a different file to reduce cluttering up the actual raminit source. While doing so it also uses more but smaller arrays and also adds the respective default delays for DDR3 which are not yet used in this patch. This patch add a function to set the read DQS delays instead of just programming magic values. (This will prove useful for DQS read training) To prepare for adding trainings on the delay values it stores these default delays in the sysinfo struct to program those. Later when trainings are implemented those trained values will be used instead of these safe default values, via using the cached sysinfo in 'mrc' cache. Change-Id: I0e3676e06586ea84fc0729469946dbc9a8225934 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/Makefile.inc M src/northbridge/intel/x4x/raminit_ddr2.c A src/northbridge/intel/x4x/raminit_tables.c M src/northbridge/intel/x4x/x4x.h 4 files changed, 403 insertions(+), 106 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/22327/1 diff --git a/src/northbridge/intel/x4x/Makefile.inc b/src/northbridge/intel/x4x/Makefile.inc index d910f92..0e5a4a3 100644 --- a/src/northbridge/intel/x4x/Makefile.inc +++ b/src/northbridge/intel/x4x/Makefile.inc @@ -21,6 +21,7 @@ romstage-y += raminit_ddr2.c romstage-y += ram_calc.c romstage-y += rcven.c +romstage-y += raminit_tables.c ramstage-y += acpi.c ramstage-y += ram_calc.c diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index 4958226..c427f63 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -26,6 +26,7 @@ #else #include <southbridge/intel/i82801jx/i82801jx.h> #endif +#include <string.h> #include "iomap.h" #include "x4x.h" @@ -344,6 +345,24 @@ } } +static void rt_set_dqs(u8 channel, u8 lane, u8 rank, + struct rt_dqs_setting *dqs_setting) +{ + u8 saved_tap = MCHBAR16(0x540 + 0x400 * channel + lane * 4); + u8 saved_pi = MCHBAR16(0x542 + 0x400 * channel + lane * 4); + printk(RAM_SPEW, "RT DQS: ch%d, L%d, %d.%d\n", channel, lane, + dqs_setting->tap, + dqs_setting->pi); + + saved_tap &= ~(0xf << (rank * 4)); + saved_tap |= dqs_setting->tap << (rank * 4); + MCHBAR16(0x540 + 0x400 * channel + lane * 4) = saved_tap; + + saved_pi &= ~(0x7 << (rank * 3)); + saved_pi |= dqs_setting->pi << (rank * 3); + MCHBAR16(0x542 + 0x400 * channel + lane * 4) = saved_pi; +} + static void timings_ddr2(struct sysinfo *s) { u8 i; @@ -574,7 +593,6 @@ u8 i, j, r, reg8, clk, async = 0; u16 reg16 = 0; u32 reg32 = 0; - u8 lane; MCHBAR16(0x180) = (MCHBAR16(0x180) & ~0x7e06) | 0xc04; MCHBAR16(0x182) = (MCHBAR16(0x182) & ~0x3ff) | 0xc8; @@ -660,60 +678,6 @@ MCHBAR8(0x1a4) = MCHBAR8(0x1a4) | 0x40; MCHBAR16(0x5f0) = (MCHBAR16(0x5f0) & ~0x400) | 0x400; - static const struct dll_setting dll_setting_667[23] = { - // tap pi db delay - {13, 0, 1, 0, 0}, - {4, 1, 0, 0, 0}, - {13, 0, 1, 0, 0}, - {4, 5, 0, 0, 0}, - {4, 1, 0, 0, 0}, - {4, 1, 0, 0, 0}, - {4, 1, 0, 0, 0}, - {1, 5, 1, 1, 1}, - {1, 6, 1, 1, 1}, - {2, 0, 1, 1, 1}, - {2, 1, 1, 1, 1}, - {2, 1, 1, 1, 1}, - {14, 6, 1, 0, 0}, - {14, 3, 1, 0, 0}, - {14, 0, 1, 0, 0}, - {9, 0, 0, 0, 1}, - {9, 1, 0, 0, 1}, - {9, 2, 0, 0, 1}, - {9, 2, 0, 0, 1}, - {9, 1, 0, 0, 1}, - {6, 4, 0, 0, 1}, - {6, 2, 0, 0, 1}, - {5, 4, 0, 0, 1} - }; - - static const struct dll_setting dll_setting_800[23] = { - // tap pi db delay - {11, 5, 1, 0, 0}, - {0, 5, 1, 1, 0}, - {11, 5, 1, 0, 0}, - {1, 4, 1, 1, 0}, - {0, 5, 1, 1, 0}, - {0, 5, 1, 1, 0}, - {0, 5, 1, 1, 0}, - {2, 5, 1, 1, 1}, - {2, 6, 1, 1, 1}, - {3, 0, 1, 1, 1}, - {3, 0, 1, 1, 1}, - {3, 3, 1, 1, 1}, - {2, 0, 1, 1, 1}, - {1, 3, 1, 1, 1}, - {0, 3, 1, 1, 1}, - {9, 3, 0, 0, 1}, - {9, 4, 0, 0, 1}, - {9, 5, 0, 0, 1}, - {9, 6, 0, 0, 1}, - {10, 0, 0, 0, 1}, - {8, 1, 0, 0, 1}, - {7, 5, 0, 0, 1}, - {6, 2, 0, 0, 1} - }; - FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { MCHBAR16(0x400*i + 0x5f0) = (MCHBAR16(0x400*i + 0x5f0) & ~0x3fc) | 0x3fc; MCHBAR32(0x400*i + 0x5fc) = MCHBAR32(0x400*i + 0x5fc) & ~0xcccccccc; @@ -723,21 +687,21 @@ FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz) { - clkset0(i, &dll_setting_667[CLKSET0]); - clkset1(i, &dll_setting_667[CLKSET1]); - ctrlset0(i, &dll_setting_667[CTRL0]); - ctrlset1(i, &dll_setting_667[CTRL1]); - ctrlset2(i, &dll_setting_667[CTRL2]); - ctrlset3(i, &dll_setting_667[CTRL3]); - cmdset(i, &dll_setting_667[CMD]); + clkset0(i, &default_ddr2_667_ctrl[CLKSET0]); + clkset1(i, &default_ddr2_667_ctrl[CLKSET1]); + ctrlset0(i, &default_ddr2_667_ctrl[CTRL0]); + ctrlset1(i, &default_ddr2_667_ctrl[CTRL1]); + ctrlset2(i, &default_ddr2_667_ctrl[CTRL2]); + ctrlset3(i, &default_ddr2_667_ctrl[CTRL3]); + cmdset(i, &default_ddr2_667_ctrl[CMD]); } else { - clkset0(i, &dll_setting_800[CLKSET0]); - clkset1(i, &dll_setting_800[CLKSET1]); - ctrlset0(i, &dll_setting_800[CTRL0]); - ctrlset1(i, &dll_setting_800[CTRL1]); - ctrlset2(i, &dll_setting_800[CTRL2]); - ctrlset3(i, &dll_setting_800[CTRL3]); - cmdset(i, &dll_setting_800[CMD]); + clkset0(i, &default_ddr2_800_ctrl[CLKSET0]); + clkset1(i, &default_ddr2_800_ctrl[CLKSET1]); + ctrlset0(i, &default_ddr2_800_ctrl[CTRL0]); + ctrlset1(i, &default_ddr2_800_ctrl[CTRL1]); + ctrlset2(i, &default_ddr2_800_ctrl[CTRL2]); + ctrlset3(i, &default_ddr2_800_ctrl[CTRL3]); + cmdset(i, &default_ddr2_800_ctrl[CMD]); } } @@ -837,32 +801,82 @@ if (s->selected_timings.mem_clk == MEM_CLOCK_1333MHz) MCHBAR8(0x18c) = MCHBAR8(0x18c) | 1; +} - // Program DQ/DQS dll settings - reg32 = 0; - FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { +static void select_default_dq_dqs_settings(struct sysinfo *s) +{ + int ch, lane, rank; + + FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { for (lane = 0; lane < 8; lane++) { - if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz) - reg32 = 0x06db7777; - else if (s->selected_timings.mem_clk == MEM_CLOCK_800MHz) - reg32 = 0x00007777; - MCHBAR32(0x400*i + 0x540 + lane*4) = - (MCHBAR32(0x400*i + 0x540 + lane*4) & 0x0fffffff) | - reg32; + FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, ch, rank) { + switch (s->selected_timings.mem_clk) { + case MEM_CLOCK_667MHz: + s->rt_dqs[ch][rank][lane].tap = 7; + s->rt_dqs[ch][rank][lane].pi = 2; + break; + case MEM_CLOCK_800MHz: + if (s->spd_type == DDR2) { + s->rt_dqs[ch][rank][lane].tap = 7; + s->rt_dqs[ch][rank][lane].pi = 0; + } else { /* DDR3 */ + s->rt_dqs[ch][rank][lane].tap = 6; + s->rt_dqs[ch][rank][lane].pi = 2; + } + break; + case MEM_CLOCK_1066MHz: + s->rt_dqs[ch][rank][lane].tap = 5; + s->rt_dqs[ch][rank][lane].pi = 2; + break; + case MEM_CLOCK_1333MHz: + s->rt_dqs[ch][rank][lane].tap = 7; + s->rt_dqs[ch][rank][lane].pi = 0; + break; + default: /* not supported */ + break; + } + } + switch (s->selected_timings.mem_clk) { + case MEM_CLOCK_667MHz: + memcpy(s->dqs_settings[ch], + default_ddr2_667_dqs, + sizeof(s->dqs_settings[ch])); + memcpy(s->dq_settings[ch], + default_ddr2_667_dq, + sizeof(s->dq_settings[ch])); + + break; + case MEM_CLOCK_800MHz: + if (s->spd_type == DDR2) { + memcpy(s->dqs_settings[ch], + default_ddr2_800_dqs, + sizeof(s->dqs_settings[ch])); + memcpy(s->dq_settings[ch], + default_ddr2_800_dq, + sizeof(s->dq_settings[ch])); + } + /* else TODO */ + break; + default: /* TODO */ + break; + } } } +} - FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { - if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz) { - for (lane = 0; lane < 8; lane++) - dqsset(i, lane, &dll_setting_667[DQS1+lane]); - for (lane = 0; lane < 8; lane++) - dqset(i, lane, &dll_setting_667[DQ1+lane]); - } else { - for (lane = 0; lane < 8; lane++) - dqsset(i, lane, &dll_setting_800[DQS1+lane]); - for (lane = 0; lane < 8; lane++) - dqset(i, lane, &dll_setting_800[DQ1+lane]); +static void set_all_dq_dqs_dll_settings(struct sysinfo *s) +{ + // Program DQ/DQS dll settings + int ch, lane, rank; + + FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { + for (lane = 0; lane < 8; lane++) { + FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, ch, rank) { + rt_set_dqs(ch, lane, rank, + &s->rt_dqs[ch][rank][lane]); + } + dqsset(ch, lane, &s->dqs_settings[ch][lane]); + dqset(ch, lane, &s->dq_settings[ch][lane]); } } } @@ -1492,6 +1506,9 @@ // Program DLL dll_ddr2(s); + if (!fast_boot) + select_default_dq_dqs_settings(s); + set_all_dq_dqs_dll_settings(s); // RCOMP if (s->boot_path != BOOT_PATH_WARM_RESET) { diff --git a/src/northbridge/intel/x4x/raminit_tables.c b/src/northbridge/intel/x4x/raminit_tables.c new file mode 100644 index 0000000..3cbba13 --- /dev/null +++ b/src/northbridge/intel/x4x/raminit_tables.c @@ -0,0 +1,271 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <stdint.h> +#include "x4x.h" + +const struct dll_setting default_ddr2_667_ctrl[7] = { + /* tap pi db delay coarse*/ + {13, 0, 1, 0, 0, 0}, /* clkset0 */ + {4, 1, 0, 0, 0, 0}, /* ctrl0 */ + {13, 0, 1, 0, 0, 0}, /* clkset1 */ + {4, 5, 0, 0, 0, 0}, /* cmd */ + {4, 1, 0, 0, 0, 0}, /* ctrl1 */ + {4, 1, 0, 0, 0, 0}, /* ctrl2 */ + {4, 1, 0, 0, 0, 0}, /* ctrl3 */ +}; + +const struct dll_setting default_ddr2_667_dqs[8] = { + {1, 5, 1, 1, 1, 0}, + {1, 6, 1, 1, 1, 0}, + {2, 0, 1, 1, 1, 0}, + {2, 1, 1, 1, 1, 0}, + {2, 1, 1, 1, 1, 0}, + {14, 6, 1, 0, 0, 0}, + {14, 3, 1, 0, 0, 0}, + {14, 0, 1, 0, 0, 0}, +}; + +const struct dll_setting default_ddr2_667_dq[8] = { + {9, 0, 0, 0, 1, 0}, + {9, 1, 0, 0, 1, 0}, + {9, 2, 0, 0, 1, 0}, + {9, 2, 0, 0, 1, 0}, + {9, 1, 0, 0, 1, 0}, + {6, 4, 0, 0, 1, 0}, + {6, 2, 0, 0, 1, 0}, + {5, 4, 0, 0, 1, 0} +}; + +const struct dll_setting default_ddr2_800_ctrl[7] = { + /* tap pi db delay coarse */ + {11, 5, 1, 0, 0, 0}, + {0, 5, 1, 1, 0, 0}, + {11, 5, 1, 0, 0, 0}, + {1, 4, 1, 1, 0, 0}, + {0, 5, 1, 1, 0, 0}, + {0, 5, 1, 1, 0, 0}, + {0, 5, 1, 1, 0, 0}, +}; + +const struct dll_setting default_ddr2_800_dqs[8] = { + {2, 5, 1, 1, 1, 0}, + {2, 6, 1, 1, 1, 0}, + {3, 0, 1, 1, 1, 0}, + {3, 0, 1, 1, 1, 0}, + {3, 3, 1, 1, 1, 0}, + {2, 0, 1, 1, 1, 0}, + {1, 3, 1, 1, 1, 0}, + {0, 3, 1, 1, 1, 0}, +}; + +const struct dll_setting default_ddr2_800_dq[8] = { + {9, 3, 0, 0, 1, 0}, + {9, 4, 0, 0, 1, 0}, + {9, 5, 0, 0, 1, 0}, + {9, 6, 0, 0, 1, 0}, + {10, 0, 0, 0, 1, 0}, + {8, 1, 0, 0, 1, 0}, + {7, 5, 0, 0, 1, 0}, + {6, 2, 0, 0, 1, 0} +}; + +const struct dll_setting default_ddr3_800_ctrl[2][7] = { + { /* 1N */ + /* tap pi db(2) delay coarse */ + {8, 2, 0, 0, 0, 0}, + {8, 4, 0, 0, 0, 0}, + {9, 5, 0, 0, 0, 0}, + {6, 1, 0, 0, 0, 0}, + {8, 4, 0, 0, 0, 0}, + {10, 0, 0, 0, 0, 0}, + {10, 0, 0, 0, 0, 0}, }, + { /* 2N */ + {2, 2, 1, 1, 0, 0}, + {2, 4, 1, 1, 0, 0}, + {3, 5, 0, 0, 0, 0}, + {3, 2, 1, 1, 0, 0}, + {2, 4, 1, 1, 0, 0}, + {3, 6, 0, 0, 0, 0}, + {3, 6, 0, 0, 0, 0}, } +}; + +const struct dll_setting default_ddr3_800_dqs[2][8] = { + { /* 1N */ + {12, 0, 1, 0, 0, 0}, + {1, 1, 1, 1, 1, 0}, + {2, 4, 1, 1, 1, 0}, + {3, 5, 0, 0, 1, 0}, + {4, 3, 0, 0, 1, 0}, + {5, 2, 0, 0, 1, 0}, + {6, 1, 0, 0, 1, 0}, + {6, 4, 0, 0, 1, 0}, }, + { /* 2N */ + {5, 6, 0, 0, 0, 0}, + {8, 0, 0, 0, 0, 0}, + {9, 4, 0, 0, 0, 0}, + {10, 4, 1, 0, 0, 0}, + {11, 3, 1, 0, 0, 0}, + {12, 1, 1, 0, 0, 0}, + {0, 1, 1, 1, 1, 0}, + {0, 3, 1, 1, 1, 0}, } +}; + +const struct dll_setting default_ddr3_800_dq[2][8] = { + { /* 1N */ + {4, 1, 0, 0, 1, 0}, + {6, 4, 0, 0, 1, 0}, + {8, 1, 0, 0, 1, 0}, + {8, 6, 0, 0, 1, 0}, + {9, 5, 0, 0, 1, 0}, + {10, 2, 0, 0, 1, 0}, + {10, 6, 1, 0, 1, 0}, + {11, 4, 1, 0, 1, 0} }, + { /* 2N */ + {11, 0, 1, 0, 0, 0}, + {0, 3, 1, 1, 1, 0}, + {2, 1, 1, 1, 1, 0}, + {2, 5, 1, 1, 1, 0}, + {3, 5, 0, 0, 1, 0}, + {4, 2, 0, 0, 1, 0}, + {4, 6, 0, 0, 1, 0}, + {5, 4, 0, 0, 1, 0}, } +}; + +const struct dll_setting default_ddr3_1067_ctrl[2][7] = { + { /* 1N */ + {8, 5, 0, 0, 0, 0}, + {7, 6, 0, 0, 0, 0}, + {10, 2, 1, 0, 0, 0}, + {0, 4, 4, 0, 0, 0}, + {7, 6, 0, 0, 0, 0}, + {9, 2, 1, 0, 0, 0}, + {9, 2, 1, 0, 0, 0}, }, + { /* 2N */ + {1, 5, 1, 1, 0, 0}, + {0, 6, 1, 1, 0, 0}, + {3, 2, 0, 0, 0, 0}, + {2, 6, 1, 1, 0, 0}, + {0, 6, 1, 1, 0, 0}, + {2, 2, 1, 1, 0, 0}, + {2, 2, 1, 1, 0, 0}, } +}; + +const struct dll_setting default_ddr3_1067_dqs[2][8] = { + { /* 1N */ + {2, 5, 1, 1, 1, 0}, + {5, 1, 0, 0, 1, 0}, + {6, 6, 0, 0, 1, 0}, + {8, 0, 0, 0, 1, 0}, + {8, 6, 0, 0, 1, 0}, + {9, 6, 1, 0, 1, 0}, + {10, 6, 1, 0, 1, 0}, + {0, 1, 1, 1, 0, 0}, }, + { /* 2N */ + {6, 4, 0, 0, 0, 0}, + {9, 1, 1, 0, 0, 0}, + {10, 6, 1, 0, 0, 0}, + {1, 0, 1, 1, 1, 0}, + {1, 6, 1, 1, 1, 0}, + {2, 5, 1, 1, 1, 0}, + {3, 5, 0, 0, 1, 0}, + {4, 1, 0, 0, 1, 0}, + } +}; + +const struct dll_setting default_ddr3_1067_dq[2][8] = { + { /* 1N */ + {6, 5, 0, 0, 1, 0}, + {9, 3, 1, 0, 1, 0}, + {0, 2, 1, 1, 0, 1}, + {1, 0, 1, 1, 0, 1}, + {2, 0, 1, 1, 0, 1}, + {2, 5, 1, 1, 0, 1}, + {3, 2, 0, 0, 0, 1}, + {4, 1, 0, 0, 0, 1}, }, + { /* 2N */ + {10, 5, 1, 0, 0, 0}, + {2, 3, 1, 1, 1, 0}, + {4, 1, 0, 0, 1, 0}, + {5, 0, 0, 0, 1, 0}, + {6, 0, 0, 0, 1, 0}, + {6, 5, 0, 0, 1, 0}, + {7, 2, 0, 0, 1, 0}, + {8, 1, 0, 0, 1, 0}, + } +}; + +const struct dll_setting default_ddr3_1333_ctrl[2][7] = { + { /* 1N */ + {8, 5, 0, 0, 0, 0}, + {9, 0, 1, 0, 0, 0}, + {10, 2, 1, 0, 0, 0}, + {0, 0, 1, 1, 0, 0}, + {9, 0, 1, 0, 0, 0}, + {10, 4, 1, 0, 0, 0}, + {10, 4, 1, 0, 0, 0}, }, + { /* 2N */ + {1, 6, 1, 1, 0, 0}, + {2, 2, 1, 1, 0, 0}, + {4, 2, 0, 0, 0, 0}, + {3, 1, 1, 1, 0, 0}, + {2, 2, 1, 1, 0, 0}, + {4, 5, 0, 0, 0, 0}, + {4, 5, 0, 0, 0, 0}, } +}; + +const struct dll_setting default_ddr3_1333_dqs[2][8] = { + { /* 1N */ + {2, 4, 1, 1, 1, 0}, + {5, 1, 0, 0, 1, 0}, + {6, 6, 0, 0, 1, 0}, + {8, 0, 0, 0, 1, 0}, + {8, 6, 0, 0, 1, 0}, + {9, 5, 1, 0, 1, 0}, + {10, 6, 1, 0, 1, 0}, + {0, 1, 1, 1, 0, 1}, }, + { /* 2N */ + {10, 4, 0, 0, 0, 0}, + {0, 3, 1, 1, 1, 0}, + {3, 2, 1, 1, 1, 0}, + {5, 0, 0, 0, 1, 0}, + {6, 1, 0, 0, 1, 0}, + {7, 4, 0, 0, 1, 0}, + {9, 2, 0, 0, 1, 0}, + {9, 6, 0, 0, 1, 0}, } +}; + +const struct dll_setting default_ddr3_1333_dq[2][8] = { + { /* 1N */ + {6, 5, 0, 0, 1, 0}, + {9, 3, 1, 0, 1, 0}, + {0, 2, 1, 1, 0, 1}, + {1, 0, 1, 1, 0, 1}, + {2, 0, 1, 1, 0, 1}, + {2, 5, 1, 1, 0, 1}, + {3, 2, 0, 0, 0, 1}, + {4, 1, 0, 0, 0, 1}, }, + { /* 2N */ + {1, 3, 1, 1, 1, 0}, + {5, 6, 0, 0, 1, 0}, + {8, 5, 0, 0, 1, 0}, + {10, 2, 0, 0, 1, 0}, + {11, 1, 0, 0, 1, 0}, + {12, 3, 1, 0, 1, 0}, + {13, 6, 1, 0, 1, 0}, + {0, 3, 1, 1, 0, 1}, } +}; diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 97c225b..0995435 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -250,6 +250,11 @@ u8 coarse; }; +struct rt_dqs_setting { + u8 tap; + u8 pi; +}; + enum n_banks { N_BANKS_4 = 0, N_BANKS_8 = 1, @@ -305,6 +310,9 @@ struct dimminfo dimms[4]; u8 spd_map[4]; struct rcven_timings rcven_t[TOTAL_CHANNELS]; + struct rt_dqs_setting rt_dqs[TOTAL_CHANNELS][RANKS_PER_CHANNEL][8]; + struct dll_setting dqs_settings[TOTAL_CHANNELS][8]; + struct dll_setting dq_settings[TOTAL_CHANNELS][8]; }; #define BOOT_PATH_NORMAL 0 #define BOOT_PATH_WARM_RESET 1 @@ -318,22 +326,6 @@ CTRL1, CTRL2, CTRL3, - DQS1, - DQS2, - DQS3, - DQS4, - DQS5, - DQS6, - DQS7, - DQS8, - DQ1, - DQ2, - DQ3, - DQ4, - DQ5, - DQ6, - DQ7, - DQ8 }; #ifndef __BOOTBLOCK__ @@ -348,6 +340,22 @@ u32 fsb2mhz(u32 speed); u32 ddr2mhz(u32 speed); +extern const struct dll_setting default_ddr2_667_ctrl[7]; +extern const struct dll_setting default_ddr2_800_ctrl[7]; +extern const struct dll_setting default_ddr3_800_ctrl[2][7]; +extern const struct dll_setting default_ddr3_1067_ctrl[2][7]; +extern const struct dll_setting default_ddr3_1333_ctrl[2][7]; +extern const struct dll_setting default_ddr2_667_dqs[8]; +extern const struct dll_setting default_ddr2_800_dqs[8]; +extern const struct dll_setting default_ddr3_800_dqs[2][8]; +extern const struct dll_setting default_ddr3_1067_dqs[2][8]; +extern const struct dll_setting default_ddr3_1333_dqs[2][8]; +extern const struct dll_setting default_ddr2_667_dq[8]; +extern const struct dll_setting default_ddr2_800_dq[8]; +extern const struct dll_setting default_ddr3_800_dq[2][8]; +extern const struct dll_setting default_ddr3_1067_dq[2][8]; +extern const struct dll_setting default_ddr3_1333_dq[2][8]; + struct acpi_rsdp; #ifndef __SIMPLE_DEVICE__ unsigned long northbridge_write_acpi_tables(device_t device, unsigned long start, struct acpi_rsdp *rsdp); -- To view, visit https://review.coreboot.org/22327 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0e3676e06586ea84fc0729469946dbc9a8225934 Gerrit-Change-Number: 22327 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: ec/lenovo/h8: Clear EC output queue before enablement
by build bot (Jenkins) (Code Review) 04 Nov '17

04 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22181 ) Change subject: ec/lenovo/h8: Clear EC output queue before enablement ...................................................................... Patch Set 22: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17906/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/62945/ : SUCCESS -- To view, visit https://review.coreboot.org/22181 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id1733f7350232d0b10ac0d1bc912b62e7fa4da75 Gerrit-Change-Number: 22181 Gerrit-PatchSet: 22 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Maximilian Schander <coreboot(a)mimoja.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 04 Nov 2017 04:19:06 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: ec/acpi: add mechanisms to clear EC output queue
by build bot (Jenkins) (Code Review) 04 Nov '17

04 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22180 ) Change subject: ec/acpi: add mechanisms to clear EC output queue ...................................................................... Patch Set 22: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17905/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/62944/ : SUCCESS -- To view, visit https://review.coreboot.org/22180 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iee031306c02f5211a4512c6b4ec90f7f0db196ae Gerrit-Change-Number: 22180 Gerrit-PatchSet: 22 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 04 Nov 2017 03:45:07 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: CI test: Payloads
by build bot (Jenkins) (Code Review) 04 Nov '17

04 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20668 ) Change subject: CI test: Payloads ...................................................................... Patch Set 4: Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/62937/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/17899/ : SUCCESS -- To view, visit https://review.coreboot.org/20668 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7298595313a8f62b8c94361fb8ec6a3bca86d5ea Gerrit-Change-Number: 20668 Gerrit-PatchSet: 4 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 04 Nov 2017 01:26:41 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: CI test: Tools
by build bot (Jenkins) (Code Review) 04 Nov '17

04 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20657 ) Change subject: CI test: Tools ...................................................................... Patch Set 5: Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/62938/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/17900/ : SUCCESS -- To view, visit https://review.coreboot.org/20657 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia9e479584be451ef7352bdf68694245f822b8da5 Gerrit-Change-Number: 20657 Gerrit-PatchSet: 5 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 04 Nov 2017 00:49:59 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: CI test: Lint-stable
by build bot (Jenkins) (Code Review) 04 Nov '17

04 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/14197 ) Change subject: CI test: Lint-stable ...................................................................... Patch Set 10: Build Failed https://qa.coreboot.org/job/coreboot-gerrit/62939/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/17901/ : SUCCESS -- To view, visit https://review.coreboot.org/14197 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I38db15c4d169bfebc443007da883e17a08fadc01 Gerrit-Change-Number: 14197 Gerrit-PatchSet: 10 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 04 Nov 2017 00:47:29 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: intel/cannonlake_rvp: Clean up GPIO programming
by build bot (Jenkins) (Code Review) 04 Nov '17

04 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22326 ) Change subject: intel/cannonlake_rvp: Clean up GPIO programming ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17898/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/62936/ : SUCCESS -- To view, visit https://review.coreboot.org/22326 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0022b791bd8459ea2afdcd0241b603ce81408785 Gerrit-Change-Number: 22326 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 04 Nov 2017 00:17:04 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: include: Deactivate timestamp_get if kconfig option not set
by build bot (Jenkins) (Code Review) 04 Nov '17

04 Nov '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22147 ) Change subject: include: Deactivate timestamp_get if kconfig option not set ...................................................................... Patch Set 13: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17897/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/62935/ : SUCCESS -- To view, visit https://review.coreboot.org/22147 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8ac63ba7e4485e26dc35fb5a68b1811f6df2f91d Gerrit-Change-Number: 22147 Gerrit-PatchSet: 13 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 04 Nov 2017 00:12:58 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: intel/cannonlake_rvp: Clean up GPIO programming
by Lijian Zhao (Code Review) 04 Nov '17

04 Nov '17

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/22326 Change subject: intel/cannonlake_rvp: Clean up GPIO programming ...................................................................... intel/cannonlake_rvp: Clean up GPIO programming Since we move from cannonlake U DDR 4 platform to cannonlake U LPDDR4 platform, it is also critical to revisit the GPIO settings as they are different. Remove unused GPIO setting for old platform, and clean up the native function definition. PAD_CFG_NF can only select NF1,NF2 ..., set to GPIO mode is illegal. TEST=Boot up in chromeos successfully. Change-Id: I0022b791bd8459ea2afdcd0241b603ce81408785 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c 1 file changed, 19 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/22326/1 diff --git a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c index b69d338..f50c5b7 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/cannonlake_rvp/variants/baseboard/gpio.c @@ -30,9 +30,7 @@ /* A7 : PRIQAB_GSP10_CS1B */ PAD_CFG_GPI_SCI_HIGH(GPP_A7, UP_20K, DEEP, EDGE_SINGLE), /* A8 : CLKRUNB */ -#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY) PAD_CFG_GPO(GPP_A8, 1, PLTRST), -#endif /* A9 : CLKOUT_LPC_0_ESPI_CLK */ /* A10 : CLKOUT_LPC_1 */ /* A11 : PMEB_GSP11_CS1B */ @@ -47,17 +45,17 @@ PAD_CFG_GPO(GPP_A16, 0, PLTRST), /* A17 : SD_VDD1_PWR_EN_B_ISH_GP_7 */ /* A18 : ISH_GP_0 */ - PAD_CFG_NF(GPP_A18, UP_20K, DEEP, GPIO), + PAD_CFG_NF(GPP_A18, UP_20K, DEEP, NF1), /* A19 : ISH_GP_1 */ - PAD_CFG_NF(GPP_A19, UP_20K, DEEP, GPIO), + PAD_CFG_NF(GPP_A19, UP_20K, DEEP, NF1), /* A20 : ISH_GP_2 */ - PAD_CFG_NF(GPP_A20, UP_20K, DEEP, GPIO), + PAD_CFG_NF(GPP_A20, UP_20K, DEEP, NF1), /* A21 : ISH_GP_3 */ - PAD_CFG_NF(GPP_A21, UP_20K, DEEP, GPIO), + PAD_CFG_NF(GPP_A21, UP_20K, DEEP, NF1), /* A22 : ISH_GP_4 */ - PAD_CFG_NF(GPP_A22, UP_20K, DEEP, GPIO), + PAD_CFG_NF(GPP_A22, UP_20K, DEEP, NF1), /* A23 : ISH_GP_5 */ - PAD_CFG_NF(GPP_A23, UP_20K, DEEP, GPIO), + PAD_CFG_NF(GPP_A23, UP_20K, DEEP, NF1), /* B0 : CORE_VID_0 */ /* B1 : CORE_VID_1 */ @@ -74,18 +72,13 @@ /* B9 : SRCCLKREQB_4 */ /* B10 : SRCCLKREQB_5 */ /* B11 : EXT_PWR_GATEB */ -#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY) PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), -#endif -#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU) - PAD_CFG_GPO(GPP_B11, 1, PLTRST), -#endif /* B12 : SLP_S0B */ /* B13 : PLTRSTB */ /* B14 : SPKR */ PAD_CFG_GPO(GPP_B14, 1, PLTRST), /* B15 : GSPI0_CS0B */ - PAD_CFG_NF(GPP_B15, NONE, DEEP, GPIO), + PAD_CFG_GPO(GPP_B15, 0, DEEP), /* B16 : GSPI0_CLK */ PAD_CFG_GPI_APIC(GPP_B16, NONE, PLTRST, LEVEL, NONE), /* B17 : GSPI0_MISO */ @@ -175,17 +168,10 @@ /* E3 : CPU_GP_0 */ PAD_CFG_GPI_SMI(GPP_E3, NONE, PLTRST, EDGE_SINGLE, NONE), /* E4 : SATA_DEVSLP_0 */ -#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY) - PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), -#endif -#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU) - PAD_CFG_GPI_SCI_HIGH(GPP_E4, NONE, PLTRST, LEVEL), -#endif + PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), /* E5 : SATA_DEVSLP_1 */ /* E6 : SATA_DEVSLP_2 */ -#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY) PAD_CFG_GPI_SCI(GPP_E6, NONE, DEEP, OFF, NONE), -#endif /* E7 : CPU_GP_1 */ PAD_CFG_GPI_INT(GPP_E7, NONE, PLTRST, EDGE_SINGLE), /* E8 : SATA_LEDB */ @@ -196,13 +182,8 @@ /* E13 : DDSP_HPD_0_DISP_MISC_0 */ /* E14 : DDSP_HPD_0_DISP_MISC_1 */ /* E15 : DDSP_HPD_0_DISP_MISC_2 */ - /* E16 : DDSP_HPD_0_DISP_MISC_3 */ -#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY) - PAD_CFG_GPO(GPP_E16, 1, DEEP), -#endif -#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU) - PAD_CFG_GPI_SCI_HIGH(GPP_E16, NONE, DEEP, LEVEL), -#endif + /* E16 : EMMC_EN */ + PAD_CFG_GPO(GPP_E16, 1, PLTRST), /* E17 : EDP_HPD_DISP_MISC_4 */ /* E18 : DDPB_CTRLCLK */ /* E19 : DDPB_CTRLDATA */ @@ -212,7 +193,7 @@ /* E23 : DDPD_CTRLDATA */ /* F0 : CNV_GNSS_PA_BLANKING */ - PAD_CFG_NF(GPP_F0, NONE, DEEP, GPIO), + PAD_CFG_GPI(GPP_F0, NONE, PLTRST), /* F1 : CNV_GNSS_FAT */ PAD_CFG_TERM_GPO(GPP_F1, 1, UP_20K, DEEP), /* F2 : CNV_GNSS_SYSCK */ @@ -228,12 +209,7 @@ /* F9 : CNV_MFUART2_TXD */ PAD_CFG_NF(GPP_F9, UP_20K, DEEP, NF1), /* F10 : GPP_F_10 */ -#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY) - PAD_CFG_GPO(GPP_F10, 1, DEEP), -#endif -#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU) - PAD_CFG_GPI(GPP_F10, UP_20K, PLTRST), -#endif + PAD_CFG_GPO(GPP_F10, 1, PLTRST), /* F11 : EMMC_CMD */ /* F12 : EMMC_DATA0 */ /* F13 : EMMC_DATA1 */ @@ -246,20 +222,18 @@ /* F20 : EMMC_RCLK */ /* F21 : EMMC_CLK */ /* F22 : EMMC_RESETB */ - /* F23 : EMMC_PRESENT */ -#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY) + /* F23 : BIOS_REC */ PAD_CFG_GPI(GPP_F23, UP_20K, DEEP), -#endif /* G0 : SD3_D2 */ /* G1 : SD3_D0_SD4_RCLK_P */ /* G2 : SD3_D1_SD4_RCLK_N */ /* G3 : SD3_D2 */ /* G4 : SD3_D3 */ /* G5 : SD3_CDB */ - PAD_CFG_NF(GPP_G5, UP_20K, DEEP, GPIO), + PAD_CFG_NF(GPP_G5, UP_20K, DEEP, NF1), /* G6 : SD3_CLK */ /* G7 : SD3_WP */ - PAD_CFG_NF(GPP_G7, DN_20K, DEEP, GPIO), + PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1), /* H0 : SSP2_SCLK */ /* H1 : SSP2_SFRM */ @@ -283,14 +257,10 @@ PAD_CFG_GPO(GPP_H14, 0, PLTRST), /* H15 : M2_SKT2_CFG_3 */ PAD_CFG_GPO(GPP_H15, 1, PLTRST), - /* H16 : DDPF_CTRLCLK */ -#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY) - PAD_CFG_GPO(GPP_H16, 1, DEEP), -#endif - /* H17 : DDPF_CTRLDATA */ -#if IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPY) - PAD_CFG_GPO(GPP_H17, 1, DEEP), -#endif + /* H16 : CAM5_PWR_EN */ + PAD_CFG_GPO(GPP_H16, 1, PLTRST), + /* H17 : CAM5_FLASH_STROBE */ + PAD_CFG_GPO(GPP_H17, 1, PLTRST), /* H18 : BOOTMPC */ /* H19 : TIMESYNC_0 */ PAD_CFG_GPO(GPP_H19, 1, PLTRST), -- To view, visit https://review.coreboot.org/22326 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0022b791bd8459ea2afdcd0241b603ce81408785 Gerrit-Change-Number: 22326 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com>

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Change in coreboot[master]: gru: Fix and export SPK_PA_EN GPIO for Scarlet
by Alexandru Stan (Code Review) 04 Nov '17

04 Nov '17

Alexandru Stan has posted comments on this change. ( https://review.coreboot.org/22323 ) Change subject: gru: Fix and export SPK_PA_EN GPIO for Scarlet ...................................................................... Patch Set 1: Code-Review+1 +1 Verified too -- To view, visit https://review.coreboot.org/22323 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1ac70ee47ebf04b8b92ff17a46cbf5d839421a61 Gerrit-Change-Number: 22323 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Alexandru Stan <amstan(a)chromium.org> Gerrit-Reviewer: David Schneider <dnschneid(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 03 Nov 2017 23:23:06 +0000 Gerrit-HasComments: No

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