Hello Aaron Durbin, Julius Werner, Paul Menzel, build bot (Jenkins), Vadim Bendebury,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/22105
to look at the new patch set (#12).
Change subject: security/tpm: Move TSS stacks into sub-directory
......................................................................
security/tpm: Move TSS stacks into sub-directory
Change-Id: I5e20d98665c17d39f3f69772093a062bb905f6f9
Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org>
---
M src/security/tpm/Makefile.inc
R src/security/tpm/tss/tcg-1.2/tss.c
R src/security/tpm/tss/tcg-1.2/tss_internal.h
R src/security/tpm/tss/tcg-1.2/tss_structures.h
R src/security/tpm/tss/tcg-2.0/tss.c
R src/security/tpm/tss/tcg-2.0/tss_marshaling.c
R src/security/tpm/tss/tcg-2.0/tss_marshaling.h
R src/security/tpm/tss/tcg-2.0/tss_structures.h
8 files changed, 14 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/22105/12
--
To view, visit https://review.coreboot.org/22105
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I5e20d98665c17d39f3f69772093a062bb905f6f9
Gerrit-Change-Number: 22105
Gerrit-PatchSet: 12
Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Vadim Bendebury <vbendeb(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Hello Aaron Durbin, Julius Werner, Paul Menzel, build bot (Jenkins), Vadim Bendebury,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/22105
to look at the new patch set (#11).
Change subject: WIP: security/tpm: Move TSS stacks into sub-directory
......................................................................
WIP: security/tpm: Move TSS stacks into sub-directory
Change-Id: I5e20d98665c17d39f3f69772093a062bb905f6f9
Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org>
---
M src/cpu/intel/haswell/romstage.c
M src/drivers/intel/fsp1_1/romstage.c
M src/drivers/intel/fsp2_0/memory_init.c
M src/drivers/pc80/tpm/Makefile.inc
D src/drivers/pc80/tpm/romstage.c
M src/mainboard/asus/kgpe-d16/romstage.c
M src/mainboard/google/link/romstage.c
M src/mainboard/google/parrot/romstage.c
M src/mainboard/google/stout/romstage.c
M src/mainboard/intel/emeraldlake2/romstage.c
M src/mainboard/lenovo/x201/romstage.c
M src/mainboard/pcengines/apu2/romstage.c
M src/mainboard/samsung/lumpy/romstage.c
M src/mainboard/samsung/stumpy/romstage.c
M src/northbridge/intel/sandybridge/romstage.c
M src/security/tpm/Makefile.inc
A src/security/tpm/tspi.h
A src/security/tpm/tspi/tspi.c
R src/security/tpm/tss/tcg-1.2/tss.c
R src/security/tpm/tss/tcg-1.2/tss_internal.h
R src/security/tpm/tss/tcg-1.2/tss_structures.h
R src/security/tpm/tss/tcg-2.0/tss.c
R src/security/tpm/tss/tcg-2.0/tss_marshaling.c
R src/security/tpm/tss/tcg-2.0/tss_marshaling.h
R src/security/tpm/tss/tcg-2.0/tss_structures.h
R src/security/vboot/antirollback.h
M src/security/vboot/secdata_mock.c
M src/security/vboot/secdata_tpm.c
M src/security/vboot/vboot_logic.c
M src/soc/intel/baytrail/romstage/romstage.c
M src/soc/intel/broadwell/romstage/romstage.c
31 files changed, 290 insertions(+), 436 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/22105/11
--
To view, visit https://review.coreboot.org/22105
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I5e20d98665c17d39f3f69772093a062bb905f6f9
Gerrit-Change-Number: 22105
Gerrit-PatchSet: 11
Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Vadim Bendebury <vbendeb(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Martin Roth has uploaded this change for review. ( https://review.coreboot.org/22373
Change subject: mainboard/google/kahlee: Add baseboard framework
......................................................................
mainboard/google/kahlee: Add baseboard framework
BUG=b:68293392
TEST=Build only
Change-Id: Ie4d039b4da10a992fc9dd2b0221fd4a1644aae6a
Signed-off-by: Martin Roth <martinroth(a)google.com>
---
A src/mainboard/google/kahlee/variants/baseboard/Makefile.inc
A src/mainboard/google/kahlee/variants/baseboard/gpio.c
A src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/usb_oc.asl
M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h
A src/mainboard/google/kahlee/variants/baseboard/memory.c
5 files changed, 124 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/22373/1
diff --git a/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc b/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc
new file mode 100644
index 0000000..94f3889
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/baseboard/Makefile.inc
@@ -0,0 +1,22 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2017 Google, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+bootblock-y += gpio.c
+
+romstage-y += gpio.c
+romstage-y += memory.c
+
+ramstage-y += gpio.c
+ramstage-y += memory.c
diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c
new file mode 100644
index 0000000..cb71097
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <AGESA.h>
+#include <FchPlatform.h>
+#include <mainboard.h>
+#include <soc/smi.h>
+#include <soc/southbridge.h>
+#include <stdlib.h>
+
+const GPIO_CONTROL __attribute__((weak)) agesa_board_gpios[] = {
+
+ {-1}
+};
+
+/*
+ * GPE setup table must match ACPI GPE ASL
+ * { gevent, gpe, direction, level }
+ */
+static const struct sci_source gpe_table[] = {
+
+
+};
+
+const __attribute__((weak)) struct sci_source *get_gpe_table(size_t *num)
+{
+ *num = ARRAY_SIZE(gpe_table);
+ return gpe_table;
+}
diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/usb_oc.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/usb_oc.asl
new file mode 100644
index 0000000..72f26d8
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/usb_oc.asl
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Advanced Micro Devices, Inc.
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* USB overcurrent mapping pins. */
+Name (UOM0, 0)
+Name (UOM1, 0)
+Name (UOM2, 0)
+Name (UOM3, 0)
+Name (UOM4, 0)
+Name (UOM5, 0)
+Name (UOM6, 0)
+Name (UOM7, 0)
+Name (UOM8, 0)
+Name (UOM9, 0)
+
+/* USB Overcurrent GPEs */
diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h
index 5aca3e8..a936061 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h
+++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/gpio.h
@@ -25,8 +25,8 @@
# define MEM_CONFIG3 GPIO_0
/* SPI Write protect */
-#define CROS_WP_GPIO GPIO_0
-#define GPIO_EC_IN_RW GPIO_0
+#define CROS_WP_GPIO 0
+#define GPIO_EC_IN_RW 0
#endif /* _ACPI__ */
diff --git a/src/mainboard/google/kahlee/variants/baseboard/memory.c b/src/mainboard/google/kahlee/variants/baseboard/memory.c
new file mode 100644
index 0000000..511241f
--- /dev/null
+++ b/src/mainboard/google/kahlee/variants/baseboard/memory.c
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <gpio.h> /* src/include/gpio.h */
+#include <baseboard/variants.h>
+#include <variant/gpio.h>
+
+size_t __attribute__((weak)) variant_board_id(void)
+{
+ gpio_t pads[] = {
+ [3] = MEM_CONFIG3,
+ [2] = MEM_CONFIG2,
+ [1] = MEM_CONFIG1,
+ [0] = MEM_CONFIG0,
+ };
+
+ return gpio_pullup_base2_value(pads, ARRAY_SIZE(pads));
+}
--
To view, visit https://review.coreboot.org/22373
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ie4d039b4da10a992fc9dd2b0221fd4a1644aae6a
Gerrit-Change-Number: 22373
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth <martinroth(a)google.com>
Martin Roth has uploaded this change for review. ( https://review.coreboot.org/22371
Change subject: mainboard/google/kahlee: Define MEM_CONFIG3 for Kahlee variant
......................................................................
mainboard/google/kahlee: Define MEM_CONFIG3 for Kahlee variant
Even though this GPIO isn't used for Kahlee, it needs to be defined
so that the weak version of the variant_board_id() function can
compile.
BUG=b:68293392
TEST=Build and boot kahlee
Change-Id: Ia8daf70fbafe02ec37c6b5eb8421cdb11de3be8b
Signed-off-by: Martin Roth <martinroth(a)google.com>
---
M src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/22371/1
diff --git a/src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h b/src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h
index dfb6354..78bca93 100644
--- a/src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h
+++ b/src/mainboard/google/kahlee/variants/kahlee/include/variant/gpio.h
@@ -22,6 +22,7 @@
#define MEM_CONFIG0 GPIO_135
#define MEM_CONFIG1 GPIO_140
#define MEM_CONFIG2 GPIO_144
+#define MEM_CONFIG3 0
/* SPI Write protect */
#define CROS_WP_GPIO GPIO_142
--
To view, visit https://review.coreboot.org/22371
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ia8daf70fbafe02ec37c6b5eb8421cdb11de3be8b
Gerrit-Change-Number: 22371
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth <martinroth(a)google.com>