coreboot-gerrit October 2017

coreboot-gerrit@coreboot.org

1 participants
1771 discussions

Change in coreboot[master]: nb/intel/sandybridge/raminit: Fix PDWN_mode on desktops
by build bot (Jenkins) (Code Review) 31 Oct '17

31 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22260 ) Change subject: nb/intel/sandybridge/raminit: Fix PDWN_mode on desktops ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17726/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/62723/ : SUCCESS -- To view, visit https://review.coreboot.org/22260 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic42f2ff3e719636be67b00fa37155939cd2e17de Gerrit-Change-Number: 22260 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 31 Oct 2017 10:53:01 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: nb/intel/sandybridge/raminit: Set REFIx9 according to spec
by build bot (Jenkins) (Code Review) 31 Oct '17

31 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22259 ) Change subject: nb/intel/sandybridge/raminit: Set REFIx9 according to spec ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17725/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/62722/ : SUCCESS -- To view, visit https://review.coreboot.org/22259 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ifd32a70f28aa75418030b0e4d1fc7d539a315f83 Gerrit-Change-Number: 22259 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 31 Oct 2017 10:50:36 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: nb/intel/sandybridge/raminit: Set REFIx9 according to spec
by Patrick Rudolph (Code Review) 31 Oct '17

31 Oct '17

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/22259 Change subject: nb/intel/sandybridge/raminit: Set REFIx9 according to spec ...................................................................... nb/intel/sandybridge/raminit: Set REFIx9 according to spec Set tREFIx9 to 8.9*tREFI/1024 as suggested in xeon-e3-1200v3-vol-2-datasheet.pdf chapter 4.2.15 or 2nd-gen-core-family-mobile-vol-2-datasheet chapter 2.14.1. Use the minimum value of REFI*8.9 and tRASmax as suggested by 3rd-gen-core-desktop-vol-2-datasheet.pdf chapter 2.13.9. Change-Id: Ifd32a70f28aa75418030b0e4d1fc7d539a315f83 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 12 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/22259/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index eaef5f7..88357f6 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -263,16 +263,18 @@ dram_odt_stretch(ctrl, channel); - // REFI - reg = 0; - val32 = ctrl->tREFI; - reg = (reg & ~0xffff) | val32; - val32 = ctrl->tRFC; - reg = (reg & ~0x1ff0000) | (val32 << 16); - val32 = (u32) (ctrl->tREFI * 9) / 1024; - reg = (reg & ~0xfe000000) | (val32 << 25); - printram("REFI [%x] = %x\n", 0x400 * channel + 0x4298, - reg); + /* + * TC—Refresh timing parameters + * The tREFIx9 field should be programmed to minimum of + * 8.9*tREFI (to allow for possible delays from ZQ or + * isoc) and tRASmax (70us) divided by 1024. + */ + val32 = MIN((ctrl->tREFI * 89) / 10, (70000 << 8) / ctrl->tCK); + + reg = ((ctrl->tREFI & 0xffff) << 0) | + ((ctrl->tRFC & 0x1ff) << 16) | + (((val32 / 1024) & 0x7f) << 25); + printram("REFI [%x] = %x\n", 0x400 * channel + 0x4298, reg); MCHBAR32(0x400 * channel + 0x4298) = reg; MCHBAR32(0x400 * channel + 0x4294) |= 0xff; -- To view, visit https://review.coreboot.org/22259 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifd32a70f28aa75418030b0e4d1fc7d539a315f83 Gerrit-Change-Number: 22259 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

1 0

Change in coreboot[master]: nb/intel/sandybridge/raminit: Fix PDWN_mode on desktops
by Patrick Rudolph (Code Review) 31 Oct '17

31 Oct '17

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/22260 Change subject: nb/intel/sandybridge/raminit: Fix PDWN_mode on desktops ...................................................................... nb/intel/sandybridge/raminit: Fix PDWN_mode on desktops On desktop boards the PPD bit of MRS register MR0 is set and thus DLL_Off mode shouldn't be used, as enforced by datasheet 2nd-gen-core-family-mobile-vol-2-datasheet chapter 2.14.1. Change-Id: Ic42f2ff3e719636be67b00fa37155939cd2e17de Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 8 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/22260/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 88357f6..4c7d372 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -3197,7 +3197,14 @@ write32(DEFAULT_MCHBAR + 0x400c, (read32(DEFAULT_MCHBAR + 0x400c) & 0xFFFFCFFF) | 0x1000); // OK write32(DEFAULT_MCHBAR + 0x440c, (read32(DEFAULT_MCHBAR + 0x440c) & 0xFFFFCFFF) | 0x1000); // OK - write32(DEFAULT_MCHBAR + 0x4cb0, 0x00000740); + + if (ctrl->mobile) + /* APD - DLL Off, 64 DCLKs until idle, decision per rank */ + write32(DEFAULT_MCHBAR + 0x4cb0, 0x00000740); + else + /* APD - PPD, 64 DCLKs until idle, decision per rank */ + write32(DEFAULT_MCHBAR + 0x4cb0, 0x00000340); + write32(DEFAULT_MCHBAR + 0x4380, 0x00000aaa); // OK write32(DEFAULT_MCHBAR + 0x4780, 0x00000aaa); // OK write32(DEFAULT_MCHBAR + 0x4f88, 0x5f7003ff); // OK -- To view, visit https://review.coreboot.org/22260 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic42f2ff3e719636be67b00fa37155939cd2e17de Gerrit-Change-Number: 22260 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

1 0

Change in coreboot[master]: vx900: map the SPI controller
by build bot (Jenkins) (Code Review) 31 Oct '17

31 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22258 ) Change subject: vx900: map the SPI controller ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17724/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/62720/ : SUCCESS -- To view, visit https://review.coreboot.org/22258 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id756d86a7f3b34f816ea7a7ed78f159512f550d5 Gerrit-Change-Number: 22258 Gerrit-PatchSet: 1 Gerrit-Owner: Lubomir Rintel <lkundrak(a)v3.sk> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 31 Oct 2017 08:54:35 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: vx900: fix format strings for DEBUG_RAM_SETUP=y
by build bot (Jenkins) (Code Review) 31 Oct '17

31 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22257 ) Change subject: vx900: fix format strings for DEBUG_RAM_SETUP=y ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17723/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/62719/ : SUCCESS -- To view, visit https://review.coreboot.org/22257 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I990969cf1389c19032c4a0fafbdef45b9d6d1e8b Gerrit-Change-Number: 22257 Gerrit-PatchSet: 1 Gerrit-Owner: Lubomir Rintel <lkundrak(a)v3.sk> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 31 Oct 2017 08:50:05 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: vx900: map the SPI controller
by Lubomir Rintel (Code Review) 31 Oct '17

31 Oct '17

Lubomir Rintel has uploaded this change for review. ( https://review.coreboot.org/22258 Change subject: vx900: map the SPI controller ...................................................................... vx900: map the SPI controller This is required for Flashrom to work well. Change-Id: Id756d86a7f3b34f816ea7a7ed78f159512f550d5 Signed-off-by: Lubomir Rintel <lkundrak(a)v3.sk> --- M src/northbridge/via/vx900/lpc.c M src/northbridge/via/vx900/vx900.h 2 files changed, 53 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/22258/1 diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c index b36aaed..822e9ac 100644 --- a/src/northbridge/via/vx900/lpc.c +++ b/src/northbridge/via/vx900/lpc.c @@ -184,9 +184,58 @@ dump_pci_device(dev); } +static void vx900_lpc_read_resources(device_t dev) +{ + struct resource *res; + pci_dev_read_resources(dev); + + /* MMIO space */ + res = new_resource(dev, VX900_MMCONFIG_MBAR); + res->base = 0xfed03000; + res->size = 0x1000; + res->align = 12; + res->gran = 12; + res->limit = 0xffffffff; + res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE; + + /* SPI controller */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + res->base = 0xfed02000; + res->size = 0x8; + res->align = 12; + res->gran = 12; + res->limit = 0xffffffff; + res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE; +} + +static void vx900_lpc_set_resources(device_t dev) +{ + struct resource *mmio, *spi; + u32 reg; + + mmio = find_resource(dev, VX900_MMCONFIG_MBAR); + if (mmio) { + report_resource_stored(dev, mmio, "<mmconfig>"); + mmio->flags |= IORESOURCE_STORED; + reg = pci_read_config32(dev, VX900_MMCONFIG_MBAR); + reg &= 0xff000000; + reg |= mmio->base >> 8; + pci_write_config32(dev, VX900_MMCONFIG_MBAR, reg); + + spi = find_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + if (spi) { + report_resource_stored(dev, spi, "<spi>"); + spi->flags |= IORESOURCE_STORED; + /* Set base and the enable bit. */ + ((u32*)(uintptr_t)mmio->base)[0] = (spi->base | 0x01); + } + } + pci_dev_set_resources(dev); +} + static struct device_operations vx900_lpc_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .read_resources = vx900_lpc_read_resources, + .set_resources = vx900_lpc_set_resources, .enable_resources = pci_dev_enable_resources, .init = vx900_lpc_init, .scan_bus = scan_lpc_bus, diff --git a/src/northbridge/via/vx900/vx900.h b/src/northbridge/via/vx900/vx900.h index 12e5733..216f637 100644 --- a/src/northbridge/via/vx900/vx900.h +++ b/src/northbridge/via/vx900/vx900.h @@ -26,6 +26,8 @@ #define SMBUS_IO_BASE 0x500 +#define VX900_MMCONFIG_MBAR 0xbc + /* The maximum number of DIMM slots that the VX900 supports */ #define VX900_MAX_DIMM_SLOTS 2 #define VX900_MAX_MEM_RANKS 4 -- To view, visit https://review.coreboot.org/22258 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id756d86a7f3b34f816ea7a7ed78f159512f550d5 Gerrit-Change-Number: 22258 Gerrit-PatchSet: 1 Gerrit-Owner: Lubomir Rintel <lkundrak(a)v3.sk>

1 0

Change in coreboot[master]: vx900: fix format strings for DEBUG_RAM_SETUP=y
by Lubomir Rintel (Code Review) 31 Oct '17

31 Oct '17

Lubomir Rintel has uploaded this change for review. ( https://review.coreboot.org/22257 Change subject: vx900: fix format strings for DEBUG_RAM_SETUP=y ...................................................................... vx900: fix format strings for DEBUG_RAM_SETUP=y Change-Id: I990969cf1389c19032c4a0fafbdef45b9d6d1e8b Signed-off-by: Lubomir Rintel <lkundrak(a)v3.sk> --- M src/northbridge/via/vx900/raminit_ddr3.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/22257/1 diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c index 56ec5fd..eec4aa3 100644 --- a/src/northbridge/via/vx900/raminit_ddr3.c +++ b/src/northbridge/via/vx900/raminit_ddr3.c @@ -897,7 +897,7 @@ for (i = 0; i < VX900_MAX_MEM_RANKS; i++) { if (ranks->phys_rank_size_mb[i] == 0) continue; - printram("Initializing rank %lu\n", i); + printram("Initializing rank %zu\n", i); /* Set target physical rank to virtual rank 0 * other ranks to virtual rank 3*/ @@ -1283,7 +1283,7 @@ break; } if (n_tries > 1) - printram("Hmm, we had to try %lu times before our calibration " + printram("Hmm, we had to try %zu times before our calibration " "was good.\n", n_tries); } @@ -1340,7 +1340,7 @@ break; } if (n_tries > 1) - printram("Hmm, we had to try %lu times before our calibration " + printram("Hmm, we had to try %zu times before our calibration " "was good.\n", n_tries); } @@ -1575,7 +1575,7 @@ * column address bits. */ if ((col_bits < 10) || (col_bits > 11)) { - printram("DIMM %ld has %d column address bits.\n", + printram("DIMM %zd has %d column address bits.\n", i, col_bits); die("Unsupported DIMM. Try booting without this DIMM"); } -- To view, visit https://review.coreboot.org/22257 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I990969cf1389c19032c4a0fafbdef45b9d6d1e8b Gerrit-Change-Number: 22257 Gerrit-PatchSet: 1 Gerrit-Owner: Lubomir Rintel <lkundrak(a)v3.sk>

1 0

Change in coreboot[master]: util/pirdump: add tool to dump PIR table
by build bot (Jenkins) (Code Review) 31 Oct '17

31 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22256 ) Change subject: util/pirdump: add tool to dump PIR table ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17722/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/62718/ : SUCCESS -- To view, visit https://review.coreboot.org/22256 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9b0a2ae459bb98ed6854fef280d67f9c14a25314 Gerrit-Change-Number: 22256 Gerrit-PatchSet: 1 Gerrit-Owner: Lubomir Rintel <lkundrak(a)v3.sk> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 31 Oct 2017 08:42:33 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: util/pirdump: add tool to dump PIR table
by Lubomir Rintel (Code Review) 31 Oct '17

31 Oct '17

Lubomir Rintel has uploaded this change for review. ( https://review.coreboot.org/22256 Change subject: util/pirdump: add tool to dump PIR table ...................................................................... util/pirdump: add tool to dump PIR table Signed-off-by: Lubomir Rintel <lkundrak(a)v3.sk> Change-Id: I9b0a2ae459bb98ed6854fef280d67f9c14a25314 --- A util/pirdump/Makefile A util/pirdump/pirdump.1 A util/pirdump/pirdump.c 3 files changed, 346 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/22256/1 diff --git a/util/pirdump/Makefile b/util/pirdump/Makefile new file mode 100644 index 0000000..7938c82 --- /dev/null +++ b/util/pirdump/Makefile @@ -0,0 +1,33 @@ +# +# Copyright (C) 2017 Lubomir Rintel <lkundrak(a)v3.sk> +# +# Based on an inteltool Makefile: +# +# Copyright (C) 2008 by coresystems GmbH +# written by Stefan Reinauer <stepan(a)coresystems.de> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +PROGRAM = pirdump + +all: $(PROGRAM) + +clean: + rm -f $(PROGRAM) *.o + +install: $(PROGRAM) + mkdir -p $(DESTDIR)$(PREFIX)/bin + install $(PROGRAM) $(DESTDIR)$(PREFIX)/bin + mkdir -p $(DESTDIR)$(PREFIX)/share/man/man1 + install -p -m644 $(PROGRAM).1 $(DESTDIR)$(PREFIX)/share/man/man1 + +.PHONY: all clean diff --git a/util/pirdump/pirdump.1 b/util/pirdump/pirdump.1 new file mode 100644 index 0000000..6e61419 --- /dev/null +++ b/util/pirdump/pirdump.1 @@ -0,0 +1,56 @@ +.TH PIRDUMP 1 "October 29, 2017" +.SH NAME +pirdump \- dump the PCI Interrupt Routing table +.SH SYNOPSIS +.B pirdump [format] [<dump file>] +.SH DESCRIPTION +.B pirdump +dumps the PIR table from memory or a dump file in a variety of formats. +.SH OPTIONS +.TP +.B "\-d" | "\-\-default" +Dump in human-readable format (default). +.TP +.B "\-r" | "\-\-raw" +Dump the raw (binary) table data. +.TP +.B "\-c" | "\-\-C" +Dump the C language snippet with coreboot's "struct +irq_routing_table" initializer. +.TP +.B "\-\-" +Keeps the default format. This is useful if your dump file name starts with a +dash. +.TP +.B "<dump file>" +Look for the PIR table in the provided file instead of memory. +.SH EXAMPLES +.TP +.B "pirdump" +Look for the system's PIR table and print it in a human-readable form. +.TP +.B "pirdump --raw >dump.pir" +Dump the system's PIR table into a file. +.TP +.B "pirdump -c dump.pir" +Read a the PIR table dump from a file and print it in a C language form. +.B "pirdump build/ramstage/mainboard/hp/t5550/irq_tables.o" +Find the PIR table in an object file and print it in a human-readable form. +.SH BUGS +The checksum and table size is not checked for validity. +.P +Works only on little-endian systems. +.P +Please report any bugs to https://ticket.coreboot.org/projects/coreboot or the +coreboot mailing list at <coreboot(a)coreboot.org>. +.SH LICENCE +.B pirdump +is covered by the GNU General Public License (GPL), version 2 or (at your +option) any later version. +.SH SEE ALSO +.BR flashrom (1), +.BR abuild (1). +.SH COPYRIGHT +2017 Lubomir Rintel +.SH AUTHORS +2017 Lubomir Rintel <lkundrak(a)v3.sk> diff --git a/util/pirdump/pirdump.c b/util/pirdump/pirdump.c new file mode 100644 index 0000000..336b360 --- /dev/null +++ b/util/pirdump/pirdump.c @@ -0,0 +1,257 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Lubomir Rintel <lkundrak(a)v3.sk> + * + * Structure definitions were copied from + * src/arch/x86/include/arch/pirq_routing.h: + * + * Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Copyright (C) 2012 Patrick Georgi <patrick(a)georgi-clan.de> + * Copyright (C) 2010 Stefan Reinauer <stepan(a)coreboot.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <fcntl.h> +#include <stdint.h> +#include <stdio.h> +#include <string.h> +#include <sys/mman.h> +#include <sys/stat.h> +#include <sys/types.h> +#include <unistd.h> + +#define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24)) +#define PIRQ_VERSION 0x0100 + +struct irq_info { + uint8_t bus, devfn; /* Bus, device and function */ + struct { + uint8_t link; /* IRQ line ID, chipset dependent, 0=not routed */ + uint16_t bitmap; /* Available IRQs */ + } __attribute__((packed)) irq[4]; + uint8_t slot; /* Slot number, 0=onboard */ + uint8_t rfu; +} __attribute__((packed)); + +struct irq_routing_table { + uint32_t signature; /* PIRQ_SIGNATURE should be here */ + uint16_t version; /* PIRQ_VERSION */ + uint16_t size; /* Table size in bytes */ + uint8_t rtr_bus, rtr_devfn; /* Where the interrupt router lies */ + uint16_t exclusive_irqs; /* IRQs devoted exclusively to PCI usage */ + uint16_t rtr_vendor, rtr_device;/* Vendor/device ID of interrupt router */ + uint32_t miniport_data; + uint8_t rfu[11]; + uint8_t checksum; /* Modulo 256 checksum must give zero */ + struct irq_info slots[1]; +} __attribute__((packed)); + +static int +dump (struct irq_routing_table *pir) +{ + int slot, irq; + + printf ("Signature: 0x%08x\n", pir->signature); + printf ("Version: 0x%04x\n", pir->version); + printf ("Size: 0x%04x\n", pir->size); + printf ("Interrupt router bus: 0x%02x\n", pir->rtr_bus); + printf ("Interrupt router device/function: 0x%02x\n", pir->rtr_devfn); + printf ("IRQs devoted exclusively to PCI usage: 0x%02x\n", pir->exclusive_irqs); + printf ("Interrupt router vendor: 0x%04x\n", pir->rtr_vendor); + printf ("Interrupt router device: 0x%04x\n", pir->rtr_device); + printf ("Miniport data: 0x%08x\n", pir->miniport_data); + printf ("Checksum: 0x%02x\n", pir->checksum); + + for (slot = 0; (void *)&pir->slots[slot] < (void *)pir + pir->size; slot++) { + printf ("Slot: %d\n", slot); + printf ("\tBus: 0x%02x\n", pir->slots[slot].bus); + printf ("\tDevice/function: 0x%02x\n", pir->slots[slot].devfn); + + for (irq = 0; irq < 4; irq++) { + printf ("\tIRQ: %d\n", irq); + printf ("\t\tLink: 0x%02x\n", pir->slots[slot].irq[irq].link); + printf ("\t\tBitmap: 0x%04x\n", pir->slots[slot].irq[irq].bitmap); + } + + printf ("\tSlot number: 0x%02x\n", pir->slots[slot].slot); + } + + return 0; +} + +static int +dumpc (struct irq_routing_table *pir) +{ + int i, slot, irq; + + puts ("const struct irq_routing_table table = {"); + + putchar ('\t'); + if (pir->signature == PIRQ_SIGNATURE) + printf ("PIRQ_SIGNATURE"); + else + printf ("0x%08x", pir->signature); + printf (",\t\t/* u32 signature */\n"); + + putchar ('\t'); + if (pir->version == PIRQ_VERSION) + printf ("PIRQ_VERSION"); + else + printf ("0x%08x", pir->signature); + printf (",\t\t/* u16 version */\n"); + + putchar ('\t'); + if ((pir->size - 32) % 16 == 0) + printf ("32 + 16 * %d", (pir->size - 32) / 16); + else + printf ("%d", pir->size); + printf (",\t\t/* Max. number of devices on the bus */\n"); + + printf ("\t0x%02x,\t\t\t/* Interrupt router bus */\n", pir->rtr_bus); + printf ("\t(0x%02x << 3) | 0x%x,\t/* Interrupt router dev */\n", pir->rtr_devfn >> 3, pir->rtr_devfn & 7); + printf ("\t0x%x,\t\t\t/* IRQs devoted exclusively for PCI */\n", pir->exclusive_irqs); + printf ("\t0x%04x,\t\t\t/* Vendor */\n", pir->rtr_vendor); + printf ("\t0x%04x,\t\t\t/* Device */\n", pir->rtr_device); + printf ("\t0x%04x,\t\t\t/* Miniport */\n", pir->miniport_data); + printf ("\t{"); + for (i = 0; i < 11; i++) { + printf (" %d", pir->rfu[i]); + if (i < 10) + printf (","); + } + printf (" }, /* u8 rfu[11] */\n"); + printf ("\t0x%02x,\t\t\t/* Checksum (has to be set to some value that\n", pir->checksum); + puts ("\t\t\t\t * would give 0 after the sum of all bytes"); + puts ("\t\t\t\t * for this structure (including checksum). */"); + puts ("\t{"); + + printf ("\t\t/* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */\n"); + for (slot = 0; (void *)&pir->slots[slot] < (void *)pir + pir->size; slot++) { + printf ("\t\t{0x%02x, ", pir->slots[slot].bus); + printf ("(0x%02x << 3) | 0x%x, {", pir->slots[slot].devfn >> 3, pir->slots[slot].devfn & 7); + for (irq = 0; irq < 4; irq++) { + printf ("{0x%02x, 0x%04x}", pir->slots[slot].irq[irq].link, pir->slots[slot].irq[irq].bitmap); + if (irq < 3) + printf (", "); + } + printf ("}, 0x%x, 0x%x},\n", pir->slots[slot].slot, pir->slots[slot].rfu); + } + puts ("\t}\n};"); + + return 0; +} + +static int +dumpr (struct irq_routing_table *pir) +{ + int written = 0; + int ret; + + do { + ret = write (STDOUT_FILENO, pir + written, pir->size - written); + switch (ret) { + case -1: + perror ("write"); + /* fallthrough */ + case 0: + return 1; + default: + written += ret; + } + } while (written < pir->size); + + return 0; +} + +int +main (int argc, char *argv[]) +{ + int fd; + void *mem; + struct irq_routing_table *pir; + const char *pathname; + size_t size, offset, step; + struct stat statbuf; + enum { DEFAULT, C, RAW } format = DEFAULT; + int arg = 1; + + if (argc > arg && argv[arg][0] == '-') { + if ( strcmp (argv[arg], "--default") == 0 + || strcmp (argv[arg], "-d") == 0) { + format = DEFAULT; + } else if ( strcasecmp (argv[arg], "--c") == 0 + || strcasecmp (argv[arg], "-c") == 0) { + format = C; + } else if ( strcmp (argv[arg], "--raw") == 0 + || strcmp (argv[arg], "-r") == 0) { + format = RAW; + } else if (strcmp (argv[arg], "--") != 0) { + fprintf (stderr, "Bad argument: %s\n", argv[arg]); + return 1; + } + arg++; + } + + if (argc > arg) { + if (stat (argv[arg], &statbuf) == -1) { + perror (argv[arg]); + return 1; + } + + pathname = argv[arg]; + offset = 0; + size = statbuf.st_size; + step = 4; + arg++; + } else { + pathname = "/dev/mem"; + offset = 0xf0000; + size = 0x10000; + step = 16; + } + + if (argc > arg) { + fprintf (stderr, "Extra argument: %s\n", argv[arg]); + return 1; + } + + fd = open (pathname, O_RDONLY); + if (fd == -1) { + perror (pathname); + return 1; + } + + mem = mmap (NULL, size, PROT_READ, MAP_SHARED, fd, offset); + if (mem == MAP_FAILED) { + perror ("mmap"); + return 1; + } + + for (pir = mem; (void *)pir < mem + size; pir = (void *)pir + step) { + if (pir->signature == PIRQ_SIGNATURE) + break; + } + if (pir == mem + size) { + fprintf (stderr, "$PIR signature not found\n"); + return 1; + } + + switch (format) { + case DEFAULT: + return dump (pir); + case RAW: + return dumpr (pir); + case C: + return dumpc (pir); + } +} -- To view, visit https://review.coreboot.org/22256 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9b0a2ae459bb98ed6854fef280d67f9c14a25314 Gerrit-Change-Number: 22256 Gerrit-PatchSet: 1 Gerrit-Owner: Lubomir Rintel <lkundrak(a)v3.sk>

1 0

← Newer
1
2
3
4
5
6
7
8
9
...
178
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2017