Lubomir Rintel has uploaded a new patch set (#2). ( https://review.coreboot.org/22262 )
Change subject: vx900: decode the whole ROM
......................................................................
vx900: decode the whole ROM
Fixes supports for flash ROMs larger than 512K, such as the 1M one in
HP t5550 Thin Client.
Change-Id: I4d6287e130809c33dfbd40bce7913a95b4b3a9c7
Signed-off-by: Lubomir Rintel <lkundrak(a)v3.sk>
---
M src/northbridge/via/vx900/Kconfig
A src/northbridge/via/vx900/bootblock.c
2 files changed, 50 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/22262/2
--
To view, visit https://review.coreboot.org/22262
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I4d6287e130809c33dfbd40bce7913a95b4b3a9c7
Gerrit-Change-Number: 22262
Gerrit-PatchSet: 2
Gerrit-Owner: Lubomir Rintel <lkundrak(a)v3.sk>
Lubomir Rintel has uploaded this change for review. ( https://review.coreboot.org/22262
Change subject: vx900: decode the whole ROM image
......................................................................
vx900: decode the whole ROM image
Fixes supports for flash ROMs larger than 512K, such as the 1M one in
HP t5550 Thin Client.
Change-Id: I4d6287e130809c33dfbd40bce7913a95b4b3a9c7
Signed-off-by: Lubomir Rintel <lkundrak(a)v3.sk>
---
M src/northbridge/via/vx900/Kconfig
A src/northbridge/via/vx900/bootblock.c
2 files changed, 50 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/22262/1
diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig
index 4b1e6cc..bb5e06f 100644
--- a/src/northbridge/via/vx900/Kconfig
+++ b/src/northbridge/via/vx900/Kconfig
@@ -41,4 +41,8 @@
string
default "1106,7122"
+config BOOTBLOCK_NORTHBRIDGE_INIT
+ string
+ default "northbridge/via/vx900/bootblock.c"
+
endif
diff --git a/src/northbridge/via/vx900/bootblock.c b/src/northbridge/via/vx900/bootblock.c
new file mode 100644
index 0000000..11123b6
--- /dev/null
+++ b/src/northbridge/via/vx900/bootblock.c
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Lubomir Rintel <lkundrak(a)v3.sk>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+
+#if CONFIG_ROM_SIZE == 0x80000
+# define ROM_DECODE_MAP 0x00
+#elif CONFIG_ROM_SIZE == 0x100000
+# define ROM_DECODE_MAP 0x40
+#elif CONFIG_ROM_SIZE == 0x180000
+# define ROM_DECODE_MAP 0x60
+#elif CONFIG_ROM_SIZE == 0x200000
+# define ROM_DECODE_MAP 0x70
+#elif CONFIG_ROM_SIZE == 0x280000
+# define ROM_DECODE_MAP 0x78
+#elif CONFIG_ROM_SIZE == 0x300000
+# define ROM_DECODE_MAP 0x7c
+#elif CONFIG_ROM_SIZE == 0x380000
+# define ROM_DECODE_MAP 0x7e
+#elif CONFIG_ROM_SIZE == 0x400000
+# define ROM_DECODE_MAP 0x7f
+#else
+# error "Bad CONFIG_ROM_SIZE"
+#endif
+
+static void bootblock_northbridge_init(void)
+{
+ u8 reg;
+
+ pci_io_read_config8(PCI_DEV(0, 0x11, 0), 0x41);
+ reg |= ROM_DECODE_MAP;
+ pci_io_write_config8(PCI_DEV(0, 0x11, 0), 0x41, reg);
+}
--
To view, visit https://review.coreboot.org/22262
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I4d6287e130809c33dfbd40bce7913a95b4b3a9c7
Gerrit-Change-Number: 22262
Gerrit-PatchSet: 1
Gerrit-Owner: Lubomir Rintel <lkundrak(a)v3.sk>
Hello Kyösti Mälkki, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/22106
to look at the new patch set (#25).
Change subject: security/tpm: Setup generic TSPI
......................................................................
security/tpm: Setup generic TSPI
* Remove second software stack from driver level
(src/drivers/pc80/tpm/romstage.c)
* Re-implement init_tpm() and fix includes.
* Move antirollback.h to the vboot directory.
* Split antirollback and tspi functions.
Change-Id: I883c489801fce88e13952fe24b67315ab6bb1afb
Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org>
---
M src/cpu/intel/haswell/romstage.c
M src/drivers/intel/fsp1_1/romstage.c
M src/drivers/intel/fsp2_0/memory_init.c
M src/drivers/pc80/tpm/Kconfig
M src/drivers/pc80/tpm/Makefile.inc
D src/drivers/pc80/tpm/romstage.c
M src/mainboard/asus/kgpe-d16/romstage.c
M src/mainboard/google/link/romstage.c
M src/mainboard/google/parrot/romstage.c
M src/mainboard/google/stout/romstage.c
M src/mainboard/intel/emeraldlake2/romstage.c
M src/mainboard/lenovo/x201/romstage.c
M src/mainboard/pcengines/apu2/romstage.c
M src/mainboard/samsung/lumpy/romstage.c
M src/mainboard/samsung/stumpy/romstage.c
M src/northbridge/intel/sandybridge/romstage.c
M src/security/tpm/Kconfig
M src/security/tpm/Makefile.inc
M src/security/tpm/tis.h
A src/security/tpm/tspi.h
A src/security/tpm/tspi/tspi.c
M src/security/tpm/tss.h
A src/security/tpm/tss/cr50/tss.c
M src/security/tpm/tss/tcg-1.2/tss.c
A src/security/tpm/tss/tcg-1.2/tss_commands.h
M src/security/tpm/tss/tcg-1.2/tss_structures.h
M src/security/tpm/tss/tcg-2.0/tss.c
M src/security/tpm/tss/tcg-2.0/tss_structures.h
D src/security/tpm/tss_constants.h
R src/security/vboot/antirollback.h
M src/security/vboot/secdata_mock.c
M src/security/vboot/secdata_tpm.c
M src/security/vboot/vboot_logic.c
M src/soc/intel/baytrail/romstage/romstage.c
M src/soc/intel/broadwell/romstage/romstage.c
35 files changed, 656 insertions(+), 746 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/22106/25
--
To view, visit https://review.coreboot.org/22106
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I883c489801fce88e13952fe24b67315ab6bb1afb
Gerrit-Change-Number: 22106
Gerrit-PatchSet: 25
Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>
Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Hello Aaron Durbin, Julius Werner, Paul Menzel, build bot (Jenkins), Vadim Bendebury,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/22105
to look at the new patch set (#10).
Change subject: security/tpm: Move TSS stacks into sub-directory
......................................................................
security/tpm: Move TSS stacks into sub-directory
Change-Id: I5e20d98665c17d39f3f69772093a062bb905f6f9
Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org>
---
M src/security/tpm/Makefile.inc
R src/security/tpm/tss/tcg-1.2/tss.c
R src/security/tpm/tss/tcg-1.2/tss_internal.h
R src/security/tpm/tss/tcg-1.2/tss_structures.h
R src/security/tpm/tss/tcg-2.0/tss.c
R src/security/tpm/tss/tcg-2.0/tss_marshaling.c
R src/security/tpm/tss/tcg-2.0/tss_marshaling.h
R src/security/tpm/tss/tcg-2.0/tss_structures.h
8 files changed, 14 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/22105/10
--
To view, visit https://review.coreboot.org/22105
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I5e20d98665c17d39f3f69772093a062bb905f6f9
Gerrit-Change-Number: 22105
Gerrit-PatchSet: 10
Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Vadim Bendebury <vbendeb(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>