coreboot-gerrit October 2017

coreboot-gerrit@coreboot.org

1 participants
1771 discussions

Change in coreboot[master]: mb/google/poppy/variants/nautilus: add nhlt support
by Naveen Manohar (Code Review) 31 Oct '17

31 Oct '17

Hello Rizwan Qureshi, I'd like you to do a code review. Please visit https://review.coreboot.org/22265 to review the following change. Change subject: mb/google/poppy/variants/nautilus: add nhlt support ...................................................................... mb/google/poppy/variants/nautilus: add nhlt support The use of a NHLT table is required to make audio work on the kabylake SoCs employing the internal DSP. The table describes the audo endpoints (render vs capture) along with their supported formats. Nautilus board uses Dialog da7219 headset codec, Select the appropriate NHLT blob to be packaged in CBFS. Also generate the required ACPI NHLT table for codec and the supported topology in nautilus. BUG=b:68686020 TEST=With the required driver support in kernel verify that the Audio plays on headset and recording on headset mic. Change-Id: I27356a0f1d27cb2190f1ebd141720f3adca4c602 Signed-off-by: Naveen Manohar <naveen.m(a)intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Shruthi Sudhakar <shruthi.sudhakar(a)intel.com> --- M src/mainboard/google/poppy/Kconfig M src/mainboard/google/poppy/variants/baseboard/nhlt.c M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/include/soc/nhlt.h M src/soc/intel/skylake/nhlt/Makefile.inc A src/soc/intel/skylake/nhlt/da7219.c 6 files changed, 93 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/22265/1 diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index ceaf7eb..96fe2ed 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -56,8 +56,10 @@ config INCLUDE_NHLT_BLOBS_NAUTILUS bool "Include blobs for nautilus audio." + default y if BOARD_GOOGLE_NAUTILUS select NHLT_DMIC_2CH select NHLT_DMIC_4CH + select NHLT_DA7219 config MAINBOARD_DIR string diff --git a/src/mainboard/google/poppy/variants/baseboard/nhlt.c b/src/mainboard/google/poppy/variants/baseboard/nhlt.c index 81557e4..9fb6ad9 100644 --- a/src/mainboard/google/poppy/variants/baseboard/nhlt.c +++ b/src/mainboard/google/poppy/variants/baseboard/nhlt.c @@ -28,6 +28,10 @@ if (nhlt_soc_add_dmic_array(nhlt, 4)) printk(BIOS_ERR, "Couldn't add 4CH DMIC arrays.\n"); + /* Dialog DA7219 Headset codec. */ + if (nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP1)) + printk(BIOS_ERR, "Couldn't add Dialog DA7219.\n"); + /* Maxim MAX98927 Smart Amps for left and right channel */ if (nhlt_soc_add_max98927(nhlt, AUDIO_LINK_SSP0)) printk(BIOS_ERR, "Couldn't add Maxim MAX98927\n"); diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index f830f54..f943170 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -272,6 +272,12 @@ help Include DSP firmware settings for max98927 amplifier. +config NHLT_DA7219 + bool + default n + help + Include DSP firmware settings for DA7219 headset codec. + choice prompt "Cache-as-ram implementation" default CAR_NEM_ENHANCED diff --git a/src/soc/intel/skylake/include/soc/nhlt.h b/src/soc/intel/skylake/include/soc/nhlt.h index d3e4568..1af27e8 100644 --- a/src/soc/intel/skylake/include/soc/nhlt.h +++ b/src/soc/intel/skylake/include/soc/nhlt.h @@ -77,4 +77,10 @@ */ int nhlt_soc_add_max98927(struct nhlt *nhlt, int hwlink); +/* + * Add da7219 headset codec on provided SSP link. Return 0 on success, < 0 + * on error. + */ +int nhlt_soc_add_da7219(struct nhlt *nhlt, int hwlink); + #endif diff --git a/src/soc/intel/skylake/nhlt/Makefile.inc b/src/soc/intel/skylake/nhlt/Makefile.inc index 35b2829..9c9b4c8 100644 --- a/src/soc/intel/skylake/nhlt/Makefile.inc +++ b/src/soc/intel/skylake/nhlt/Makefile.inc @@ -5,6 +5,7 @@ ramstage-y += rt5514.c ramstage-y += rt5663.c ramstage-y += max98927.c +ramstage-y += da7219.c # DSP firmware settings files. ifeq ($(CONFIG_SOC_INTEL_KABYLAKE),y) @@ -25,6 +26,7 @@ RT5663 = rt5663-2ch-48khz-24b.bin SSM4567_RENDER = ssm4567-render-2ch-48khz-24b.bin SSM4567_CAPTURE = ssm4567-capture-4ch-48khz-32b.bin +DA7219_RENDER_CAPTURE = dialog-2ch-48khz-24b.bin cbfs-files-$(CONFIG_NHLT_DMIC_2CH) += $(DMIC_2CH_48KHZ_16B) $(DMIC_2CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_2CH_48KHZ_16B) @@ -73,3 +75,7 @@ cbfs-files-$(CONFIG_NHLT_MAX98927) += $(MAX98927_RENDER_24B) $(MAX98927_RENDER_24B)-file := $(NHLT_BLOB_PATH)/$(MAX98927_RENDER_24B) $(MAX98927_RENDER_24B)-type := raw + +cbfs-files-$(CONFIG_NHLT_DA7219) += $(DA7219_RENDER_CAPTURE) +$(DA7219_RENDER_CAPTURE)-file := $(NHLT_BLOB_PATH)/$(DA7219_RENDER_CAPTURE) +$(DA7219_RENDER_CAPTURE)-type := raw diff --git a/src/soc/intel/skylake/nhlt/da7219.c b/src/soc/intel/skylake/nhlt/da7219.c new file mode 100644 index 0000000..6aa66c7 --- /dev/null +++ b/src/soc/intel/skylake/nhlt/da7219.c @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <nhlt.h> +#include <soc/nhlt.h> + +static const struct nhlt_tdm_config tdm_config = { + .virtual_slot = 0, + .config_type = NHLT_TDM_BASIC, +}; + +static const struct nhlt_format_config da7219_formats[] = { + /* 48 KHz 24-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 32, + .valid_bits_per_sample = 24, + .settings_file = "dialog-2ch-48khz-24b.bin", + }, +}; + +static const struct nhlt_endp_descriptor da7219_descriptors[] = { + /* Render Endpoint */ + { + .link = NHLT_LINK_SSP, + .device = NHLT_SSP_DEV_I2S, + .direction = NHLT_DIR_RENDER, + .vid = NHLT_VID, + .did = NHLT_DID_SSP, + .cfg = &tdm_config, + .cfg_size = sizeof(tdm_config), + .formats = da7219_formats, + .num_formats = ARRAY_SIZE(da7219_formats), + }, + /* Capture Endpoint */ + { + .link = NHLT_LINK_SSP, + .device = NHLT_SSP_DEV_I2S, + .direction = NHLT_DIR_CAPTURE, + .vid = NHLT_VID, + .did = NHLT_DID_SSP, + .cfg = &tdm_config, + .cfg_size = sizeof(tdm_config), + .formats = da7219_formats, + .num_formats = ARRAY_SIZE(da7219_formats), + }, +}; + +int nhlt_soc_add_da7219(struct nhlt *nhlt, int hwlink) +{ + /* Virtual bus id of SSP links are the hardware port ids proper. */ + return nhlt_add_ssp_endpoints(nhlt, hwlink, da7219_descriptors, + ARRAY_SIZE(da7219_descriptors)); +} -- To view, visit https://review.coreboot.org/22265 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I27356a0f1d27cb2190f1ebd141720f3adca4c602 Gerrit-Change-Number: 22265 Gerrit-PatchSet: 1 Gerrit-Owner: Naveen Manohar <naveen.m(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com>

1 0

Change in coreboot[master]: mb/google/poppy/variants/nautilus:: Enable Dialog DA7219 support
by Naveen Manohar (Code Review) 31 Oct '17

31 Oct '17

Naveen Manohar has uploaded this change for review. ( https://review.coreboot.org/22264 Change subject: mb/google/poppy/variants/nautilus:: Enable Dialog DA7219 support ...................................................................... mb/google/poppy/variants/nautilus:: Enable Dialog DA7219 support Enable Dialog DA7219 codec i2c device and add required SSDT parameters. BUG=b:68686020 TEST=With required driver support in kernel verify audio on headset Change-Id: Ic815c929f29bec0d26a2981e9933b752c2d84c70 Signed-off-by: Shruthi Sudhakar <shruthi.sudhakar(a)intel.com> Signed-off-by: Naveen Manohar <naveen.m(a)intel.com> --- M src/mainboard/google/poppy/Kconfig M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/gpio.c 3 files changed, 28 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/22264/1 diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index a6ba1a8..ceaf7eb 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -3,6 +3,7 @@ def_bool n select BOARD_ID_AUTO select BOARD_ROMSIZE_KB_16384 + select DRIVERS_I2C_DA7219 if BOARD_GOOGLE_NAUTILUS select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID select DRIVERS_I2C_MAX98927 if !BOARD_GOOGLE_NAUTILUS diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 9530cd9..6618698 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -204,6 +204,13 @@ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, }" + # Enable I2C5 for audio codec at 400kHz + register "i2c[5]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 104, + .fall_time_ns = 52, + }" + register "speed_shift_enable" = "1" # PL2 override 15W for KBL-Y register "tdp_pl2_override" = "15" @@ -241,7 +248,25 @@ device pci 16.4 off end # Management Engine Interface 3 device pci 17.0 off end # SATA device pci 19.0 on end # UART #2 - device pci 19.1 on end # I2C #5 + device pci 19.1 on + chip drivers/i2c/da7219 + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D9_IRQ)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1A on end + end + end # I2C #5 device pci 19.2 on end # I2C #4 device pci 1c.0 on chip drivers/intel/wifi diff --git a/src/mainboard/google/poppy/variants/nautilus/gpio.c b/src/mainboard/google/poppy/variants/nautilus/gpio.c index 6f7a3e7..bf56395 100644 --- a/src/mainboard/google/poppy/variants/nautilus/gpio.c +++ b/src/mainboard/google/poppy/variants/nautilus/gpio.c @@ -195,7 +195,7 @@ /* D8 : ISH_I2C1_SCL ==> NC */ PAD_CFG_NC(GPP_D8), /* D9 : ISH_SPI_CS# ==> HP_IRQ_GPIO */ - PAD_CFG_GPI(GPP_D9, NONE, PLTRST), + PAD_CFG_GPI_APIC(GPP_D9, 20K_PU, DEEP), /* D10 : ISH_SPI_CLK ==> SPKR_RST_L */ PAD_CFG_GPO(GPP_D10, 1, DEEP), /* D11 : ISH_SPI_MISO ==> SPKR_INT_L */ -- To view, visit https://review.coreboot.org/22264 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic815c929f29bec0d26a2981e9933b752c2d84c70 Gerrit-Change-Number: 22264 Gerrit-PatchSet: 1 Gerrit-Owner: Naveen Manohar <naveen.m(a)intel.com>

1 0

Change in coreboot[master]: soc/intel/cannonlake: Install common i2c
by build bot (Jenkins) (Code Review) 31 Oct '17

31 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22238 ) Change subject: soc/intel/cannonlake: Install common i2c ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17753/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/62752/ : SUCCESS -- To view, visit https://review.coreboot.org/22238 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5c60b0579f9e6050308896dcb13dda0bbb724d2b Gerrit-Change-Number: 22238 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 31 Oct 2017 18:23:43 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: spi/tpm: Make sure AP properly syncs up with Cr50
by build bot (Jenkins) (Code Review) 31 Oct '17

31 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22231 ) Change subject: spi/tpm: Make sure AP properly syncs up with Cr50 ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17752/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/62751/ : SUCCESS -- To view, visit https://review.coreboot.org/22231 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7e67ec62c2bf31077b9ae558e09214d07eccf96b Gerrit-Change-Number: 22231 Gerrit-PatchSet: 5 Gerrit-Owner: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 31 Oct 2017 17:41:00 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: spi/tpm: Make sure AP properly syncs up with Cr50
by build bot (Jenkins) (Code Review) 31 Oct '17

31 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22231 ) Change subject: spi/tpm: Make sure AP properly syncs up with Cr50 ...................................................................... Patch Set 4: Build Failed https://qa.coreboot.org/job/coreboot-gerrit/62750/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/17751/ : SUCCESS -- To view, visit https://review.coreboot.org/22231 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7e67ec62c2bf31077b9ae558e09214d07eccf96b Gerrit-Change-Number: 22231 Gerrit-PatchSet: 4 Gerrit-Owner: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 31 Oct 2017 17:25:22 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: amd/stoneyridge: Add UMA settings to chip.h
by build bot (Jenkins) (Code Review) 31 Oct '17

31 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21334 ) Change subject: amd/stoneyridge: Add UMA settings to chip.h ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17749/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/62748/ : SUCCESS -- To view, visit https://review.coreboot.org/21334 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I38b6603f365fdc1f1f615794365476f749e58be7 Gerrit-Change-Number: 21334 Gerrit-PatchSet: 4 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 31 Oct 2017 17:18:32 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: spi/tpm: Make sure AP properly syncs up with Cr50
by build bot (Jenkins) (Code Review) 31 Oct '17

31 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22231 ) Change subject: spi/tpm: Make sure AP properly syncs up with Cr50 ...................................................................... Patch Set 3: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/62749/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/17750/ : SUCCESS -- To view, visit https://review.coreboot.org/22231 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7e67ec62c2bf31077b9ae558e09214d07eccf96b Gerrit-Change-Number: 22231 Gerrit-PatchSet: 3 Gerrit-Owner: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Vadim Bendebury <vbendeb(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 31 Oct 2017 17:11:24 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: google/kahlee: Move DRAM clear override to devicetree
by build bot (Jenkins) (Code Review) 31 Oct '17

31 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21858 ) Change subject: google/kahlee: Move DRAM clear override to devicetree ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/17748/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/62747/ : SUCCESS -- To view, visit https://review.coreboot.org/21858 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3196cb8b94bec64e8ce59e4285cf8d97f442bd3d Gerrit-Change-Number: 21858 Gerrit-PatchSet: 3 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 31 Oct 2017 16:47:00 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/skylake: Turn off XTAL Disqualification for XTAL Shutdown
by build bot (Jenkins) (Code Review) 31 Oct '17

31 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22237 ) Change subject: soc/intel/skylake: Turn off XTAL Disqualification for XTAL Shutdown ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/62746/ : SUCCESS -- To view, visit https://review.coreboot.org/22237 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8abc6e9b88b3bc25cf865824aa14b292ac0524ef Gerrit-Change-Number: 22237 Gerrit-PatchSet: 3 Gerrit-Owner: Roy Mingi Park <roy.mingi.park(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rajneesh Bhardwaj <rajneesh.bhardwaj(a)intel.corp-partner.google.com> Gerrit-Reviewer: Rushikesh S Kadam <rushikesh.s.kadam(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 31 Oct 2017 15:11:23 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: vx900: decode the whole ROM
by build bot (Jenkins) (Code Review) 31 Oct '17

31 Oct '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22262 ) Change subject: vx900: decode the whole ROM ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/62745/ : SUCCESS -- To view, visit https://review.coreboot.org/22262 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4d6287e130809c33dfbd40bce7913a95b4b3a9c7 Gerrit-Change-Number: 22262 Gerrit-PatchSet: 2 Gerrit-Owner: Lubomir Rintel <lkundrak(a)v3.sk> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 31 Oct 2017 14:32:03 +0000 Gerrit-HasComments: No

1 0

Jump to page:

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2017