coreboot-gerrit January 2017

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: util/lint: Add check for the signed-off-by line
by Martin Roth 05 Jan '17

05 Jan '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17941 -gerrit commit fae06a54e6d4085c7e5e27429289ef0d357e712d Author: Martin Roth <martinroth(a)google.com> Date: Thu Dec 22 10:54:55 2016 -0700 util/lint: Add check for the signed-off-by line Gerrit will let you submit a patch without a signed-off-by line, although I believe it can't actually be merged. Instead of catching it either manually, or when the patch is attempting to be merged, catch this in the jenkins builder. Change-Id: I80161befa157266dd4e3209839a06ff398aab6bb Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/lint/lint-stable-020-signed-off-by | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/util/lint/lint-stable-020-signed-off-by b/util/lint/lint-stable-020-signed-off-by new file mode 100755 index 0000000..40b6e9e --- /dev/null +++ b/util/lint/lint-stable-020-signed-off-by @@ -0,0 +1,23 @@ +#!/bin/sh +# This file is part of the coreboot project. +# +# Copyright 2016 Google Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License, or (at your option) +# any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# DESCR: Check for a signed-off-by line on the latest git commit + +# This test is mainly for the jenkins server +if [ -n "$(command -v git)" ] && [ -d .git ]; then + if [ -z "$(git log -n 1 | grep '[[:space:]]\+Signed-off-by: ')" ]; then + echo "No Signed-off-by line in commit message" + fi +fi

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Patch set updated for coreboot: chromeos: Implement locating and decoding wifi sar data from VPD
by Robbie Zhang 05 Jan '17

05 Jan '17

Robbie Zhang (robbie.zhang(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17958 -gerrit commit 6a89cb79285a33ed29b95f52315dfc503e61a4ec Author: Robbie Zhang <robbie.zhang(a)intel.com> Date: Fri Dec 23 11:43:07 2016 -0800 chromeos: Implement locating and decoding wifi sar data from VPD A VPD entry "wifi_sar" needs to be created which contains a heximal encoded string in length of 40 bytes. get_wifi_sar_limits() function retrieves and decodes the data from the VPD entry, which would later be consumed by platform code. BUG=chrome-os-partner:60821 TEST=Build and boot lars and reef Change-Id: I923b58a63dc1f8a7fdd685cf1c618b2fdf4e7061 Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com> --- src/include/sar.h | 28 +++++++++++++++ src/vendorcode/google/chromeos/Makefile.inc | 1 + src/vendorcode/google/chromeos/cros_vpd.h | 1 + src/vendorcode/google/chromeos/sar.c | 53 +++++++++++++++++++++++++++++ 4 files changed, 83 insertions(+) diff --git a/src/include/sar.h b/src/include/sar.h new file mode 100644 index 0000000..05cfe9b --- /dev/null +++ b/src/include/sar.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef _SAR_H_ +#define _SAR_H_ + +#include <stdint.h> + +/* Wifi SAR limit table structure */ +struct wifi_sar_limits { + uint8_t sar_limit[4][10]; /* Total 4 SAR limit sets, each has 10 bytes */ +}; + +/* Retrieve the SAR limits data from VPD and decode it */ +int get_wifi_sar_limits(struct wifi_sar_limits *sar_limits); + +#endif /* _SAR_H_ */ diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index e84eb3d..878b068 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -25,6 +25,7 @@ ramstage-$(CONFIG_CHROMEOS_RAMOOPS) += ramoops.c romstage-y += vpd_decode.c ramstage-y += vpd_decode.c cros_vpd.c vpd_mac.c vpd_serialno.c vpd_calibration.c ramstage-$(CONFIG_HAVE_REGULATORY_DOMAIN) += wrdd.c +ramstage-$(CONFIG_USE_SAR) += sar.c ifeq ($(CONFIG_ARCH_MIPS),) bootblock-y += watchdog.c ramstage-y += watchdog.c diff --git a/src/vendorcode/google/chromeos/cros_vpd.h b/src/vendorcode/google/chromeos/cros_vpd.h index 96ca8af..1fa56a4 100644 --- a/src/vendorcode/google/chromeos/cros_vpd.h +++ b/src/vendorcode/google/chromeos/cros_vpd.h @@ -8,6 +8,7 @@ #define __CROS_VPD_H__ #define CROS_VPD_REGION_NAME "region" +#define CROS_VPD_WIFI_SAR_NAME "wifi_sar" /* * Reads VPD string value by key. diff --git a/src/vendorcode/google/chromeos/sar.c b/src/vendorcode/google/chromeos/sar.c new file mode 100644 index 0000000..4ca014e --- /dev/null +++ b/src/vendorcode/google/chromeos/sar.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <console/console.h> +#include <types.h> +#include <string.h> +#include <sar.h> +#include "cros_vpd.h" + +/* Retrieve the wifi SAR limits data from VPD and decode it */ +int get_wifi_sar_limits(struct wifi_sar_limits *sar_limits) +{ + const char *wifi_sar_limit_key = CROS_VPD_WIFI_SAR_NAME; + /* + * cros_vpd_gets() reads in one less than size characters from the VPD + * with a terminating null byte ('\0') stored as the last character into + * the buffer, thus the increasing by 1 for buffer_size. + */ + const size_t buffer_size = (sizeof(struct wifi_sar_limits) / + sizeof(uint8_t)) * 2 + 1; + char wifi_sar_limit_str[buffer_size]; + + /* Try to read the SAR limit entry from VPD */ + if (!cros_vpd_gets(wifi_sar_limit_key, wifi_sar_limit_str, + ARRAY_SIZE(wifi_sar_limit_str))) { + printk(BIOS_ERR, + "Error: Could not locate '%s' in VPD\n", + wifi_sar_limit_key); + return -1; + } + printk(BIOS_DEBUG, "VPD wifi_sar = %s\n", wifi_sar_limit_str); + + /* Decode the heximal encoded string to binary values */ + if (hexstrtobin(wifi_sar_limit_str, sar_limits, + sizeof(struct wifi_sar_limits)) + < sizeof(struct wifi_sar_limits)) { + printk(BIOS_ERR, + "Error: VPD wifi_sar contains non-heximal value!\n"); + return -1; + } + return 0; +}

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Patch merged into coreboot/master: src/amd: Add common definition of AMD ACPI MMIO address
by gerrit＠coreboot.org 05 Jan '17

05 Jan '17

the following patch was just integrated into master: commit 7ad4dc5e9914e927a827ce48a030d2d04e7ec792 Author: Timothy Pearson <tpearson(a)raptorengineering.com> Date: Wed Jan 4 14:26:26 2017 -0600 src/amd: Add common definition of AMD ACPI MMIO address The bare ACPI MMIO address 0xFED80000 was used in multiple AMD mainboard files as well as the SB800 native code. Reduce duplication by using a centrally defined value for all AMD ACPI MMIO access. Change-Id: I39a30c0d0733096dbd5892c9e18855aa5bb5a4a7 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineering.com> Reviewed-on: https://review.coreboot.org/18032 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/18032 for details. -gerrit

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New patch to review for coreboot: apollolake: Update UPD header files for FSP 1.3.0
by Brandon Breitenstein 05 Jan '17

05 Jan '17

Brandon Breitenstein (brandon.breitenstein(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18046 -gerrit commit fb40f934e46308c2393fb1221e5b1a0ff9cd10fe Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Date: Thu Jan 5 12:47:27 2017 -0800 apollolake: Update UPD header files for FSP 1.3.0 These updated header files contain USB tuning parameters as well as some general cleanup of unused parameters in the UPD Headers. This patch along with the upcoming FSP 1.3.0 release will allow for USB tuning on apollolake platforms. Change-Id: Id7cce1ea83057630d508523ada18c5425804535e Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- .../intel/fsp/fsp2_0/apollolake/FspmUpd.h | 36 +------------ .../intel/fsp/fsp2_0/apollolake/FspsUpd.h | 59 ++++++++++++---------- 2 files changed, 33 insertions(+), 62 deletions(-) diff --git a/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspmUpd.h index d0620f5..3cfbd71 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspmUpd.h @@ -820,32 +820,6 @@ typedef struct { UINT8 ReservedFspmUpd[12]; } FSP_M_CONFIG; -/** Fsp M Test Configuration -**/ -typedef struct { - -/** Offset 0x0160 -**/ - UINT32 Signature; - -/** Offset 0x0164 -**/ - UINT8 ReservedFspmTestUpd[12]; -} FSP_M_TEST_CONFIG; - -/** Fsp M Restricted Configuration -**/ -typedef struct { - -/** Offset 0x0170 -**/ - UINT32 Signature; - -/** Offset 0x0174 -**/ - UINT8 ReservedFspmRestrictedUpd[124]; -} FSP_M_RESTRICTED_CONFIG; - /** Fsp M UPD Configuration **/ typedef struct { @@ -864,15 +838,7 @@ typedef struct { /** Offset 0x0160 **/ - FSP_M_TEST_CONFIG FspmTestConfig; - -/** Offset 0x0170 -**/ - FSP_M_RESTRICTED_CONFIG FspmRestrictedConfig; - -/** Offset 0x01F0 -**/ - UINT8 UnusedUpdSpace2[14]; + UINT8 UnusedUpdSpace2[158]; /** Offset 0x01FE **/ diff --git a/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspsUpd.h index 8a4fe1a..82a224d 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/apollolake/FspsUpd.h @@ -1521,34 +1521,47 @@ typedef struct { /** Offset 0x0334 **/ - UINT8 ReservedFspsUpd[12]; -} FSP_S_CONFIG; + UINT8 UnusedUpdSpace7[4]; -/** Fsp S Test Configuration +/** Offset 0x0338 - PerPort Half Bit Pre-emphasis + PerPort Half Bit Pre-emphasis. Value of register USB2_PER_PORT_PPX [14] **/ -typedef struct { + UINT8 PortUsb20PerPortTxPeHalf[8]; -/** Offset 0x0340 +/** Offset 0x0340 - PerPort HS Pre-emphasis Bias + PerPort HS Pre-emphasis Bias. Value of register USB2_PER_PORT_PPX [13:11] **/ - UINT32 Signature; + UINT8 PortUsb20PerPortPeTxiSet[8]; -/** Offset 0x0344 +/** Offset 0x0348 - PerPort HS Transmitter Bias + PerPort HS Transmitter Bias. Value of register USB2_PER_PORT_PPX [10:8] **/ - UINT8 ReservedFspsTestUpd[12]; -} FSP_S_TEST_CONFIG; + UINT8 PortUsb20PerPortTxiSet[8]; -/** Fsp S Restricted Configuration +/** Offset 0x0350 - Select the skew direction for HS transition + Select the skew direction for HS transition. Value of register USB2_PER_PORT_2_PPX [25] **/ -typedef struct { + UINT8 PortUsb20HsSkewSel[8]; + +/** Offset 0x0358 - Per Port HS Transmitter Emphasis + Per Port HS Transmitter Emphasis. Value of register USB2_PER_PORT_2_PPX [24:23] +**/ + UINT8 PortUsb20IUsbTxEmphasisEn[8]; + +/** Offset 0x0360 - PerPort HS Receiver Bias + PerPort HS Receiver Bias. Value of register USB2_PER_PORT_2_PPX [19:17] +**/ + UINT8 PortUsb20PerPortRXISet[8]; -/** Offset 0x0350 +/** Offset 0x0368 - Delay/skew's strength control for HS driver + Delay/skew's strength control for HS driver. Value of register USB2_PER_PORT_2_PPX [1:0] **/ - UINT32 Signature; + UINT8 PortUsb20HsNpreDrvSel[8]; -/** Offset 0x0354 +/** Offset 0x0370 **/ - UINT8 ReservedFspsRestrictedUpd[12]; -} FSP_S_RESTRICTED_CONFIG; + UINT8 ReservedFspsUpd[16]; +} FSP_S_CONFIG; /** Fsp S UPD Configuration **/ @@ -1562,19 +1575,11 @@ typedef struct { **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x0340 -**/ - FSP_S_TEST_CONFIG FspsTestConfig; - -/** Offset 0x0350 -**/ - FSP_S_RESTRICTED_CONFIG FspsRestrictedConfig; - -/** Offset 0x0360 +/** Offset 0x0380 **/ - UINT8 UnusedUpdSpace7[14]; + UINT8 UnusedUpdSpace8[46]; -/** Offset 0x036E +/** Offset 0x03AE **/ UINT16 UpdTerminator; } FSPS_UPD;

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New patch to review for coreboot: commonlib/cbfs: remove cbfs_vb2_hash_contents() function
by Aaron Durbin 05 Jan '17

05 Jan '17

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18045 -gerrit commit e86abde15c1e57632faeac56fd5fcfb9b71c9485 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jan 5 13:20:15 2017 -0600 commonlib/cbfs: remove cbfs_vb2_hash_contents() function Things will still fail to build because of internal usage vb2 hashing functions. Change-Id: Id467d46223f9c7ab19beff88be579321ebfe4cbe Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/commonlib/cbfs.c | 56 ---------------------------------- src/commonlib/include/commonlib/cbfs.h | 10 ------ 2 files changed, 66 deletions(-) diff --git a/src/commonlib/cbfs.c b/src/commonlib/cbfs.c index 1db8d31..76d5143 100644 --- a/src/commonlib/cbfs.c +++ b/src/commonlib/cbfs.c @@ -314,59 +314,3 @@ static int cbfs_extend_hash_master_header(struct vb2_digest_context *ctx, return cbfs_extend_hash_with_offset(ctx, cbfs, &rdev); } - -int cbfs_vb2_hash_contents(const struct region_device *cbfs, - enum vb2_hash_algorithm hash_alg, void *digest, - size_t digest_sz) -{ - struct vb2_digest_context ctx; - int rv; - struct cbfsf f; - struct cbfsf *prev; - struct cbfsf *fh; - - rv = vb2_digest_init(&ctx, hash_alg); - - if (rv) - return rv; - - rv = cbfs_extend_hash_master_header(&ctx, cbfs); - if (rv) - return rv; - - prev = NULL; - fh = &f; - - while (1) { - uint32_t ftype; - - rv = cbfs_for_each_file(cbfs, prev, fh); - prev = fh; - - if (rv < 0) - return VB2_ERROR_UNKNOWN; - - /* End of CBFS. */ - if (rv > 0) - break; - - rv = cbfs_extend_hash_with_offset(&ctx, cbfs, &fh->metadata); - - if (rv) - return rv; - - /* Include data contents in hash if file is non-empty. */ - if (cbfsf_file_type(fh, &ftype)) - return VB2_ERROR_UNKNOWN; - - if (ftype == CBFS_TYPE_DELETED || ftype == CBFS_TYPE_DELETED2) - continue; - - rv = cbfs_extend_hash_with_offset(&ctx, cbfs, &fh->data); - - if (rv) - return rv; - } - - return vb2_digest_finalize(&ctx, digest, digest_sz); -} diff --git a/src/commonlib/include/commonlib/cbfs.h b/src/commonlib/include/commonlib/cbfs.h index 163bef2..87a4000 100644 --- a/src/commonlib/include/commonlib/cbfs.h +++ b/src/commonlib/include/commonlib/cbfs.h @@ -18,7 +18,6 @@ #include <commonlib/cbfs_serialized.h> #include <commonlib/region.h> -#include <vb2_api.h> /* Object representing cbfs files. */ struct cbfsf { @@ -70,13 +69,4 @@ size_t cbfs_for_each_attr(void *metadata, size_t metadata_size, */ int cbfsf_decompression_info(struct cbfsf *fh, uint32_t *algo, size_t *size); -/* - * Perform the vb2 hash over the CBFS region skipping empty file contents. - * Caller is responsible for providing the hash algorithm as well as storage - * for the final digest. Return 0 on success or non-zero on error. - */ -int cbfs_vb2_hash_contents(const struct region_device *cbfs, - enum vb2_hash_algorithm hash_alg, void *digest, - size_t digest_sz); - #endif

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Patch merged into coreboot/master: mb/ga-m57sli-s4: Fix early uart output
by gerrit＠coreboot.org 05 Jan '17

05 Jan '17

the following patch was just integrated into master: commit d502dc092a26726472fc5871c77ebff192be4cb8 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Tue Dec 27 01:08:02 2016 +0100 mb/ga-m57sli-s4: Fix early uart output The console output is garbled until it is fixed in ramstage by devicetree which sets the uart clock predivider correctly. Change-Id: I6d6ec0febfec98a8d4a71e1476036c804cf5f08d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/17969 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See https://review.coreboot.org/17969 for details. -gerrit

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New patch to review for coreboot: nb/intel/*/northbridge.c: Remove #include <device/hypertransport.h>
by Arthur Heymans 05 Jan '17

05 Jan '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18044 -gerrit commit 71b169163856c962e93a30e384503701acd1178d Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Jan 5 17:07:33 2017 +0100 nb/intel/*/northbridge.c: Remove #include <device/hypertransport.h> Nothing from that header is used or even declared since CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not selected on Intel hardware. Change-Id: I9101eb6ffa6664a2ab45bc0b247279c916266537 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/fsp_sandybridge/northbridge.c | 1 - src/northbridge/intel/gm45/northbridge.c | 1 - src/northbridge/intel/haswell/northbridge.c | 1 - src/northbridge/intel/i3100/northbridge.c | 1 - src/northbridge/intel/i945/northbridge.c | 1 - src/northbridge/intel/nehalem/northbridge.c | 1 - src/northbridge/intel/pineview/northbridge.c | 1 - src/northbridge/intel/sandybridge/northbridge.c | 1 - src/northbridge/intel/x4x/northbridge.c | 1 - src/soc/intel/sch/northbridge.c | 1 - 10 files changed, 10 deletions(-) diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c index 92a4365..a565b8d 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.c +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c @@ -25,7 +25,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/hypertransport.h> #include <stdlib.h> #include <string.h> #include <cpu/cpu.h> diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index af62f12..3cb7d11 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -19,7 +19,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/hypertransport.h> #include <stdlib.h> #include <string.h> #include <cpu/cpu.h> diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index d4b6e90..63cbb70 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -24,7 +24,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/hypertransport.h> #include <stdlib.h> #include <string.h> #include <cpu/cpu.h> diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c index d5eb8a6..3663c11 100644 --- a/src/northbridge/intel/i3100/northbridge.c +++ b/src/northbridge/intel/i3100/northbridge.c @@ -22,7 +22,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/hypertransport.h> #include <stdlib.h> #include <string.h> #include <cbmem.h> diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 5092b17..f6c3364 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -19,7 +19,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/hypertransport.h> #include <stdlib.h> #include <string.h> #include <cbmem.h> diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 8a64aa3..83c6506 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -26,7 +26,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/hypertransport.h> #include <stdlib.h> #include <string.h> #include <cpu/cpu.h> diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index bf35731..6fc841c 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -20,7 +20,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/hypertransport.h> #include <stdlib.h> #include <string.h> #include <cpu/cpu.h> diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 71dd802..562e7f2 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -25,7 +25,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/hypertransport.h> #include <stdlib.h> #include <string.h> #include <cpu/cpu.h> diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 15e150e..1c220b2 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -20,7 +20,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/hypertransport.h> #include <stdlib.h> #include <string.h> #include <cpu/cpu.h> diff --git a/src/soc/intel/sch/northbridge.c b/src/soc/intel/sch/northbridge.c index 0bc840d..db19b18 100644 --- a/src/soc/intel/sch/northbridge.c +++ b/src/soc/intel/sch/northbridge.c @@ -19,7 +19,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/hypertransport.h> #include <stdlib.h> #include <string.h> #include <cbmem.h>

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New patch to review for coreboot: arch/x86: fix cmos post logging in non romcc bootblock
by Aaron Durbin 05 Jan '17

05 Jan '17

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18043 -gerrit commit fe8305fe35de5af66f77f850865860e085b747f2 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jan 5 10:07:19 2017 -0600 arch/x86: fix cmos post logging in non romcc bootblock cmos_post_init() is called in src/arch/x86/bootblock_simple.c, and that function is reponsible for bootstrapping the cmos post register contents. Without this function being called none of the cmos post functionality works correctly. Therefore, add a call to lib/bootblock.c which the C_ENVIRONMENT_BOOTBLOCK SoCs use. BUG=chrome-os-partner:61546 Change-Id: I2e3519f2f3f2c28e5cba26b5811f1eb0c2a90572 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/include/arch/bootblock_romcc.h | 26 -------------------------- src/include/pc80/mc146818rtc.h | 29 +++++++++++++++++++++++++++++ src/lib/bootblock.c | 3 +++ 3 files changed, 32 insertions(+), 26 deletions(-) diff --git a/src/arch/x86/include/arch/bootblock_romcc.h b/src/arch/x86/include/arch/bootblock_romcc.h index 54e05a1..eab8a0d 100644 --- a/src/arch/x86/include/arch/bootblock_romcc.h +++ b/src/arch/x86/include/arch/bootblock_romcc.h @@ -62,29 +62,3 @@ static void sanitize_cmos(void) } } #endif - -#if CONFIG_CMOS_POST -static void cmos_post_init(void) -{ - u8 magic = CMOS_POST_BANK_0_MAGIC; - - /* Switch to the other bank */ - switch (cmos_read(CMOS_POST_BANK_OFFSET)) { - case CMOS_POST_BANK_1_MAGIC: - break; - case CMOS_POST_BANK_0_MAGIC: - magic = CMOS_POST_BANK_1_MAGIC; - break; - default: - /* Initialize to zero */ - cmos_write(0, CMOS_POST_BANK_0_OFFSET); - cmos_write(0, CMOS_POST_BANK_1_OFFSET); -#if CONFIG_CMOS_POST_EXTRA - cmos_write32(CMOS_POST_BANK_0_EXTRA, 0); - cmos_write32(CMOS_POST_BANK_1_EXTRA, 0); -#endif - } - - cmos_write(magic, CMOS_POST_BANK_OFFSET); -} -#endif diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 66d5edb..99fba9d 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -221,10 +221,39 @@ unsigned read_option_lowlevel(unsigned start, unsigned size, unsigned def); #define CMOS_POST_EXTRA_DEV_PATH 0x01 void cmos_post_log(void); + +/* cmos_post_init() is exposed in this manner because it also needs to be called + * by bootblock code compiled by romcc. */ +static inline void cmos_post_init(void) +{ + u8 magic = CMOS_POST_BANK_0_MAGIC; + + /* Switch to the other bank */ + switch (cmos_read(CMOS_POST_BANK_OFFSET)) { + case CMOS_POST_BANK_1_MAGIC: + break; + case CMOS_POST_BANK_0_MAGIC: + magic = CMOS_POST_BANK_1_MAGIC; + break; + default: + /* Initialize to zero */ + cmos_write(0, CMOS_POST_BANK_0_OFFSET); + cmos_write(0, CMOS_POST_BANK_1_OFFSET); +#if CONFIG_CMOS_POST_EXTRA + cmos_write32(CMOS_POST_BANK_0_EXTRA, 0); + cmos_write32(CMOS_POST_BANK_1_EXTRA, 0); +#endif + } + + cmos_write(magic, CMOS_POST_BANK_OFFSET); +} #else static inline void cmos_post_log(void) {} +static inline void cmos_post_init(void) {} #endif /* CONFIG_CMOS_POST */ +#else /* !CONFIG_ARCH_X86 */ +static inline void cmos_post_init(void) {} #endif /* CONFIG_ARCH_X86 */ #endif /* PC80_MC146818RTC_H */ diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c index 9dece0c..a560152 100644 --- a/src/lib/bootblock.c +++ b/src/lib/bootblock.c @@ -18,6 +18,7 @@ #include <bootblock_common.h> #include <console/console.h> #include <delay.h> +#include <pc80/mc146818rtc.h> #include <program_loading.h> #include <symbols.h> #include <timestamp.h> @@ -35,6 +36,8 @@ void asmlinkage bootblock_main_with_timestamp(uint64_t base_timestamp) if (IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) && _timestamp_size > 0) timestamp_init(base_timestamp); + cmos_post_init(); + bootblock_soc_early_init(); bootblock_mainboard_early_init();

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Patch set updated for coreboot: nb/intel/x4x: Fix raminit on reset path
by Arthur Heymans 05 Jan '17

05 Jan '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18009 -gerrit commit eca3f656cef8e108e36387d2509c05c069561cb4 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Wed Nov 30 18:40:38 2016 +0100 nb/intel/x4x: Fix raminit on reset path Previously the raminit failed on hot reset and to work around this issue it unconditionally did a cold reset. This has the following issues: * it's slow; * when the OS issues a hot reset some disk drives expect their 5V power supply to remain on, which gets cut off by a cold reset, causing data corruption. To fix this some steps in raminit must be ommited on the reset path. This includes searching for receive enable. To achieve this it stores receive enable results in nvram (which is also needed when implementing S3 suspend/resume from S3). Change-Id: I6601dd90aebd071a0de7cec070487b0f9845bc30 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout | 2 + src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 7 +- src/northbridge/intel/x4x/raminit_ddr2.c | 135 ++++++++++++++++++++---- src/northbridge/intel/x4x/x4x.h | 7 +- 4 files changed, 126 insertions(+), 25 deletions(-) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout index 3138479..bc5f3df 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout +++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout @@ -68,6 +68,8 @@ entries # coreboot config options: check sums 984 16 h 0 check_sum +# RAM initialization internal data +1024 256 r 0 recv_enable_results # ----------------------------------------------------------------- enumerations diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index 2503db9..2302842 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -29,6 +29,7 @@ #include <lib.h> #include <arch/stages.h> #include <cbmem.h> +#include <northbridge/intel/x4x/iomap.h> #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) @@ -136,6 +137,7 @@ void mainboard_romstage_entry(unsigned long bist) { // ch0 ch1 const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; + u8 boot_path = 0; /* Disable watchdog timer */ RCBA32(0x3410) = RCBA32(0x3410) | 0x20; @@ -155,8 +157,11 @@ void mainboard_romstage_entry(unsigned long bist) x4x_early_init(); + if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) + boot_path = BOOT_PATH_RESET; + printk(BIOS_DEBUG, "Initializing memory\n"); - sdram_initialize(0, spd_addrmap); + sdram_initialize(boot_path, spd_addrmap); quick_ram_check(); cbmem_initialize_empty(); printk(BIOS_DEBUG, "Memory initialized\n"); diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index b3ee34a..ef21cb8 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -20,6 +20,9 @@ #include <console/console.h> #include <commonlib/helpers.h> #include <delay.h> +#include <pc80/mc146818rtc.h> +/* only needed for RCBA32() so it's ok to only include ICH7 function */ +#include <southbridge/intel/i82801gx/i82801gx.h> #include "iomap.h" #include "x4x.h" @@ -258,10 +261,13 @@ static void checkreset_ddr2(struct sysinfo *s) { u8 pmcon2; u8 reset = 0; + u32 pmir; + pmir = pci_read_config32(PCI_DEV(0, 0x1f, 0), 0xac); pmcon2 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); - if (!(pmcon2 & 0x80)) { - pmcon2 |= 0x80; + + if (pmcon2 & 0x80) { + pmcon2 &= ~0x80; pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); reset = 1; @@ -273,10 +279,16 @@ static void checkreset_ddr2(struct sysinfo *s) } if (reset) { printk(BIOS_DEBUG, "Reset...\n"); + /* Do a global reset. only useful on ICH10 */ + pmir |= (1 << 20); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, pmir); outb(0xe, 0xcf9); asm ("hlt"); } - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2 | 0x80); + pmir &= ~(1 << 20); + pmcon2 |= 0x80; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, pmir); } static void setioclk_ddr2(struct sysinfo *s) @@ -1486,6 +1498,76 @@ static void rcven_ddr2(struct sysinfo *s) printk(BIOS_DEBUG, "End rcven\n"); } +static void sdram_save_receive_enable(void) +{ + int i = 0, j; + u32 reg32; + u16 reg16; + u8 values[32]; + u8 lane, ch; + + FOR_EACH_CHANNEL(ch) { + for (lane = 0; lane < 8; lane++) + values[i++] = MCHBAR8(0x400*ch + 0x560 + (lane*4)); + reg32 = MCHBAR32(0x400*ch + 0x248); + for (j = 0; j < 4; j++) + values[i++] = (reg32 >> (j * 8)) & 0xff; + reg16 = MCHBAR16(0x400*ch + 0x5fa); + for (j = 0; j < 2; j++) + values[i++] = (reg16 >> (j * 8)) & 0xff; + reg16 = MCHBAR16(0x400*ch + 0x58c); + for (j = 0; j < 2; j++) + values[i++] = (reg16 >> (j * 8)) & 0xff; + } + + for (i = 0; i < ARRAY_SIZE(values); i++) + cmos_write(values[i], 128 + i); +} + +static void sdram_recover_receive_enable(void) +{ + u8 i, j; + u32 reg32 = 0; + u16 reg16 = 0; + u8 values[32]; + u8 ch, lane; + + for (i = 0; i < ARRAY_SIZE(values); i++) + values[i] = cmos_read(128 + i); + + i = 0; + FOR_EACH_CHANNEL(ch) { + for (lane = 0; lane < 8; lane++) + MCHBAR8(0x400*ch + 0x560 + (lane*4)) = values[i++]; + for (j = 0; j < 4; j++) + reg32 |= (values[i++] << (j * 8)); + MCHBAR32(0x400*ch + 0x248) = reg32; + reg32 = 0; + for (j = 0; j < 2; j++) + reg16 |= (values[i++] << (j * 8)); + MCHBAR16(0x400*ch + 0x5fa) = reg16; + reg16 = 0; + for (j = 0; j < 2; j++) + reg16 |= (values[i++] << (j * 8)); + MCHBAR16(0x400*ch + 0x58c) = reg16; + reg16 = 0; + } +} + +static void sdram_program_receive_enable(struct sysinfo *s) +{ + /* enable upper CMOS */ + RCBA32(0x3400) = (1 << 2); + + /* Program Receive Enable Timings */ + if (s->boot_path == BOOT_PATH_RESET) { + sdram_recover_receive_enable(); + } else { + rcven_ddr2(s); + sdram_save_receive_enable(); + } +} + static void dradrb_ddr2(struct sysinfo *s) { u8 map, i, ch, r, rankpop0, rankpop1; @@ -1860,22 +1942,24 @@ void raminit_ddr2(struct sysinfo *s) checkreset_ddr2(s); // Clear self refresh - MCHBAR32(0xf14) = MCHBAR32(0xf14) | 0x3; + if (s->boot_path != BOOT_PATH_RESET) { + MCHBAR32(PMSTS_MCHBAR) = MCHBAR32(PMSTS_MCHBAR) + | PMSTS_BOTH_SELFREFRESH; - // Clear host clk gate reg - MCHBAR32(0x1c) = MCHBAR32(0x1c) | 0xffffffff; + // Clear host clk gate reg + MCHBAR32(0x1c) = MCHBAR32(0x1c) | 0xffffffff; - // Select DDR2 - MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x4; + // Select DDR2 + MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x4; - // Set freq - MCHBAR32(0xc00) = (MCHBAR32(0xc00) & ~0x70) | - (s->selected_timings.mem_clk << 4) | (1 << 10); + // Set freq + MCHBAR32(0xc00) = (MCHBAR32(0xc00) & ~0x70) | + (s->selected_timings.mem_clk << 4) | (1 << 10); - // Overwrite freq if chipset rejects it - s->selected_timings.mem_clk = (MCHBAR8(0xc00) & 0x70) >> 4; - if (s->selected_timings.mem_clk > (s->max_fsb + 3)) { - die("Error: DDR is faster than FSB, halt\n"); + // Overwrite freq if chipset rejects it + s->selected_timings.mem_clk = (MCHBAR8(0xc00) & 0x70) >> 4; + if (s->selected_timings.mem_clk > (s->max_fsb + 3)) + die("Error: DDR is faster than FSB, halt\n"); } udelay(250000); @@ -1885,8 +1969,10 @@ void raminit_ddr2(struct sysinfo *s) printk(BIOS_DEBUG, "Done clk crossing\n"); // DDR2 IO - setioclk_ddr2(s); - printk(BIOS_DEBUG, "Done I/O clk\n"); + if (s->boot_path != BOOT_PATH_RESET) { + setioclk_ddr2(s); + printk(BIOS_DEBUG, "Done I/O clk\n"); + } // Grant to launch launch_ddr2(s); @@ -1900,16 +1986,21 @@ void raminit_ddr2(struct sysinfo *s) dll_ddr2(s); // RCOMP - rcomp_ddr2(s); - printk(BIOS_DEBUG, "RCOMP\n"); + if (s->boot_path != BOOT_PATH_RESET) { + rcomp_ddr2(s); + printk(BIOS_DEBUG, "RCOMP\n"); + } // ODT odt_ddr2(s); printk(BIOS_DEBUG, "Done ODT\n"); // RCOMP update - while ((MCHBAR8(0x130) & 1) != 0 ); - printk(BIOS_DEBUG, "Done RCOMP update\n"); + if (s->boot_path != BOOT_PATH_RESET) { + while ((MCHBAR8(0x130) & 1) != 0) + ; + printk(BIOS_DEBUG, "Done RCOMP update\n"); + } // Set defaults MCHBAR32(0x260) = (MCHBAR32(0x260) & ~1) | 0xf00000; @@ -1989,7 +2080,7 @@ void raminit_ddr2(struct sysinfo *s) } // Receive enable - rcven_ddr2(s); + sdram_program_receive_enable(s); printk(BIOS_DEBUG, "Done rcven\n"); // Finish rcven diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 7ca634f..1823b8c 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -87,8 +87,8 @@ #define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) #define PMSTS_MCHBAR 0x0f14 /* Self refresh channel status */ -#define PMSTS_WARM_RESET (1 << 1) -#define PMSTS_BOTH_SELFREFRESH (1 << 0) +#define PMSTS_WARM_RESET (1 << 8) +#define PMSTS_BOTH_SELFREFRESH (3 << 0) #define CLKCFG_MCHBAR 0x0c00 #define CLKCFG_FSBCLK_SHIFT 0 @@ -290,6 +290,9 @@ struct sysinfo { struct dimminfo dimms[4]; u8 spd_map[4]; }; +#define BOOT_PATH_NORMAL 0 +#define BOOT_PATH_RESET 1 +#define BOOT_PATH_RESUME 2 enum ddr2_signals { CLKSET0 = 0,

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Patch set updated for coreboot: payloads/external/SeaBIOS: Bump version to 1.10.1
by Philipp Deppenwiese 04 Jan '17

04 Jan '17

Philipp Deppenwiese (zaolin.daisuki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18026 -gerrit commit cd8d28405685c6381c7f5ac471a6369c09065dbb Author: Philipp Deppenwiese <zaolin(a)das-labor.org> Date: Wed Jan 4 00:30:38 2017 +0100 payloads/external/SeaBIOS: Bump version to 1.10.1 Changes since SeaBIOS 1.9.3 Release 1.10.0: * Initial support for Trusted Platform Module (TPM) version 2.0 * Several USB XHCI timing fixes on real hardware * Support for "LSI MPT Fusion" scsi controllers on QEMU * Support for virtio devices mapped above 4GB * Several bug fixes and code cleanups Release 1.10.1: * Updates for QEMU for reproducible builds Change-Id: I465700307d72fa44b6900b38b332603ea505ed09 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- payloads/external/SeaBIOS/Kconfig | 2 +- payloads/external/SeaBIOS/Makefile | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index 0780820..ac4f922 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -5,7 +5,7 @@ choice default SEABIOS_STABLE config SEABIOS_STABLE - bool "1.9.3" + bool "1.10.1" help Stable SeaBIOS version config SEABIOS_MASTER diff --git a/payloads/external/SeaBIOS/Makefile b/payloads/external/SeaBIOS/Makefile index 9ec3e60..4b108d5 100644 --- a/payloads/external/SeaBIOS/Makefile +++ b/payloads/external/SeaBIOS/Makefile @@ -1,5 +1,5 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master -TAG-$(CONFIG_SEABIOS_STABLE)=e2fc41e24ee0ada60fc511d60b15a41b294538be +TAG-$(CONFIG_SEABIOS_STABLE)=8891697e3f7d84355420573efd98e94f14736768 TAG-$(CONFIG_SEABIOS_REVISION)=$(CONFIG_SEABIOS_REVISION_ID) project_git_repo=https://review.coreboot.org/p/seabios.git

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coreboot-gerrit January 2017